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tcg/mips: Try three insns with shift and add in tcg_out_movi
These sequences are inexpensive to test. Maxing out at three insns results in the same space as a load plus the constant pool entry. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -569,6 +569,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
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tcg_target_long arg, TCGReg tbreg)
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{
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tcg_target_long tmp;
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int sh, lo;
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if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
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arg = (int32_t)arg;
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@ -591,6 +592,49 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
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return;
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}
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/*
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* Load bitmasks with a right-shift. This is good for things
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* like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4.
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* or similarly using LUI. For this to work, bit 31 must be set.
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*/
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if (arg > 0 && (int32_t)arg < 0) {
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sh = clz64(arg);
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if (tcg_out_movi_one(s, ret, arg << sh)) {
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tcg_out_dsrl(s, ret, ret, sh);
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return;
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}
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}
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/*
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* Load slightly larger constants using left-shift.
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* Limit this sequence to 3 insns to avoid too much expansion.
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*/
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sh = ctz64(arg);
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if (sh && tcg_out_movi_two(s, ret, arg >> sh)) {
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tcg_out_dsll(s, ret, ret, sh);
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return;
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}
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/*
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* Load slightly larger constants using left-shift and add/or.
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* Prefer addi with a negative immediate when that would produce
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* a larger shift. For this to work, bits 15 and 16 must be set.
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*/
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lo = arg & 0xffff;
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if (lo) {
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if ((arg & 0x18000) == 0x18000) {
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lo = (int16_t)arg;
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}
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tmp = arg - lo;
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sh = ctz64(tmp);
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tmp >>= sh;
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if (tcg_out_movi_one(s, ret, tmp)) {
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tcg_out_dsll(s, ret, ret, sh);
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tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo);
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return;
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}
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}
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/* Otherwise, put 64-bit constants into the constant pool. */
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tcg_out_movi_pool(s, ret, arg, tbreg);
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}
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