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hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals
Booting using "Direct Kernel Boot" for PolarFire SoC & skipping u-boot entirely is probably not advisable, but it does at least show signs of life. Recent Linux kernel versions make use of peripherals that are missing definitions in QEMU and lead to kernel panics. These issues almost certain rear their head for other methods of booting, but I was unable to figure out a suitable HSS version that is recent enough to support these peripherals & works with QEMU. With these peripherals added, booting a kernel with the following hangs hangs waiting for the system controller's hwrng, but the kernel no longer panics. With the Linux driver for hwrng disabled, it boots to console. qemu-system-riscv64 -M microchip-icicle-kit \ -m 2G -smp 5 \ -kernel $(vmlinux_bin) \ -dtb $(dtb)\ -initrd $(initramfs) \ -display none -serial null \ -serial stdio More peripherals are added than strictly required to fix the panics in the hopes of avoiding a replication of this problem in the future. Some of the peripherals which are in the device tree for recent kernels are implemented in the FPGA fabric. The eMMC/SD mux, which exists as an unimplemented device is replaced by a wider entry. This updated entry covers both the mux & the remainder of the FPGA fabric connected to the MSS using Fabric Interrconnect (FIC) 3. Link: https://github.com/polarfire-soc/icicle-kit-reference-design#fabric-memory-map Link: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/SupportingCollateral/V1_4_Register_Map.zip Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220813135127.2971754-1-mail@conchuod.ie> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Conor Dooley
Alistair Francis
parent
bf8803c64d
commit
25da6e3113
@ -100,8 +100,11 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
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[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
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[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
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[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
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[MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 },
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[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
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[MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 },
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[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
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[MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 },
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[MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
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[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
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[MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
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@ -109,19 +112,28 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
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[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
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[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
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[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
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[MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 },
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[MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 },
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[MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 },
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[MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 },
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[MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
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[MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
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[MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 },
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[MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
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[MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 },
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[MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 },
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[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
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[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
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[MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
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[MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
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[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
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[MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 },
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[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
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[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
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[MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 },
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[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
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[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
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[MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 },
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[MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 },
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[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
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[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
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[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
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@ -292,11 +304,21 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
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memmap[MICROCHIP_PFSOC_SYSREG].base);
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/* AXISW */
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create_unimplemented_device("microchip.pfsoc.axisw",
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memmap[MICROCHIP_PFSOC_AXISW].base,
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memmap[MICROCHIP_PFSOC_AXISW].size);
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/* MPUCFG */
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create_unimplemented_device("microchip.pfsoc.mpucfg",
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memmap[MICROCHIP_PFSOC_MPUCFG].base,
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memmap[MICROCHIP_PFSOC_MPUCFG].size);
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/* FMETER */
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create_unimplemented_device("microchip.pfsoc.fmeter",
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memmap[MICROCHIP_PFSOC_FMETER].base,
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memmap[MICROCHIP_PFSOC_FMETER].size);
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/* DDR SGMII PHY */
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sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
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@ -336,6 +358,23 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
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qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
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serial_hd(4));
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/* Watchdogs */
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create_unimplemented_device("microchip.pfsoc.watchdog0",
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memmap[MICROCHIP_PFSOC_WDOG0].base,
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memmap[MICROCHIP_PFSOC_WDOG0].size);
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create_unimplemented_device("microchip.pfsoc.watchdog1",
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memmap[MICROCHIP_PFSOC_WDOG1].base,
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memmap[MICROCHIP_PFSOC_WDOG1].size);
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create_unimplemented_device("microchip.pfsoc.watchdog2",
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memmap[MICROCHIP_PFSOC_WDOG2].base,
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memmap[MICROCHIP_PFSOC_WDOG2].size);
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create_unimplemented_device("microchip.pfsoc.watchdog3",
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memmap[MICROCHIP_PFSOC_WDOG3].base,
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memmap[MICROCHIP_PFSOC_WDOG3].size);
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create_unimplemented_device("microchip.pfsoc.watchdog4",
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memmap[MICROCHIP_PFSOC_WDOG4].base,
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memmap[MICROCHIP_PFSOC_WDOG4].size);
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/* SPI */
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create_unimplemented_device("microchip.pfsoc.spi0",
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memmap[MICROCHIP_PFSOC_SPI0].base,
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@ -344,11 +383,27 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
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memmap[MICROCHIP_PFSOC_SPI1].base,
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memmap[MICROCHIP_PFSOC_SPI1].size);
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/* I2C1 */
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/* I2C */
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create_unimplemented_device("microchip.pfsoc.i2c0",
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memmap[MICROCHIP_PFSOC_I2C0].base,
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memmap[MICROCHIP_PFSOC_I2C0].size);
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create_unimplemented_device("microchip.pfsoc.i2c1",
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memmap[MICROCHIP_PFSOC_I2C1].base,
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memmap[MICROCHIP_PFSOC_I2C1].size);
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/* CAN */
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create_unimplemented_device("microchip.pfsoc.can0",
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memmap[MICROCHIP_PFSOC_CAN0].base,
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memmap[MICROCHIP_PFSOC_CAN0].size);
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create_unimplemented_device("microchip.pfsoc.can1",
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memmap[MICROCHIP_PFSOC_CAN1].base,
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memmap[MICROCHIP_PFSOC_CAN1].size);
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/* USB */
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create_unimplemented_device("microchip.pfsoc.usb",
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memmap[MICROCHIP_PFSOC_USB].base,
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memmap[MICROCHIP_PFSOC_USB].size);
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/* GEMs */
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nd = &nd_table[0];
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@ -402,10 +457,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
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memmap[MICROCHIP_PFSOC_IOSCB].base);
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/* eMMC/SD mux */
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create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
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memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
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memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
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/* FPGA Fabric */
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create_unimplemented_device("microchip.pfsoc.fabricfic3",
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memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base,
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memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size);
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/* QSPI Flash */
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memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
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@ -88,8 +88,11 @@ enum {
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MICROCHIP_PFSOC_L2LIM,
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MICROCHIP_PFSOC_PLIC,
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MICROCHIP_PFSOC_MMUART0,
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MICROCHIP_PFSOC_WDOG0,
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MICROCHIP_PFSOC_SYSREG,
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MICROCHIP_PFSOC_AXISW,
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MICROCHIP_PFSOC_MPUCFG,
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MICROCHIP_PFSOC_FMETER,
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MICROCHIP_PFSOC_DDR_SGMII_PHY,
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MICROCHIP_PFSOC_EMMC_SD,
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MICROCHIP_PFSOC_DDR_CFG,
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@ -97,19 +100,28 @@ enum {
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MICROCHIP_PFSOC_MMUART2,
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MICROCHIP_PFSOC_MMUART3,
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MICROCHIP_PFSOC_MMUART4,
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MICROCHIP_PFSOC_WDOG1,
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MICROCHIP_PFSOC_WDOG2,
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MICROCHIP_PFSOC_WDOG3,
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MICROCHIP_PFSOC_WDOG4,
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MICROCHIP_PFSOC_SPI0,
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MICROCHIP_PFSOC_SPI1,
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MICROCHIP_PFSOC_I2C0,
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MICROCHIP_PFSOC_I2C1,
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MICROCHIP_PFSOC_CAN0,
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MICROCHIP_PFSOC_CAN1,
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MICROCHIP_PFSOC_GEM0,
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MICROCHIP_PFSOC_GEM1,
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MICROCHIP_PFSOC_GPIO0,
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MICROCHIP_PFSOC_GPIO1,
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MICROCHIP_PFSOC_GPIO2,
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MICROCHIP_PFSOC_RTC,
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MICROCHIP_PFSOC_ENVM_CFG,
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MICROCHIP_PFSOC_ENVM_DATA,
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MICROCHIP_PFSOC_USB,
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MICROCHIP_PFSOC_QSPI_XIP,
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MICROCHIP_PFSOC_IOSCB,
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MICROCHIP_PFSOC_EMMC_SD_MUX,
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MICROCHIP_PFSOC_FABRIC_FIC3,
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MICROCHIP_PFSOC_DRAM_LO,
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MICROCHIP_PFSOC_DRAM_LO_ALIAS,
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MICROCHIP_PFSOC_DRAM_HI,
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