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target/alpha: Implement CF_PCREL
-----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmY2VlYdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/IxQf/UAxpxtc+glkuZ17C mUliqx/Vif31BuKw31GVSDENOMteD900fR8+nNGY401+2hdZxoNo2N70ZL1h9AgX xWVz1H33MwBXbW3lWhGSpikJ/Sd3K7dsqZpRWlr1uUEFmNXDSihKgY3JfhJ4mEsq 8IIITyixSiiRyl1HBgfCUqLfHkWQamHz/Tbmku9wvOZ5fYkPHV1kCmlQ8X89iB9j yxHW9Zcm8cShD0w4pU1HZAttHhyNZrB70ebauksAWX6QIG6fdTv+qMz9XP4FofuT SwLuYja3ohoTijFkC7ctA0dbsF3xwCFKES6CdP8Ne5cKHSzsrejZhh8z/0uHi+D2 jwxnMg== =oK6Y -----END PGP SIGNATURE----- Merge tag 'pull-axp-20240504' of https://gitlab.com/rth7680/qemu into staging target/alpha: Implement CF_PCREL # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmY2VlYdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/IxQf/UAxpxtc+glkuZ17C # mUliqx/Vif31BuKw31GVSDENOMteD900fR8+nNGY401+2hdZxoNo2N70ZL1h9AgX # xWVz1H33MwBXbW3lWhGSpikJ/Sd3K7dsqZpRWlr1uUEFmNXDSihKgY3JfhJ4mEsq # 8IIITyixSiiRyl1HBgfCUqLfHkWQamHz/Tbmku9wvOZ5fYkPHV1kCmlQ8X89iB9j # yxHW9Zcm8cShD0w4pU1HZAttHhyNZrB70ebauksAWX6QIG6fdTv+qMz9XP4FofuT # SwLuYja3ohoTijFkC7ctA0dbsF3xwCFKES6CdP8Ne5cKHSzsrejZhh8z/0uHi+D2 # jwxnMg== # =oK6Y # -----END PGP SIGNATURE----- # gpg: Signature made Sat 04 May 2024 08:37:58 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-axp-20240504' of https://gitlab.com/rth7680/qemu: target/alpha: Implement CF_PCREL target/alpha: Split out gen_pc_disp target/alpha: Split out gen_goto_tb target/alpha: Simplify gen_bcond_internal() target/alpha: Return DISAS_NORETURN once target/alpha: Inline DISAS_PC_UPDATED and return DISAS_NORETURN target/alpha: Use DISAS_NEXT definition instead of magic '0' value target/alpha: Hoist branch shift to initial decode target/alpha: Use cpu_env in preference to ALPHA_CPU Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
248f6f62df
@ -28,25 +28,37 @@
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static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
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{
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AlphaCPU *cpu = ALPHA_CPU(cs);
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cpu->env.pc = value;
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CPUAlphaState *env = cpu_env(cs);
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env->pc = value;
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}
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static vaddr alpha_cpu_get_pc(CPUState *cs)
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{
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AlphaCPU *cpu = ALPHA_CPU(cs);
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CPUAlphaState *env = cpu_env(cs);
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return env->pc;
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}
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return cpu->env.pc;
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static void alpha_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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/* The program counter is always up to date with CF_PCREL. */
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if (!(tb_cflags(tb) & CF_PCREL)) {
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CPUAlphaState *env = cpu_env(cs);
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env->pc = tb->pc;
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}
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}
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static void alpha_restore_state_to_opc(CPUState *cs,
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const TranslationBlock *tb,
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const uint64_t *data)
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{
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AlphaCPU *cpu = ALPHA_CPU(cs);
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CPUAlphaState *env = cpu_env(cs);
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cpu->env.pc = data[0];
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if (tb_cflags(tb) & CF_PCREL) {
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env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
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} else {
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env->pc = data[0];
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}
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}
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static bool alpha_cpu_has_work(CPUState *cs)
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@ -81,6 +93,11 @@ static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
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AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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#ifndef CONFIG_USER_ONLY
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/* Use pc-relative instructions in system-mode */
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cs->tcg_cflags |= CF_PCREL;
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#endif
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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@ -193,6 +210,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
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static const TCGCPUOps alpha_tcg_ops = {
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.initialize = alpha_translate_init,
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.synchronize_from_tb = alpha_cpu_synchronize_from_tb,
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.restore_state_to_opc = alpha_restore_state_to_opc,
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#ifdef CONFIG_USER_ONLY
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@ -124,7 +124,7 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
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MMUAccessType access_type,
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bool maperr, uintptr_t retaddr)
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{
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AlphaCPU *cpu = ALPHA_CPU(cs);
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CPUAlphaState *env = cpu_env(cs);
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target_ulong mmcsr, cause;
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/* Assuming !maperr, infer the missing protection. */
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@ -155,9 +155,9 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
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}
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/* Record the arguments that PALcode would give to the kernel. */
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cpu->env.trap_arg0 = address;
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cpu->env.trap_arg1 = mmcsr;
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cpu->env.trap_arg2 = cause;
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env->trap_arg0 = address;
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env->trap_arg1 = mmcsr;
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env->trap_arg2 = cause;
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}
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#else
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/* Returns the OSF/1 entMM failure indication, or -1 on success. */
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@ -54,6 +54,9 @@ struct DisasContext {
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uint32_t tbflags;
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int mem_idx;
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/* True if generating pc-relative code. */
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bool pcrel;
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/* implver and amask values for this CPU. */
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int implver;
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int amask;
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@ -252,6 +255,16 @@ static void st_flag_byte(TCGv val, unsigned shift)
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tcg_gen_st8_i64(val, tcg_env, get_flag_ofs(shift));
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}
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static void gen_pc_disp(DisasContext *ctx, TCGv dest, int32_t disp)
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{
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uint64_t addr = ctx->base.pc_next + disp;
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if (ctx->pcrel) {
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tcg_gen_addi_i64(dest, cpu_pc, addr - ctx->base.pc_first);
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} else {
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tcg_gen_movi_i64(dest, addr);
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}
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}
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static void gen_excp_1(int exception, int error_code)
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{
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TCGv_i32 tmp1, tmp2;
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@ -263,7 +276,7 @@ static void gen_excp_1(int exception, int error_code)
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static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code)
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{
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tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
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gen_pc_disp(ctx, cpu_pc, 0);
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gen_excp_1(exception, error_code);
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return DISAS_NORETURN;
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}
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@ -425,60 +438,49 @@ static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,
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return DISAS_NEXT;
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}
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static bool use_goto_tb(DisasContext *ctx, uint64_t dest)
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static void gen_goto_tb(DisasContext *ctx, int idx, int32_t disp)
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{
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return translator_use_goto_tb(&ctx->base, dest);
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if (translator_use_goto_tb(&ctx->base, ctx->base.pc_next + disp)) {
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/* With PCREL, PC must always be up-to-date. */
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if (ctx->pcrel) {
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gen_pc_disp(ctx, cpu_pc, disp);
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tcg_gen_goto_tb(idx);
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} else {
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tcg_gen_goto_tb(idx);
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gen_pc_disp(ctx, cpu_pc, disp);
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}
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tcg_gen_exit_tb(ctx->base.tb, idx);
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} else {
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gen_pc_disp(ctx, cpu_pc, disp);
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tcg_gen_lookup_and_goto_ptr();
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}
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}
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static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp)
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{
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uint64_t dest = ctx->base.pc_next + (disp << 2);
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if (ra != 31) {
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tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next);
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gen_pc_disp(ctx, ctx->ir[ra], 0);
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}
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/* Notice branch-to-next; used to initialize RA with the PC. */
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if (disp == 0) {
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return 0;
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} else if (use_goto_tb(ctx, dest)) {
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tcg_gen_goto_tb(0);
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tcg_gen_movi_i64(cpu_pc, dest);
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tcg_gen_exit_tb(ctx->base.tb, 0);
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return DISAS_NORETURN;
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} else {
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tcg_gen_movi_i64(cpu_pc, dest);
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return DISAS_PC_UPDATED;
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return DISAS_NEXT;
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}
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gen_goto_tb(ctx, 0, disp);
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return DISAS_NORETURN;
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}
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static DisasJumpType gen_bcond_internal(DisasContext *ctx, TCGCond cond,
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TCGv cmp, uint64_t imm, int32_t disp)
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{
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uint64_t dest = ctx->base.pc_next + (disp << 2);
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TCGLabel *lab_true = gen_new_label();
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if (use_goto_tb(ctx, dest)) {
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tcg_gen_brcondi_i64(cond, cmp, imm, lab_true);
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tcg_gen_brcondi_i64(cond, cmp, imm, lab_true);
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gen_goto_tb(ctx, 0, 0);
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gen_set_label(lab_true);
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gen_goto_tb(ctx, 1, disp);
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tcg_gen_goto_tb(0);
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tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
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tcg_gen_exit_tb(ctx->base.tb, 0);
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gen_set_label(lab_true);
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tcg_gen_goto_tb(1);
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tcg_gen_movi_i64(cpu_pc, dest);
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tcg_gen_exit_tb(ctx->base.tb, 1);
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return DISAS_NORETURN;
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} else {
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TCGv_i64 i = tcg_constant_i64(imm);
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TCGv_i64 d = tcg_constant_i64(dest);
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TCGv_i64 p = tcg_constant_i64(ctx->base.pc_next);
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tcg_gen_movcond_i64(cond, cpu_pc, cmp, i, d, p);
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return DISAS_PC_UPDATED;
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}
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return DISAS_NORETURN;
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}
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static DisasJumpType gen_bcond(DisasContext *ctx, TCGCond cond, int ra,
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@ -1106,7 +1108,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
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}
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/* Allow interrupts to be recognized right away. */
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tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
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gen_pc_disp(ctx, cpu_pc, 0);
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return DISAS_PC_UPDATED_NOCHAIN;
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case 0x36:
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@ -1153,19 +1155,17 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
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#else
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{
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TCGv tmp = tcg_temp_new();
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uint64_t exc_addr = ctx->base.pc_next;
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uint64_t entry = ctx->palbr;
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uint64_t entry;
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gen_pc_disp(ctx, tmp, 0);
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if (ctx->tbflags & ENV_FLAG_PAL_MODE) {
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exc_addr |= 1;
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tcg_gen_ori_i64(tmp, tmp, 1);
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} else {
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tcg_gen_movi_i64(tmp, 1);
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st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT);
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st_flag_byte(tcg_constant_i64(1), ENV_FLAG_PAL_SHIFT);
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}
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tcg_gen_movi_i64(tmp, exc_addr);
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tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUAlphaState, exc_addr));
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entry = ctx->palbr;
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entry += (palcode & 0x80
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? 0x2000 + (palcode - 0x80) * 64
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: 0x1000 + palcode * 64);
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@ -1382,7 +1382,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
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real_islit = islit = extract32(insn, 12, 1);
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lit = extract32(insn, 13, 8);
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disp21 = sextract32(insn, 0, 21);
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disp21 = sextract32(insn, 0, 21) * 4;
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disp16 = sextract32(insn, 0, 16);
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disp12 = sextract32(insn, 0, 12);
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@ -2359,9 +2359,13 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
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/* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch
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prediction stack action, which of course we don't implement. */
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vb = load_gpr(ctx, rb);
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tcg_gen_andi_i64(cpu_pc, vb, ~3);
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if (ra != 31) {
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tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next);
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tmp = tcg_temp_new();
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tcg_gen_andi_i64(tmp, vb, ~3);
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gen_pc_disp(ctx, ctx->ir[ra], 0);
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tcg_gen_mov_i64(cpu_pc, tmp);
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} else {
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tcg_gen_andi_i64(cpu_pc, vb, ~3);
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}
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ret = DISAS_PC_UPDATED;
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break;
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@ -2862,6 +2866,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
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ctx->tbflags = ctx->base.tb->flags;
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ctx->mem_idx = alpha_env_mmu_index(env);
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ctx->pcrel = ctx->base.tb->cflags & CF_PCREL;
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ctx->implver = env->implver;
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ctx->amask = env->amask;
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@ -2897,7 +2902,13 @@ static void alpha_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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static void alpha_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
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{
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tcg_gen_insn_start(dcbase->pc_next);
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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if (ctx->pcrel) {
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tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK);
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} else {
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tcg_gen_insn_start(dcbase->pc_next);
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}
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}
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static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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@ -2920,14 +2931,10 @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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case DISAS_NORETURN:
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break;
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case DISAS_TOO_MANY:
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if (use_goto_tb(ctx, ctx->base.pc_next)) {
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tcg_gen_goto_tb(0);
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tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
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tcg_gen_exit_tb(ctx->base.tb, 0);
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}
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/* FALLTHRU */
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gen_goto_tb(ctx, 0, 0);
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break;
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case DISAS_PC_STALE:
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tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
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gen_pc_disp(ctx, cpu_pc, 0);
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/* FALLTHRU */
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case DISAS_PC_UPDATED:
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tcg_gen_lookup_and_goto_ptr();
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