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target-arm queue:

Browse Source 
* target/arm: Add missing break statement for Hypervisor Trap Exception
    (fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC)
  * hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
  * target/arm: Limit ID register assertions to TCG
  * configure: Clarify URL to source downloads
  * contrib/elf2dmp: Build download.o with CURL_CFLAGS
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190722' into staging

target-arm queue:
 * target/arm: Add missing break statement for Hypervisor Trap Exception
   (fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC)
 * hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
 * target/arm: Limit ID register assertions to TCG
 * configure: Clarify URL to source downloads
 * contrib/elf2dmp: Build download.o with CURL_CFLAGS

# gpg: Signature made Mon 22 Jul 2019 14:13:31 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190722:
  contrib/elf2dmp: Build download.o with CURL_CFLAGS
  configure: Clarify URL to source downloads
  target/arm: Limit ID register assertions to TCG
  hw/arm/fsl-imx6ul.c: Remove dead SMP-related code
  target/arm: Add missing break statement for Hypervisor Trap Exception

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-07-22 15:16:48 +01:00
commit 23da9e297b
8 changed files with 30 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Makefile
View File

@ -626,7 +626,6 @@ ifneq ($(EXESUF),)
qemu-ga: qemu-ga$(EXESUF) $(QGA_VSS_PROVIDER) $(QEMU_GA_MSI)
endif
elf2dmp$(EXESUF): LIBS += $(CURL_LIBS)
elf2dmp$(EXESUF): $(elf2dmp-obj-y)
$(call LINK, $^)

2
configure vendored
View File

@ -323,7 +323,7 @@ else
echo "to acquire QEMU source archives. Non-GIT builds are only"
echo "supported with source archives linked from:"
echo
echo " https://www.qemu.org/download/"
echo " https://www.qemu.org/download/#source"
echo
echo "Developers working with GIT can use scripts/archive-source.sh"
echo "if they need to create valid source archives."

3
contrib/elf2dmp/Makefile.objs
View File

@ -1 +1,4 @@
elf2dmp-obj-y = main.o addrspace.o download.o pdb.o qemu_elf.o
download.o-cflags := $(CURL_CFLAGS)
download.o-libs := $(CURL_LIBS)

62
hw/arm/fsl-imx6ul.c
View File

@ -29,16 +29,12 @@
static void fsl_imx6ul_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6ULState *s = FSL_IMX6UL(obj);
char name[NAME_SIZE];
int i;
for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6UL_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
"cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
}
object_initialize_child(obj, "cpu0", &s->cpu, sizeof(s->cpu),
"cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
/*
* A7MPCORE
@ -161,42 +157,25 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6ULState *s = FSL_IMX6UL(dev);
int i;
qemu_irq irq;
char name[NAME_SIZE];
unsigned int smp_cpus = ms->smp.cpus;
SysBusDevice *sbd;
DeviceState *d;
if (smp_cpus > FSL_IMX6UL_NUM_CPUS) {
error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus);
if (ms->smp.cpus > 1) {
error_setg(errp, "%s: Only a single CPU is supported (%d requested)",
TYPE_FSL_IMX6UL, ms->smp.cpus);
return;
}
for (i = 0; i < smp_cpus; i++) {
Object *o = OBJECT(&s->cpu[i]);
object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
/* On uniprocessor, the CBAR is set to 0 */
if (smp_cpus > 1) {
object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR,
"reset-cbar", &error_abort);
}
if (i) {
/* Secondary CPUs start in PSCI powered-down state */
object_property_set_bool(o, true,
"start-powered-off", &error_abort);
}
object_property_set_bool(o, true, "realized", &error_abort);
}
object_property_set_int(OBJECT(&s->cpu), QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
object_property_set_bool(OBJECT(&s->cpu), true,
"realized", &error_abort);
/*
* A7MPCORE
*/
object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
&error_abort);
object_property_set_int(OBJECT(&s->a7mpcore), 1, "num-cpu", &error_abort);
object_property_set_int(OBJECT(&s->a7mpcore),
FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
"num-irq", &error_abort);
@ -204,18 +183,13 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
for (i = 0; i < smp_cpus; i++) {
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
DeviceState *d = DEVICE(qemu_get_cpu(i));
sbd = SYS_BUS_DEVICE(&s->a7mpcore);
d = DEVICE(&s->cpu);
irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
sysbus_connect_irq(sbd, i, irq);
sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ));
sysbus_connect_irq(sbd, i + 2 * smp_cpus,
qdev_get_gpio_in(d, ARM_CPU_VIRQ));
sysbus_connect_irq(sbd, i + 3 * smp_cpus,
qdev_get_gpio_in(d, ARM_CPU_VFIQ));
}
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ));
sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ));
sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ));
sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ));
/*
* A7MPCORE DAP

2
hw/arm/mcimx6ul-evk.c
View File

@ -71,7 +71,7 @@ static void mcimx6ul_evk_init(MachineState *machine)
}
if (!qtest_enabled()) {
arm_load_kernel(&s->soc.cpu[0], &boot_info);
arm_load_kernel(&s->soc.cpu, &boot_info);
}
}

2
include/hw/arm/fsl-imx6ul.h
View File

@ -61,7 +61,7 @@ typedef struct FslIMX6ULState {
DeviceState parent_obj;
/*< public >*/
ARMCPU cpu[FSL_IMX6UL_NUM_CPUS];
ARMCPU cpu;
A15MPPrivState a7mpcore;
IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS];
IMXEPITState epit[FSL_IMX6UL_NUM_EPITS];

7
target/arm/cpu.c
View File

@ -1369,6 +1369,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* There exist AArch64 cpus without AArch32 support. When KVM
* queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
* Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
* As a general principle, we also do not make ID register
* consistency checks anywhere unless using TCG, because only
* for TCG would a consistency-check failure be a QEMU bug.
*/
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
@ -1383,7 +1386,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* Presence of EL2 itself is ARM_FEATURE_EL2, and of the
* Security Extensions is ARM_FEATURE_EL3.
*/
assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu));
set_feature(env, ARM_FEATURE_LPAE);
set_feature(env, ARM_FEATURE_V7);
}
@ -1409,7 +1412,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
if (arm_feature(env, ARM_FEATURE_V6)) {
set_feature(env, ARM_FEATURE_V5);
if (!arm_feature(env, ARM_FEATURE_M)) {
assert(no_aa32 || cpu_isar_feature(jazelle, cpu));
assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu));
set_feature(env, ARM_FEATURE_AUXCR);
}
}

1
target/arm/helper.c
View File

@ -7956,6 +7956,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
break;
case EXCP_HYP_TRAP:
addr = 0x14;
break;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
}