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First RISC-V PR for 6.0

Browse Source 
This PR:
  - Fixes some issues with the m25p80
  - Improves GDB support for RISC-V
  - Fixes some Linux boot issues, specifiaclly 32-bit boot failures
  - Enforces PMP exceptions correctly
  - Fixes some Coverity issues
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210117-3' into staging

First RISC-V PR for 6.0

This PR:
 - Fixes some issues with the m25p80
 - Improves GDB support for RISC-V
 - Fixes some Linux boot issues, specifiaclly 32-bit boot failures
 - Enforces PMP exceptions correctly
 - Fixes some Coverity issues

# gpg: Signature made Sun 17 Jan 2021 21:53:19 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210117-3:
  riscv: Pass RISCVHartArrayState by pointer
  target/riscv: Remove built-in GDB XML files for CSRs
  target/riscv: Generate the GDB XML file for CSR registers dynamically
  target/riscv: Add CSR name in the CSR function table
  target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
  hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
  hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
  target/riscv/pmp: Raise exception if no PMP entry is configured
  RISC-V: Place DTB at 3GB boundary instead of 4GB
  gdb: riscv: Add target description
  hw/block: m25p80: Implement AAI-WP command support for SST flashes
  hw/block: m25p80: Don't write to flash if write is disabled

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-01-18 10:28:26 +00:00
commit 20b8016ed8
20 changed files with 459 additions and 898 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
default-configs/targets/riscv32-linux-user.mak
View File

@ -1,4 +1,4 @@
TARGET_ARCH=riscv32
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml
TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml

2
default-configs/targets/riscv32-softmmu.mak
View File

@ -1,5 +1,5 @@
TARGET_ARCH=riscv32
TARGET_BASE_ARCH=riscv
TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml
TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml
TARGET_NEED_FDT=y

2
default-configs/targets/riscv64-linux-user.mak
View File

@ -1,4 +1,4 @@
TARGET_ARCH=riscv64
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml
TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml

2
default-configs/targets/riscv64-softmmu.mak
View File

@ -1,5 +1,5 @@
TARGET_ARCH=riscv64
TARGET_BASE_ARCH=riscv
TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml
TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
TARGET_NEED_FDT=y

250
gdb-xml/riscv-32bit-csr.xml
View File

@ -1,250 +0,0 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.csr">
<reg name="ustatus" bitsize="32"/>
<reg name="uie" bitsize="32"/>
<reg name="utvec" bitsize="32"/>
<reg name="uscratch" bitsize="32"/>
<reg name="uepc" bitsize="32"/>
<reg name="ucause" bitsize="32"/>
<reg name="utval" bitsize="32"/>
<reg name="uip" bitsize="32"/>
<reg name="fflags" bitsize="32"/>
<reg name="frm" bitsize="32"/>
<reg name="fcsr" bitsize="32"/>
<reg name="cycle" bitsize="32"/>
<reg name="time" bitsize="32"/>
<reg name="instret" bitsize="32"/>
<reg name="hpmcounter3" bitsize="32"/>
<reg name="hpmcounter4" bitsize="32"/>
<reg name="hpmcounter5" bitsize="32"/>
<reg name="hpmcounter6" bitsize="32"/>
<reg name="hpmcounter7" bitsize="32"/>
<reg name="hpmcounter8" bitsize="32"/>
<reg name="hpmcounter9" bitsize="32"/>
<reg name="hpmcounter10" bitsize="32"/>
<reg name="hpmcounter11" bitsize="32"/>
<reg name="hpmcounter12" bitsize="32"/>
<reg name="hpmcounter13" bitsize="32"/>
<reg name="hpmcounter14" bitsize="32"/>
<reg name="hpmcounter15" bitsize="32"/>
<reg name="hpmcounter16" bitsize="32"/>
<reg name="hpmcounter17" bitsize="32"/>
<reg name="hpmcounter18" bitsize="32"/>
<reg name="hpmcounter19" bitsize="32"/>
<reg name="hpmcounter20" bitsize="32"/>
<reg name="hpmcounter21" bitsize="32"/>
<reg name="hpmcounter22" bitsize="32"/>
<reg name="hpmcounter23" bitsize="32"/>
<reg name="hpmcounter24" bitsize="32"/>
<reg name="hpmcounter25" bitsize="32"/>
<reg name="hpmcounter26" bitsize="32"/>
<reg name="hpmcounter27" bitsize="32"/>
<reg name="hpmcounter28" bitsize="32"/>
<reg name="hpmcounter29" bitsize="32"/>
<reg name="hpmcounter30" bitsize="32"/>
<reg name="hpmcounter31" bitsize="32"/>
<reg name="cycleh" bitsize="32"/>
<reg name="timeh" bitsize="32"/>
<reg name="instreth" bitsize="32"/>
<reg name="hpmcounter3h" bitsize="32"/>
<reg name="hpmcounter4h" bitsize="32"/>
<reg name="hpmcounter5h" bitsize="32"/>
<reg name="hpmcounter6h" bitsize="32"/>
<reg name="hpmcounter7h" bitsize="32"/>
<reg name="hpmcounter8h" bitsize="32"/>
<reg name="hpmcounter9h" bitsize="32"/>
<reg name="hpmcounter10h" bitsize="32"/>
<reg name="hpmcounter11h" bitsize="32"/>
<reg name="hpmcounter12h" bitsize="32"/>
<reg name="hpmcounter13h" bitsize="32"/>
<reg name="hpmcounter14h" bitsize="32"/>
<reg name="hpmcounter15h" bitsize="32"/>
<reg name="hpmcounter16h" bitsize="32"/>
<reg name="hpmcounter17h" bitsize="32"/>
<reg name="hpmcounter18h" bitsize="32"/>
<reg name="hpmcounter19h" bitsize="32"/>
<reg name="hpmcounter20h" bitsize="32"/>
<reg name="hpmcounter21h" bitsize="32"/>
<reg name="hpmcounter22h" bitsize="32"/>
<reg name="hpmcounter23h" bitsize="32"/>
<reg name="hpmcounter24h" bitsize="32"/>
<reg name="hpmcounter25h" bitsize="32"/>
<reg name="hpmcounter26h" bitsize="32"/>
<reg name="hpmcounter27h" bitsize="32"/>
<reg name="hpmcounter28h" bitsize="32"/>
<reg name="hpmcounter29h" bitsize="32"/>
<reg name="hpmcounter30h" bitsize="32"/>
<reg name="hpmcounter31h" bitsize="32"/>
<reg name="sstatus" bitsize="32"/>
<reg name="sedeleg" bitsize="32"/>
<reg name="sideleg" bitsize="32"/>
<reg name="sie" bitsize="32"/>
<reg name="stvec" bitsize="32"/>
<reg name="scounteren" bitsize="32"/>
<reg name="sscratch" bitsize="32"/>
<reg name="sepc" bitsize="32"/>
<reg name="scause" bitsize="32"/>
<reg name="stval" bitsize="32"/>
<reg name="sip" bitsize="32"/>
<reg name="satp" bitsize="32"/>
<reg name="mvendorid" bitsize="32"/>
<reg name="marchid" bitsize="32"/>
<reg name="mimpid" bitsize="32"/>
<reg name="mhartid" bitsize="32"/>
<reg name="mstatus" bitsize="32"/>
<reg name="misa" bitsize="32"/>
<reg name="medeleg" bitsize="32"/>
<reg name="mideleg" bitsize="32"/>
<reg name="mie" bitsize="32"/>
<reg name="mtvec" bitsize="32"/>
<reg name="mcounteren" bitsize="32"/>
<reg name="mscratch" bitsize="32"/>
<reg name="mepc" bitsize="32"/>
<reg name="mcause" bitsize="32"/>
<reg name="mtval" bitsize="32"/>
<reg name="mip" bitsize="32"/>
<reg name="pmpcfg0" bitsize="32"/>
<reg name="pmpcfg1" bitsize="32"/>
<reg name="pmpcfg2" bitsize="32"/>
<reg name="pmpcfg3" bitsize="32"/>
<reg name="pmpaddr0" bitsize="32"/>
<reg name="pmpaddr1" bitsize="32"/>
<reg name="pmpaddr2" bitsize="32"/>
<reg name="pmpaddr3" bitsize="32"/>
<reg name="pmpaddr4" bitsize="32"/>
<reg name="pmpaddr5" bitsize="32"/>
<reg name="pmpaddr6" bitsize="32"/>
<reg name="pmpaddr7" bitsize="32"/>
<reg name="pmpaddr8" bitsize="32"/>
<reg name="pmpaddr9" bitsize="32"/>
<reg name="pmpaddr10" bitsize="32"/>
<reg name="pmpaddr11" bitsize="32"/>
<reg name="pmpaddr12" bitsize="32"/>
<reg name="pmpaddr13" bitsize="32"/>
<reg name="pmpaddr14" bitsize="32"/>
<reg name="pmpaddr15" bitsize="32"/>
<reg name="mcycle" bitsize="32"/>
<reg name="minstret" bitsize="32"/>
<reg name="mhpmcounter3" bitsize="32"/>
<reg name="mhpmcounter4" bitsize="32"/>
<reg name="mhpmcounter5" bitsize="32"/>
<reg name="mhpmcounter6" bitsize="32"/>
<reg name="mhpmcounter7" bitsize="32"/>
<reg name="mhpmcounter8" bitsize="32"/>
<reg name="mhpmcounter9" bitsize="32"/>
<reg name="mhpmcounter10" bitsize="32"/>
<reg name="mhpmcounter11" bitsize="32"/>
<reg name="mhpmcounter12" bitsize="32"/>
<reg name="mhpmcounter13" bitsize="32"/>
<reg name="mhpmcounter14" bitsize="32"/>
<reg name="mhpmcounter15" bitsize="32"/>
<reg name="mhpmcounter16" bitsize="32"/>
<reg name="mhpmcounter17" bitsize="32"/>
<reg name="mhpmcounter18" bitsize="32"/>
<reg name="mhpmcounter19" bitsize="32"/>
<reg name="mhpmcounter20" bitsize="32"/>
<reg name="mhpmcounter21" bitsize="32"/>
<reg name="mhpmcounter22" bitsize="32"/>
<reg name="mhpmcounter23" bitsize="32"/>
<reg name="mhpmcounter24" bitsize="32"/>
<reg name="mhpmcounter25" bitsize="32"/>
<reg name="mhpmcounter26" bitsize="32"/>
<reg name="mhpmcounter27" bitsize="32"/>
<reg name="mhpmcounter28" bitsize="32"/>
<reg name="mhpmcounter29" bitsize="32"/>
<reg name="mhpmcounter30" bitsize="32"/>
<reg name="mhpmcounter31" bitsize="32"/>
<reg name="mcycleh" bitsize="32"/>
<reg name="minstreth" bitsize="32"/>
<reg name="mhpmcounter3h" bitsize="32"/>
<reg name="mhpmcounter4h" bitsize="32"/>
<reg name="mhpmcounter5h" bitsize="32"/>
<reg name="mhpmcounter6h" bitsize="32"/>
<reg name="mhpmcounter7h" bitsize="32"/>
<reg name="mhpmcounter8h" bitsize="32"/>
<reg name="mhpmcounter9h" bitsize="32"/>
<reg name="mhpmcounter10h" bitsize="32"/>
<reg name="mhpmcounter11h" bitsize="32"/>
<reg name="mhpmcounter12h" bitsize="32"/>
<reg name="mhpmcounter13h" bitsize="32"/>
<reg name="mhpmcounter14h" bitsize="32"/>
<reg name="mhpmcounter15h" bitsize="32"/>
<reg name="mhpmcounter16h" bitsize="32"/>
<reg name="mhpmcounter17h" bitsize="32"/>
<reg name="mhpmcounter18h" bitsize="32"/>
<reg name="mhpmcounter19h" bitsize="32"/>
<reg name="mhpmcounter20h" bitsize="32"/>
<reg name="mhpmcounter21h" bitsize="32"/>
<reg name="mhpmcounter22h" bitsize="32"/>
<reg name="mhpmcounter23h" bitsize="32"/>
<reg name="mhpmcounter24h" bitsize="32"/>
<reg name="mhpmcounter25h" bitsize="32"/>
<reg name="mhpmcounter26h" bitsize="32"/>
<reg name="mhpmcounter27h" bitsize="32"/>
<reg name="mhpmcounter28h" bitsize="32"/>
<reg name="mhpmcounter29h" bitsize="32"/>
<reg name="mhpmcounter30h" bitsize="32"/>
<reg name="mhpmcounter31h" bitsize="32"/>
<reg name="mhpmevent3" bitsize="32"/>
<reg name="mhpmevent4" bitsize="32"/>
<reg name="mhpmevent5" bitsize="32"/>
<reg name="mhpmevent6" bitsize="32"/>
<reg name="mhpmevent7" bitsize="32"/>
<reg name="mhpmevent8" bitsize="32"/>
<reg name="mhpmevent9" bitsize="32"/>
<reg name="mhpmevent10" bitsize="32"/>
<reg name="mhpmevent11" bitsize="32"/>
<reg name="mhpmevent12" bitsize="32"/>
<reg name="mhpmevent13" bitsize="32"/>
<reg name="mhpmevent14" bitsize="32"/>
<reg name="mhpmevent15" bitsize="32"/>
<reg name="mhpmevent16" bitsize="32"/>
<reg name="mhpmevent17" bitsize="32"/>
<reg name="mhpmevent18" bitsize="32"/>
<reg name="mhpmevent19" bitsize="32"/>
<reg name="mhpmevent20" bitsize="32"/>
<reg name="mhpmevent21" bitsize="32"/>
<reg name="mhpmevent22" bitsize="32"/>
<reg name="mhpmevent23" bitsize="32"/>
<reg name="mhpmevent24" bitsize="32"/>
<reg name="mhpmevent25" bitsize="32"/>
<reg name="mhpmevent26" bitsize="32"/>
<reg name="mhpmevent27" bitsize="32"/>
<reg name="mhpmevent28" bitsize="32"/>
<reg name="mhpmevent29" bitsize="32"/>
<reg name="mhpmevent30" bitsize="32"/>
<reg name="mhpmevent31" bitsize="32"/>
<reg name="tselect" bitsize="32"/>
<reg name="tdata1" bitsize="32"/>
<reg name="tdata2" bitsize="32"/>
<reg name="tdata3" bitsize="32"/>
<reg name="dcsr" bitsize="32"/>
<reg name="dpc" bitsize="32"/>
<reg name="dscratch" bitsize="32"/>
<reg name="hstatus" bitsize="32"/>
<reg name="hedeleg" bitsize="32"/>
<reg name="hideleg" bitsize="32"/>
<reg name="hie" bitsize="32"/>
<reg name="htvec" bitsize="32"/>
<reg name="hscratch" bitsize="32"/>
<reg name="hepc" bitsize="32"/>
<reg name="hcause" bitsize="32"/>
<reg name="hbadaddr" bitsize="32"/>
<reg name="hip" bitsize="32"/>
<reg name="mbase" bitsize="32"/>
<reg name="mbound" bitsize="32"/>
<reg name="mibase" bitsize="32"/>
<reg name="mibound" bitsize="32"/>
<reg name="mdbase" bitsize="32"/>
<reg name="mdbound" bitsize="32"/>
<reg name="mucounteren" bitsize="32"/>
<reg name="mscounteren" bitsize="32"/>
<reg name="mhcounteren" bitsize="32"/>
</feature>

250
gdb-xml/riscv-64bit-csr.xml
View File

@ -1,250 +0,0 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.csr">
<reg name="ustatus" bitsize="64"/>
<reg name="uie" bitsize="64"/>
<reg name="utvec" bitsize="64"/>
<reg name="uscratch" bitsize="64"/>
<reg name="uepc" bitsize="64"/>
<reg name="ucause" bitsize="64"/>
<reg name="utval" bitsize="64"/>
<reg name="uip" bitsize="64"/>
<reg name="fflags" bitsize="64"/>
<reg name="frm" bitsize="64"/>
<reg name="fcsr" bitsize="64"/>
<reg name="cycle" bitsize="64"/>
<reg name="time" bitsize="64"/>
<reg name="instret" bitsize="64"/>
<reg name="hpmcounter3" bitsize="64"/>
<reg name="hpmcounter4" bitsize="64"/>
<reg name="hpmcounter5" bitsize="64"/>
<reg name="hpmcounter6" bitsize="64"/>
<reg name="hpmcounter7" bitsize="64"/>
<reg name="hpmcounter8" bitsize="64"/>
<reg name="hpmcounter9" bitsize="64"/>
<reg name="hpmcounter10" bitsize="64"/>
<reg name="hpmcounter11" bitsize="64"/>
<reg name="hpmcounter12" bitsize="64"/>
<reg name="hpmcounter13" bitsize="64"/>
<reg name="hpmcounter14" bitsize="64"/>
<reg name="hpmcounter15" bitsize="64"/>
<reg name="hpmcounter16" bitsize="64"/>
<reg name="hpmcounter17" bitsize="64"/>
<reg name="hpmcounter18" bitsize="64"/>
<reg name="hpmcounter19" bitsize="64"/>
<reg name="hpmcounter20" bitsize="64"/>
<reg name="hpmcounter21" bitsize="64"/>
<reg name="hpmcounter22" bitsize="64"/>
<reg name="hpmcounter23" bitsize="64"/>
<reg name="hpmcounter24" bitsize="64"/>
<reg name="hpmcounter25" bitsize="64"/>
<reg name="hpmcounter26" bitsize="64"/>
<reg name="hpmcounter27" bitsize="64"/>
<reg name="hpmcounter28" bitsize="64"/>
<reg name="hpmcounter29" bitsize="64"/>
<reg name="hpmcounter30" bitsize="64"/>
<reg name="hpmcounter31" bitsize="64"/>
<reg name="cycleh" bitsize="64"/>
<reg name="timeh" bitsize="64"/>
<reg name="instreth" bitsize="64"/>
<reg name="hpmcounter3h" bitsize="64"/>
<reg name="hpmcounter4h" bitsize="64"/>
<reg name="hpmcounter5h" bitsize="64"/>
<reg name="hpmcounter6h" bitsize="64"/>
<reg name="hpmcounter7h" bitsize="64"/>
<reg name="hpmcounter8h" bitsize="64"/>
<reg name="hpmcounter9h" bitsize="64"/>
<reg name="hpmcounter10h" bitsize="64"/>
<reg name="hpmcounter11h" bitsize="64"/>
<reg name="hpmcounter12h" bitsize="64"/>
<reg name="hpmcounter13h" bitsize="64"/>
<reg name="hpmcounter14h" bitsize="64"/>
<reg name="hpmcounter15h" bitsize="64"/>
<reg name="hpmcounter16h" bitsize="64"/>
<reg name="hpmcounter17h" bitsize="64"/>
<reg name="hpmcounter18h" bitsize="64"/>
<reg name="hpmcounter19h" bitsize="64"/>
<reg name="hpmcounter20h" bitsize="64"/>
<reg name="hpmcounter21h" bitsize="64"/>
<reg name="hpmcounter22h" bitsize="64"/>
<reg name="hpmcounter23h" bitsize="64"/>
<reg name="hpmcounter24h" bitsize="64"/>
<reg name="hpmcounter25h" bitsize="64"/>
<reg name="hpmcounter26h" bitsize="64"/>
<reg name="hpmcounter27h" bitsize="64"/>
<reg name="hpmcounter28h" bitsize="64"/>
<reg name="hpmcounter29h" bitsize="64"/>
<reg name="hpmcounter30h" bitsize="64"/>
<reg name="hpmcounter31h" bitsize="64"/>
<reg name="sstatus" bitsize="64"/>
<reg name="sedeleg" bitsize="64"/>
<reg name="sideleg" bitsize="64"/>
<reg name="sie" bitsize="64"/>
<reg name="stvec" bitsize="64"/>
<reg name="scounteren" bitsize="64"/>
<reg name="sscratch" bitsize="64"/>
<reg name="sepc" bitsize="64"/>
<reg name="scause" bitsize="64"/>
<reg name="stval" bitsize="64"/>
<reg name="sip" bitsize="64"/>
<reg name="satp" bitsize="64"/>
<reg name="mvendorid" bitsize="64"/>
<reg name="marchid" bitsize="64"/>
<reg name="mimpid" bitsize="64"/>
<reg name="mhartid" bitsize="64"/>
<reg name="mstatus" bitsize="64"/>
<reg name="misa" bitsize="64"/>
<reg name="medeleg" bitsize="64"/>
<reg name="mideleg" bitsize="64"/>
<reg name="mie" bitsize="64"/>
<reg name="mtvec" bitsize="64"/>
<reg name="mcounteren" bitsize="64"/>
<reg name="mscratch" bitsize="64"/>
<reg name="mepc" bitsize="64"/>
<reg name="mcause" bitsize="64"/>
<reg name="mtval" bitsize="64"/>
<reg name="mip" bitsize="64"/>
<reg name="pmpcfg0" bitsize="64"/>
<reg name="pmpcfg1" bitsize="64"/>
<reg name="pmpcfg2" bitsize="64"/>
<reg name="pmpcfg3" bitsize="64"/>
<reg name="pmpaddr0" bitsize="64"/>
<reg name="pmpaddr1" bitsize="64"/>
<reg name="pmpaddr2" bitsize="64"/>
<reg name="pmpaddr3" bitsize="64"/>
<reg name="pmpaddr4" bitsize="64"/>
<reg name="pmpaddr5" bitsize="64"/>
<reg name="pmpaddr6" bitsize="64"/>
<reg name="pmpaddr7" bitsize="64"/>
<reg name="pmpaddr8" bitsize="64"/>
<reg name="pmpaddr9" bitsize="64"/>
<reg name="pmpaddr10" bitsize="64"/>
<reg name="pmpaddr11" bitsize="64"/>
<reg name="pmpaddr12" bitsize="64"/>
<reg name="pmpaddr13" bitsize="64"/>
<reg name="pmpaddr14" bitsize="64"/>
<reg name="pmpaddr15" bitsize="64"/>
<reg name="mcycle" bitsize="64"/>
<reg name="minstret" bitsize="64"/>
<reg name="mhpmcounter3" bitsize="64"/>
<reg name="mhpmcounter4" bitsize="64"/>
<reg name="mhpmcounter5" bitsize="64"/>
<reg name="mhpmcounter6" bitsize="64"/>
<reg name="mhpmcounter7" bitsize="64"/>
<reg name="mhpmcounter8" bitsize="64"/>
<reg name="mhpmcounter9" bitsize="64"/>
<reg name="mhpmcounter10" bitsize="64"/>
<reg name="mhpmcounter11" bitsize="64"/>
<reg name="mhpmcounter12" bitsize="64"/>
<reg name="mhpmcounter13" bitsize="64"/>
<reg name="mhpmcounter14" bitsize="64"/>
<reg name="mhpmcounter15" bitsize="64"/>
<reg name="mhpmcounter16" bitsize="64"/>
<reg name="mhpmcounter17" bitsize="64"/>
<reg name="mhpmcounter18" bitsize="64"/>
<reg name="mhpmcounter19" bitsize="64"/>
<reg name="mhpmcounter20" bitsize="64"/>
<reg name="mhpmcounter21" bitsize="64"/>
<reg name="mhpmcounter22" bitsize="64"/>
<reg name="mhpmcounter23" bitsize="64"/>
<reg name="mhpmcounter24" bitsize="64"/>
<reg name="mhpmcounter25" bitsize="64"/>
<reg name="mhpmcounter26" bitsize="64"/>
<reg name="mhpmcounter27" bitsize="64"/>
<reg name="mhpmcounter28" bitsize="64"/>
<reg name="mhpmcounter29" bitsize="64"/>
<reg name="mhpmcounter30" bitsize="64"/>
<reg name="mhpmcounter31" bitsize="64"/>
<reg name="mcycleh" bitsize="64"/>
<reg name="minstreth" bitsize="64"/>
<reg name="mhpmcounter3h" bitsize="64"/>
<reg name="mhpmcounter4h" bitsize="64"/>
<reg name="mhpmcounter5h" bitsize="64"/>
<reg name="mhpmcounter6h" bitsize="64"/>
<reg name="mhpmcounter7h" bitsize="64"/>
<reg name="mhpmcounter8h" bitsize="64"/>
<reg name="mhpmcounter9h" bitsize="64"/>
<reg name="mhpmcounter10h" bitsize="64"/>
<reg name="mhpmcounter11h" bitsize="64"/>
<reg name="mhpmcounter12h" bitsize="64"/>
<reg name="mhpmcounter13h" bitsize="64"/>
<reg name="mhpmcounter14h" bitsize="64"/>
<reg name="mhpmcounter15h" bitsize="64"/>
<reg name="mhpmcounter16h" bitsize="64"/>
<reg name="mhpmcounter17h" bitsize="64"/>
<reg name="mhpmcounter18h" bitsize="64"/>
<reg name="mhpmcounter19h" bitsize="64"/>
<reg name="mhpmcounter20h" bitsize="64"/>
<reg name="mhpmcounter21h" bitsize="64"/>
<reg name="mhpmcounter22h" bitsize="64"/>
<reg name="mhpmcounter23h" bitsize="64"/>
<reg name="mhpmcounter24h" bitsize="64"/>
<reg name="mhpmcounter25h" bitsize="64"/>
<reg name="mhpmcounter26h" bitsize="64"/>
<reg name="mhpmcounter27h" bitsize="64"/>
<reg name="mhpmcounter28h" bitsize="64"/>
<reg name="mhpmcounter29h" bitsize="64"/>
<reg name="mhpmcounter30h" bitsize="64"/>
<reg name="mhpmcounter31h" bitsize="64"/>
<reg name="mhpmevent3" bitsize="64"/>
<reg name="mhpmevent4" bitsize="64"/>
<reg name="mhpmevent5" bitsize="64"/>
<reg name="mhpmevent6" bitsize="64"/>
<reg name="mhpmevent7" bitsize="64"/>
<reg name="mhpmevent8" bitsize="64"/>
<reg name="mhpmevent9" bitsize="64"/>
<reg name="mhpmevent10" bitsize="64"/>
<reg name="mhpmevent11" bitsize="64"/>
<reg name="mhpmevent12" bitsize="64"/>
<reg name="mhpmevent13" bitsize="64"/>
<reg name="mhpmevent14" bitsize="64"/>
<reg name="mhpmevent15" bitsize="64"/>
<reg name="mhpmevent16" bitsize="64"/>
<reg name="mhpmevent17" bitsize="64"/>
<reg name="mhpmevent18" bitsize="64"/>
<reg name="mhpmevent19" bitsize="64"/>
<reg name="mhpmevent20" bitsize="64"/>
<reg name="mhpmevent21" bitsize="64"/>
<reg name="mhpmevent22" bitsize="64"/>
<reg name="mhpmevent23" bitsize="64"/>
<reg name="mhpmevent24" bitsize="64"/>
<reg name="mhpmevent25" bitsize="64"/>
<reg name="mhpmevent26" bitsize="64"/>
<reg name="mhpmevent27" bitsize="64"/>
<reg name="mhpmevent28" bitsize="64"/>
<reg name="mhpmevent29" bitsize="64"/>
<reg name="mhpmevent30" bitsize="64"/>
<reg name="mhpmevent31" bitsize="64"/>
<reg name="tselect" bitsize="64"/>
<reg name="tdata1" bitsize="64"/>
<reg name="tdata2" bitsize="64"/>
<reg name="tdata3" bitsize="64"/>
<reg name="dcsr" bitsize="64"/>
<reg name="dpc" bitsize="64"/>
<reg name="dscratch" bitsize="64"/>
<reg name="hstatus" bitsize="64"/>
<reg name="hedeleg" bitsize="64"/>
<reg name="hideleg" bitsize="64"/>
<reg name="hie" bitsize="64"/>
<reg name="htvec" bitsize="64"/>
<reg name="hscratch" bitsize="64"/>
<reg name="hepc" bitsize="64"/>
<reg name="hcause" bitsize="64"/>
<reg name="hbadaddr" bitsize="64"/>
<reg name="hip" bitsize="64"/>
<reg name="mbase" bitsize="64"/>
<reg name="mbound" bitsize="64"/>
<reg name="mibase" bitsize="64"/>
<reg name="mibound" bitsize="64"/>
<reg name="mdbase" bitsize="64"/>
<reg name="mdbound" bitsize="64"/>
<reg name="mucounteren" bitsize="64"/>
<reg name="mscounteren" bitsize="64"/>
<reg name="mhcounteren" bitsize="64"/>
</feature>

74
hw/block/m25p80.c
View File

@ -360,6 +360,7 @@ typedef enum {
QPP_4 = 0x34,
RDID_90 = 0x90,
RDID_AB = 0xab,
AAI_WP = 0xad,
ERASE_4K = 0x20,
ERASE4_4K = 0x21,
@ -456,6 +457,7 @@ struct Flash {
bool four_bytes_address_mode;
bool reset_enable;
bool quad_enable;
bool aai_enable;
uint8_t ear;
int64_t dirty_page;
@ -601,6 +603,7 @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data)
if (!s->write_enable) {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
return;
}
if ((prev ^ data) & data) {
@ -670,6 +673,11 @@ static void complete_collecting_data(Flash *s)
case PP4_4:
s->state = STATE_PAGE_PROGRAM;
break;
case AAI_WP:
/* AAI programming starts from the even address */
s->cur_addr &= ~BIT(0);
s->state = STATE_PAGE_PROGRAM;
break;
case READ:
case READ4:
case FAST_READ:
@ -768,6 +776,7 @@ static void reset_memory(Flash *s)
s->write_enable = false;
s->reset_enable = false;
s->quad_enable = false;
s->aai_enable = false;
switch (get_man(s)) {
case MAN_NUMONYX:
@ -973,6 +982,11 @@ static void decode_qio_read_cmd(Flash *s)
s->state = STATE_COLLECTING_DATA;
}
static bool is_valid_aai_cmd(uint32_t cmd)
{
return cmd == AAI_WP || cmd == WRDI || cmd == RDSR;
}
static void decode_new_cmd(Flash *s, uint32_t value)
{
int i;
@ -984,6 +998,11 @@ static void decode_new_cmd(Flash *s, uint32_t value)
s->reset_enable = false;
}
if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
qemu_log_mask(LOG_GUEST_ERROR,
"M25P80: Invalid cmd within AAI programming sequence");
}
switch (value) {
case ERASE_4K:
@ -1103,6 +1122,9 @@ static void decode_new_cmd(Flash *s, uint32_t value)
case WRDI:
s->write_enable = false;
if (get_man(s) == MAN_SST) {
s->aai_enable = false;
}
break;
case WREN:
s->write_enable = true;
@ -1113,6 +1135,10 @@ static void decode_new_cmd(Flash *s, uint32_t value)
if (get_man(s) == MAN_MACRONIX) {
s->data[0] |= (!!s->quad_enable) << 6;
}
if (get_man(s) == MAN_SST) {
s->data[0] |= (!!s->aai_enable) << 6;
}
s->pos = 0;
s->len = 1;
s->data_read_loop = true;
@ -1260,6 +1286,24 @@ static void decode_new_cmd(Flash *s, uint32_t value)
case RSTQIO:
s->quad_enable = false;
break;
case AAI_WP:
if (get_man(s) == MAN_SST) {
if (s->write_enable) {
if (s->aai_enable) {
s->state = STATE_PAGE_PROGRAM;
} else {
s->aai_enable = true;
s->needed_bytes = get_addr_length(s);
s->state = STATE_COLLECTING_DATA;
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"M25P80: AAI_WP with write protect\n");
}
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
}
break;
default:
s->pos = 0;
s->len = 1;
@ -1305,6 +1349,17 @@ static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
flash_write8(s, s->cur_addr, (uint8_t)tx);
s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) {
/*
* There is no wrap mode during AAI programming once the highest
* unprotected memory address is reached. The Write-Enable-Latch
* bit is automatically reset, and AAI programming mode aborts.
*/
s->write_enable = false;
s->aai_enable = false;
}
break;
case STATE_READ:
@ -1450,6 +1505,24 @@ static const VMStateDescription vmstate_m25p80_data_read_loop = {
}
};
static bool m25p80_aai_enable_needed(void *opaque)
{
Flash *s = (Flash *)opaque;
return s->aai_enable;
}
static const VMStateDescription vmstate_m25p80_aai_enable = {
.name = "m25p80/aai_enable",
.version_id = 1,
.minimum_version_id = 1,
.needed = m25p80_aai_enable_needed,
.fields = (VMStateField[]) {
VMSTATE_BOOL(aai_enable, Flash),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_m25p80 = {
.name = "m25p80",
.version_id = 0,
@ -1480,6 +1553,7 @@ static const VMStateDescription vmstate_m25p80 = {
},
.subsections = (const VMStateDescription * []) {
&vmstate_m25p80_data_read_loop,
&vmstate_m25p80_aai_enable,
NULL
}
};

31
hw/misc/sifive_u_otp.c
View File

@ -63,8 +63,13 @@ static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
if (s->blk) {
int32_t buf;
blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
SIFIVE_U_OTP_FUSE_WORD);
if (blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
SIFIVE_U_OTP_FUSE_WORD) < 0) {
qemu_log_mask(LOG_GUEST_ERROR,
"read error index<%d>\n", s->pa);
return 0xff;
}
return buf;
}
@ -161,8 +166,12 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
/* write to backend */
if (s->blk) {
blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
&s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD, 0);
if (blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
&s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD,
0) < 0) {
qemu_log_mask(LOG_GUEST_ERROR,
"write error index<%d>\n", s->pa);
}
}
/* update written bit */
@ -249,12 +258,18 @@ static void sifive_u_otp_reset(DeviceState *dev)
int index = SIFIVE_U_OTP_SERIAL_ADDR;
serial_data = s->serial;
blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
qemu_log_mask(LOG_GUEST_ERROR,
"write error index<%d>\n", index);
}
serial_data = ~(s->serial);
blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
qemu_log_mask(LOG_GUEST_ERROR,
"write error index<%d>\n", index + 1);
}
}
/* Initialize write-once map */

18
hw/riscv/boot.c
View File

@ -33,14 +33,12 @@
#include <libfdt.h>
bool riscv_is_32bit(RISCVHartArrayState harts)
bool riscv_is_32bit(RISCVHartArrayState *harts)
{
RISCVCPU hart = harts.harts[0];
return riscv_cpu_is_32bit(&hart.env);
return riscv_cpu_is_32bit(&harts->harts[0].env);
}
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
target_ulong firmware_end_addr) {
if (riscv_is_32bit(harts)) {
return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
@ -194,11 +192,11 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
/*
* We should put fdt as far as possible to avoid kernel/initrd overwriting
* its content. But it should be addressable by 32 bit system as well.
* Thus, put it at an aligned address that less than fdt size from end of
* dram or 4GB whichever is lesser.
* Thus, put it at an 16MB aligned address that less than fdt size from the
* end of dram or 3GB whichever is lesser.
*/
temp = MIN(dram_end, 4096 * MiB);
fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
temp = MIN(dram_end, 3072 * MiB);
fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
fdt_pack(fdt);
/* copy in the device tree */
@ -247,7 +245,7 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
&address_space_memory);
}
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
hwaddr start_addr,
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,

16
hw/riscv/sifive_u.c
View File

@ -466,7 +466,7 @@ static void sifive_u_machine_init(MachineState *machine)
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
riscv_is_32bit(s->soc.u_cpus));
riscv_is_32bit(&s->soc.u_cpus));
if (s->start_in_flash) {
/*
@ -495,7 +495,7 @@ static void sifive_u_machine_init(MachineState *machine)
break;
}
if (riscv_is_32bit(s->soc.u_cpus)) {
if (riscv_is_32bit(&s->soc.u_cpus)) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
"opensbi-riscv32-generic-fw_dynamic.bin",
start_addr, NULL);
@ -506,7 +506,7 @@ static void sifive_u_machine_init(MachineState *machine)
}
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(s->soc.u_cpus,
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine->kernel_filename,
@ -533,7 +533,7 @@ static void sifive_u_machine_init(MachineState *machine)
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
machine->ram_size, s->fdt);
if (!riscv_is_32bit(s->soc.u_cpus)) {
if (!riscv_is_32bit(&s->soc.u_cpus)) {
start_addr_hi32 = (uint64_t)start_addr >> 32;
}
@ -552,7 +552,7 @@ static void sifive_u_machine_init(MachineState *machine)
0x00000000,
/* fw_dyn: */
};
if (riscv_is_32bit(s->soc.u_cpus)) {
if (riscv_is_32bit(&s->soc.u_cpus)) {
reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
} else {
@ -628,11 +628,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
mc->init = sifive_u_machine_init;
mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
#if defined(TARGET_RISCV32)
mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34;
#elif defined(TARGET_RISCV64)
mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54;
#endif
mc->default_cpu_type = SIFIVE_U_CPU;
mc->default_cpus = mc->min_cpus;
object_class_property_add_bool(oc, "start-in-flash",

8
hw/riscv/spike.c
View File

@ -244,7 +244,7 @@ static void spike_board_init(MachineState *machine)
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
riscv_is_32bit(s->soc[0]));
riscv_is_32bit(&s->soc[0]));
/* boot rom */
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
@ -257,7 +257,7 @@ static void spike_board_init(MachineState *machine)
* keeping ELF files here was intentional because BIN files don't work
* for the Spike machine as HTIF emulation depends on ELF parsing.
*/
if (riscv_is_32bit(s->soc[0])) {
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
"opensbi-riscv32-generic-fw_dynamic.elf",
memmap[SPIKE_DRAM].base,
@ -270,7 +270,7 @@ static void spike_board_init(MachineState *machine)
}
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine->kernel_filename,
@ -299,7 +299,7 @@ static void spike_board_init(MachineState *machine)
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
machine->ram_size, s->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(machine, s->soc[0], memmap[SPIKE_DRAM].base,
riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
memmap[SPIKE_MROM].base,
memmap[SPIKE_MROM].size, kernel_entry,
fdt_load_addr, s->fdt);

8
hw/riscv/virt.c
View File

@ -601,7 +601,7 @@ static void virt_machine_init(MachineState *machine)
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
riscv_is_32bit(s->soc[0]));
riscv_is_32bit(&s->soc[0]));
/* boot rom */
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
@ -609,7 +609,7 @@ static void virt_machine_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
mask_rom);
if (riscv_is_32bit(s->soc[0])) {
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
"opensbi-riscv32-generic-fw_dynamic.bin",
start_addr, NULL);
@ -620,7 +620,7 @@ static void virt_machine_init(MachineState *machine)
}
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0],
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine->kernel_filename,
@ -656,7 +656,7 @@ static void virt_machine_init(MachineState *machine)
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
machine->ram_size, s->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(machine, s->soc[0], start_addr,
riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
virt_memmap[VIRT_MROM].base,
virt_memmap[VIRT_MROM].size, kernel_entry,
fdt_load_addr, s->fdt);

6
include/hw/riscv/boot.h
View File

@ -24,9 +24,9 @@
#include "hw/loader.h"
#include "hw/riscv/riscv_hart.h"
bool riscv_is_32bit(RISCVHartArrayState harts);
bool riscv_is_32bit(RISCVHartArrayState *harts);
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
target_ulong firmware_end_addr);
target_ulong riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
@ -42,7 +42,7 @@ target_ulong riscv_load_kernel(const char *kernel_filename,
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);
uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
hwaddr saddr,
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,

25
target/riscv/cpu.c
View File

@ -557,6 +557,29 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
static gchar *riscv_gdb_arch_name(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
if (riscv_cpu_is_32bit(env)) {
return g_strdup("riscv:rv32");
} else {
return g_strdup("riscv:rv64");
}
}
static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
{
RISCVCPU *cpu = RISCV_CPU(cs);
if (strcmp(xmlname, "riscv-csr.xml") == 0) {
return cpu->dyn_csr_xml;
}
return NULL;
}
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@ -592,6 +615,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
#ifdef CONFIG_TCG
cc->tcg_initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;

11
target/riscv/cpu.h
View File

@ -272,6 +272,8 @@ struct RISCVCPU {
CPUNegativeOffsetState neg;
CPURISCVState env;
char *dyn_csr_xml;
/* Configuration Settings */
struct {
bool ext_i;
@ -472,12 +474,21 @@ typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
typedef struct {
const char *name;
riscv_csr_predicate_fn predicate;
riscv_csr_read_fn read;
riscv_csr_write_fn write;
riscv_csr_op_fn op;
} riscv_csr_operations;
/* CSR function table constants */
enum {
CSR_TABLE_SIZE = 0x1000
};
/* CSR function table */
extern riscv_csr_operations csr_ops[];
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);

334
target/riscv/csr.c
View File

@ -23,14 +23,6 @@
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
/* CSR function table */
static riscv_csr_operations csr_ops[];
/* CSR function table constants */
enum {
CSR_TABLE_SIZE = 0x1000
};
/* CSR function table public API */
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
{
@ -1378,114 +1370,278 @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
}
/* Control and Status Register function table */
static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Floating-Point CSRs */
[CSR_FFLAGS] = { fs, read_fflags, write_fflags },
[CSR_FRM] = { fs, read_frm, write_frm },
[CSR_FCSR] = { fs, read_fcsr, write_fcsr },
[CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
[CSR_FRM] = { "frm", fs, read_frm, write_frm },
[CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
/* Vector CSRs */
[CSR_VSTART] = { vs, read_vstart, write_vstart },
[CSR_VXSAT] = { vs, read_vxsat, write_vxsat },
[CSR_VXRM] = { vs, read_vxrm, write_vxrm },
[CSR_VL] = { vs, read_vl },
[CSR_VTYPE] = { vs, read_vtype },
[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
[CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
[CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
[CSR_VL] = { "vl", vs, read_vl },
[CSR_VTYPE] = { "vtype", vs, read_vtype },
/* User Timers and Counters */
[CSR_CYCLE] = { ctr, read_instret },
[CSR_INSTRET] = { ctr, read_instret },
[CSR_CYCLEH] = { ctr32, read_instreth },
[CSR_INSTRETH] = { ctr32, read_instreth },
[CSR_CYCLE] = { "cycle", ctr, read_instret },
[CSR_INSTRET] = { "instret", ctr, read_instret },
[CSR_CYCLEH] = { "cycleh", ctr32, read_instreth },
[CSR_INSTRETH] = { "instreth", ctr32, read_instreth },
/* In privileged mode, the monitor will have to emulate TIME CSRs only if
* rdtime callback is not provided by machine/platform emulation */
[CSR_TIME] = { ctr, read_time },
[CSR_TIMEH] = { ctr32, read_timeh },
/*
* In privileged mode, the monitor will have to emulate TIME CSRs only if
* rdtime callback is not provided by machine/platform emulation.
*/
[CSR_TIME] = { "time", ctr, read_time },
[CSR_TIMEH] = { "timeh", ctr32, read_timeh },
#if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */
[CSR_MCYCLE] = { any, read_instret },
[CSR_MINSTRET] = { any, read_instret },
[CSR_MCYCLEH] = { any32, read_instreth },
[CSR_MINSTRETH] = { any32, read_instreth },
[CSR_MCYCLE] = { "mcycle", any, read_instret },
[CSR_MINSTRET] = { "minstret", any, read_instret },
[CSR_MCYCLEH] = { "mcycleh", any32, read_instreth },
[CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
/* Machine Information Registers */
[CSR_MVENDORID] = { any, read_zero },
[CSR_MARCHID] = { any, read_zero },
[CSR_MIMPID] = { any, read_zero },
[CSR_MHARTID] = { any, read_mhartid },
[CSR_MVENDORID] = { "mvendorid", any, read_zero },
[CSR_MARCHID] = { "marchid", any, read_zero },
[CSR_MIMPID] = { "mimpid", any, read_zero },
[CSR_MHARTID] = { "mhartid", any, read_mhartid },
/* Machine Trap Setup */
[CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
[CSR_MISA] = { any, read_misa, write_misa },
[CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
[CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
[CSR_MIE] = { any, read_mie, write_mie },
[CSR_MTVEC] = { any, read_mtvec, write_mtvec },
[CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
[CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus },
[CSR_MISA] = { "misa", any, read_misa, write_misa },
[CSR_MIDELEG] = { "mideleg", any, read_mideleg, write_mideleg },
[CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
[CSR_MIE] = { "mie", any, read_mie, write_mie },
[CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
[CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren },
[CSR_MSTATUSH] = { any32, read_mstatush, write_mstatush },
[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush },
[CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
[CSR_MSCOUNTEREN] = { "msounteren", any, read_mscounteren, write_mscounteren },
/* Machine Trap Handling */
[CSR_MSCRATCH] = { any, read_mscratch, write_mscratch },
[CSR_MEPC] = { any, read_mepc, write_mepc },
[CSR_MCAUSE] = { any, read_mcause, write_mcause },
[CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr },
[CSR_MIP] = { any, NULL, NULL, rmw_mip },
[CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch },
[CSR_MEPC] = { "mepc", any, read_mepc, write_mepc },
[CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause },
[CSR_MBADADDR] = { "mbadaddr", any, read_mbadaddr, write_mbadaddr },
[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
/* Supervisor Trap Setup */
[CSR_SSTATUS] = { smode, read_sstatus, write_sstatus },
[CSR_SIE] = { smode, read_sie, write_sie },
[CSR_STVEC] = { smode, read_stvec, write_stvec },
[CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren },
[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus },
[CSR_SIE] = { "sie", smode, read_sie, write_sie },
[CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
[CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
/* Supervisor Trap Handling */
[CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch },
[CSR_SEPC] = { smode, read_sepc, write_sepc },
[CSR_SCAUSE] = { smode, read_scause, write_scause },
[CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr },
[CSR_SIP] = { smode, NULL, NULL, rmw_sip },
[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
[CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc },
[CSR_SCAUSE] = { "scause", smode, read_scause, write_scause },
[CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
[CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip },
/* Supervisor Protection and Translation */
[CSR_SATP] = { smode, read_satp, write_satp },
[CSR_SATP] = { "satp", smode, read_satp, write_satp },
[CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus },
[CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg },
[CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg },
[CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip },
[CSR_HIP] = { hmode, NULL, NULL, rmw_hip },
[CSR_HIE] = { hmode, read_hie, write_hie },
[CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren },
[CSR_HGEIE] = { hmode, read_hgeie, write_hgeie },
[CSR_HTVAL] = { hmode, read_htval, write_htval },
[CSR_HTINST] = { hmode, read_htinst, write_htinst },
[CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
[CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
[CSR_HTIMEDELTAH] = { hmode32, read_htimedeltah, write_htimedeltah},
[CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus },
[CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg },
[CSR_HIDELEG] = { "hideleg", hmode, read_hideleg, write_hideleg },
[CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip },
[CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
[CSR_HIE] = { "hie", hmode, read_hie, write_hie },
[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
[CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie },
[CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
[CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst },
[CSR_HGEIP] = { "hgeip", hmode, read_hgeip, write_hgeip },
[CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp },
[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta },
[CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
[CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus },
[CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip },
[CSR_VSIE] = { hmode, read_vsie, write_vsie },
[CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec },
[CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch },
[CSR_VSEPC] = { hmode, read_vsepc, write_vsepc },
[CSR_VSCAUSE] = { hmode, read_vscause, write_vscause },
[CSR_VSTVAL] = { hmode, read_vstval, write_vstval },
[CSR_VSATP] = { hmode, read_vsatp, write_vsatp },
[CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus },
[CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip },
[CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie },
[CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec },
[CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch },
[CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc },
[CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause },
[CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval },
[CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp },
[CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 },
[CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
[CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
[CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
/* Performance Counters */
[CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
[CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
[CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero },
[CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr32, read_zero },
[CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any32, read_zero },
[CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
[CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
[CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero },
[CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero },
[CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero },
[CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero },
[CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero },
[CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero },
[CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero },
[CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero },
[CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero },
[CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero },
[CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero },
[CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero },
[CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero },
[CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero },
[CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero },
[CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero },
[CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero },
[CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero },
[CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero },
[CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero },
[CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero },
[CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero },
[CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero },
[CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero },
[CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero },
[CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
[CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
[CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero },
[CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero },
[CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero },
[CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero },
[CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero },
[CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero },
[CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero },
[CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero },
[CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero },
[CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero },
[CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero },
[CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero },
[CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero },
[CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero },
[CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero },
[CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero },
[CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero },
[CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero },
[CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero },
[CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero },
[CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero },
[CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero },
[CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero },
[CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero },
[CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero },
[CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero },
[CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero },
[CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero },
[CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero },
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
[CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
[CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
[CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero },
[CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero },
[CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero },
[CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero },
[CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero },
[CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero },
[CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero },
[CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero },
[CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero },
[CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero },
[CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero },
[CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero },
[CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero },
[CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero },
[CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero },
[CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero },
[CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero },
[CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero },
[CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero },
[CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero },
[CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero },
[CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero },
[CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero },
[CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero },
[CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero },
[CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero },
[CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero },
[CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero },
[CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero },
[CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero },
[CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero },
[CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero },
[CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero },
[CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero },
[CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero },
[CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero },
[CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero },
[CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero },
[CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero },
[CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero },
[CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero },
[CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero },
[CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero },
[CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero },
[CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero },
[CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero },
[CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero },
[CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero },
[CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero },
[CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero },
[CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero },
[CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero },
[CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero },
[CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero },
[CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero },
[CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero },
[CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero },
[CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero },
[CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero },
[CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero },
[CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero },
[CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero },
[CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero },
[CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero },
[CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero },
[CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero },
[CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero },
[CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero },
[CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero },
[CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero },
[CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero },
[CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero },
[CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero },
[CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero },
[CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero },
[CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero },
[CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero },
[CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero },
[CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero },
[CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero },
[CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero },
[CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero },
[CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero },
[CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero },
#endif /* !CONFIG_USER_ONLY */
};

308
target/riscv/gdbstub.c
View File

@ -20,256 +20,6 @@
#include "exec/gdbstub.h"
#include "cpu.h"
/*
* The GDB CSR xml files list them in documentation order, not numerical order,
* and are missing entries for unnamed CSRs. So we need to map the gdb numbers
* to the hardware numbers.
*/
static int csr_register_map[] = {
CSR_USTATUS,
CSR_UIE,
CSR_UTVEC,
CSR_USCRATCH,
CSR_UEPC,
CSR_UCAUSE,
CSR_UTVAL,
CSR_UIP,
CSR_FFLAGS,
CSR_FRM,
CSR_FCSR,
CSR_CYCLE,
CSR_TIME,
CSR_INSTRET,
CSR_HPMCOUNTER3,
CSR_HPMCOUNTER4,
CSR_HPMCOUNTER5,
CSR_HPMCOUNTER6,
CSR_HPMCOUNTER7,
CSR_HPMCOUNTER8,
CSR_HPMCOUNTER9,
CSR_HPMCOUNTER10,
CSR_HPMCOUNTER11,
CSR_HPMCOUNTER12,
CSR_HPMCOUNTER13,
CSR_HPMCOUNTER14,
CSR_HPMCOUNTER15,
CSR_HPMCOUNTER16,
CSR_HPMCOUNTER17,
CSR_HPMCOUNTER18,
CSR_HPMCOUNTER19,
CSR_HPMCOUNTER20,
CSR_HPMCOUNTER21,
CSR_HPMCOUNTER22,
CSR_HPMCOUNTER23,
CSR_HPMCOUNTER24,
CSR_HPMCOUNTER25,
CSR_HPMCOUNTER26,
CSR_HPMCOUNTER27,
CSR_HPMCOUNTER28,
CSR_HPMCOUNTER29,
CSR_HPMCOUNTER30,
CSR_HPMCOUNTER31,
CSR_CYCLEH,
CSR_TIMEH,
CSR_INSTRETH,
CSR_HPMCOUNTER3H,
CSR_HPMCOUNTER4H,
CSR_HPMCOUNTER5H,
CSR_HPMCOUNTER6H,
CSR_HPMCOUNTER7H,
CSR_HPMCOUNTER8H,
CSR_HPMCOUNTER9H,
CSR_HPMCOUNTER10H,
CSR_HPMCOUNTER11H,
CSR_HPMCOUNTER12H,
CSR_HPMCOUNTER13H,
CSR_HPMCOUNTER14H,
CSR_HPMCOUNTER15H,
CSR_HPMCOUNTER16H,
CSR_HPMCOUNTER17H,
CSR_HPMCOUNTER18H,
CSR_HPMCOUNTER19H,
CSR_HPMCOUNTER20H,
CSR_HPMCOUNTER21H,
CSR_HPMCOUNTER22H,
CSR_HPMCOUNTER23H,
CSR_HPMCOUNTER24H,
CSR_HPMCOUNTER25H,
CSR_HPMCOUNTER26H,
CSR_HPMCOUNTER27H,
CSR_HPMCOUNTER28H,
CSR_HPMCOUNTER29H,
CSR_HPMCOUNTER30H,
CSR_HPMCOUNTER31H,
CSR_SSTATUS,
CSR_SEDELEG,
CSR_SIDELEG,
CSR_SIE,
CSR_STVEC,
CSR_SCOUNTEREN,
CSR_SSCRATCH,
CSR_SEPC,
CSR_SCAUSE,
CSR_STVAL,
CSR_SIP,
CSR_SATP,
CSR_MVENDORID,
CSR_MARCHID,
CSR_MIMPID,
CSR_MHARTID,
CSR_MSTATUS,
CSR_MISA,
CSR_MEDELEG,
CSR_MIDELEG,
CSR_MIE,
CSR_MTVEC,
CSR_MCOUNTEREN,
CSR_MSCRATCH,
CSR_MEPC,
CSR_MCAUSE,
CSR_MTVAL,
CSR_MIP,
CSR_MTINST,
CSR_MTVAL2,
CSR_PMPCFG0,
CSR_PMPCFG1,
CSR_PMPCFG2,
CSR_PMPCFG3,
CSR_PMPADDR0,
CSR_PMPADDR1,
CSR_PMPADDR2,
CSR_PMPADDR3,
CSR_PMPADDR4,
CSR_PMPADDR5,
CSR_PMPADDR6,
CSR_PMPADDR7,
CSR_PMPADDR8,
CSR_PMPADDR9,
CSR_PMPADDR10,
CSR_PMPADDR11,
CSR_PMPADDR12,
CSR_PMPADDR13,
CSR_PMPADDR14,
CSR_PMPADDR15,
CSR_MCYCLE,
CSR_MINSTRET,
CSR_MHPMCOUNTER3,
CSR_MHPMCOUNTER4,
CSR_MHPMCOUNTER5,
CSR_MHPMCOUNTER6,
CSR_MHPMCOUNTER7,
CSR_MHPMCOUNTER8,
CSR_MHPMCOUNTER9,
CSR_MHPMCOUNTER10,
CSR_MHPMCOUNTER11,
CSR_MHPMCOUNTER12,
CSR_MHPMCOUNTER13,
CSR_MHPMCOUNTER14,
CSR_MHPMCOUNTER15,
CSR_MHPMCOUNTER16,
CSR_MHPMCOUNTER17,
CSR_MHPMCOUNTER18,
CSR_MHPMCOUNTER19,
CSR_MHPMCOUNTER20,
CSR_MHPMCOUNTER21,
CSR_MHPMCOUNTER22,
CSR_MHPMCOUNTER23,
CSR_MHPMCOUNTER24,
CSR_MHPMCOUNTER25,
CSR_MHPMCOUNTER26,
CSR_MHPMCOUNTER27,
CSR_MHPMCOUNTER28,
CSR_MHPMCOUNTER29,
CSR_MHPMCOUNTER30,
CSR_MHPMCOUNTER31,
CSR_MCYCLEH,
CSR_MINSTRETH,
CSR_MHPMCOUNTER3H,
CSR_MHPMCOUNTER4H,
CSR_MHPMCOUNTER5H,
CSR_MHPMCOUNTER6H,
CSR_MHPMCOUNTER7H,
CSR_MHPMCOUNTER8H,
CSR_MHPMCOUNTER9H,
CSR_MHPMCOUNTER10H,
CSR_MHPMCOUNTER11H,
CSR_MHPMCOUNTER12H,
CSR_MHPMCOUNTER13H,
CSR_MHPMCOUNTER14H,
CSR_MHPMCOUNTER15H,
CSR_MHPMCOUNTER16H,
CSR_MHPMCOUNTER17H,
CSR_MHPMCOUNTER18H,
CSR_MHPMCOUNTER19H,
CSR_MHPMCOUNTER20H,
CSR_MHPMCOUNTER21H,
CSR_MHPMCOUNTER22H,
CSR_MHPMCOUNTER23H,
CSR_MHPMCOUNTER24H,
CSR_MHPMCOUNTER25H,
CSR_MHPMCOUNTER26H,
CSR_MHPMCOUNTER27H,
CSR_MHPMCOUNTER28H,
CSR_MHPMCOUNTER29H,
CSR_MHPMCOUNTER30H,
CSR_MHPMCOUNTER31H,
CSR_MHPMEVENT3,
CSR_MHPMEVENT4,
CSR_MHPMEVENT5,
CSR_MHPMEVENT6,
CSR_MHPMEVENT7,
CSR_MHPMEVENT8,
CSR_MHPMEVENT9,
CSR_MHPMEVENT10,
CSR_MHPMEVENT11,
CSR_MHPMEVENT12,
CSR_MHPMEVENT13,
CSR_MHPMEVENT14,
CSR_MHPMEVENT15,
CSR_MHPMEVENT16,
CSR_MHPMEVENT17,
CSR_MHPMEVENT18,
CSR_MHPMEVENT19,
CSR_MHPMEVENT20,
CSR_MHPMEVENT21,
CSR_MHPMEVENT22,
CSR_MHPMEVENT23,
CSR_MHPMEVENT24,
CSR_MHPMEVENT25,
CSR_MHPMEVENT26,
CSR_MHPMEVENT27,
CSR_MHPMEVENT28,
CSR_MHPMEVENT29,
CSR_MHPMEVENT30,
CSR_MHPMEVENT31,
CSR_TSELECT,
CSR_TDATA1,
CSR_TDATA2,
CSR_TDATA3,
CSR_DCSR,
CSR_DPC,
CSR_DSCRATCH,
CSR_HSTATUS,
CSR_HEDELEG,
CSR_HIDELEG,
CSR_HIE,
CSR_HCOUNTEREN,
CSR_HTVAL,
CSR_HIP,
CSR_HTINST,
CSR_HGATP,
CSR_MBASE,
CSR_MBOUND,
CSR_MIBASE,
CSR_MIBOUND,
CSR_MDBASE,
CSR_MDBOUND,
CSR_MUCOUNTEREN,
CSR_MSCOUNTEREN,
CSR_MHCOUNTEREN,
};
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
@ -315,11 +65,11 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
target_ulong val = 0;
int result;
/*
* CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
* CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
* register 33, so we recalculate the map index.
* This also works for CSR_FRM and CSR_FCSR.
*/
result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
result = riscv_csrrw_debug(env, n - 32, &val,
0, 0);
if (result == 0) {
return gdb_get_regl(buf, val);
@ -338,11 +88,11 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
target_ulong val = ldtul_p(mem_buf);
int result;
/*
* CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
* CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
* register 33, so we recalculate the map index.
* This also works for CSR_FRM and CSR_FCSR.
*/
result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
result = riscv_csrrw_debug(env, n - 32, NULL,
val, -1);
if (result == 0) {
return sizeof(target_ulong);
@ -353,11 +103,11 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
{
if (n < ARRAY_SIZE(csr_register_map)) {
if (n < CSR_TABLE_SIZE) {
target_ulong val = 0;
int result;
result = riscv_csrrw_debug(env, csr_register_map[n], &val, 0, 0);
result = riscv_csrrw_debug(env, n, &val, 0, 0);
if (result == 0) {
return gdb_get_regl(buf, val);
}
@ -367,11 +117,11 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < ARRAY_SIZE(csr_register_map)) {
if (n < CSR_TABLE_SIZE) {
target_ulong val = ldtul_p(mem_buf);
int result;
result = riscv_csrrw_debug(env, csr_register_map[n], NULL, val, -1);
result = riscv_csrrw_debug(env, n, NULL, val, -1);
if (result == 0) {
return sizeof(target_ulong);
}
@ -405,6 +155,38 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
return 0;
}
static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
GString *s = g_string_new(NULL);
riscv_csr_predicate_fn predicate;
int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
int i;
g_string_printf(s, "<?xml version=\"1.0\"?>");
g_string_append_printf(s, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">");
g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">");
for (i = 0; i < CSR_TABLE_SIZE; i++) {
predicate = csr_ops[i].predicate;
if (predicate && !predicate(env, i)) {
if (csr_ops[i].name) {
g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
} else {
g_string_append_printf(s, "<reg name=\"csr%03x\"", i);
}
g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
g_string_append_printf(s, " regnum=\"%d\"/>", base_reg + i);
}
}
g_string_append_printf(s, "</feature>");
cpu->dyn_csr_xml = g_string_free(s, false);
return CSR_TABLE_SIZE;
}
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
@ -417,16 +199,14 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
36, "riscv-32bit-fpu.xml", 0);
}
#if defined(TARGET_RISCV32)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
240, "riscv-32bit-csr.xml", 0);
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-32bit-virtual.xml", 0);
#elif defined(TARGET_RISCV64)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
240, "riscv-64bit-csr.xml", 0);
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-64bit-virtual.xml", 0);
#endif
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
"riscv-csr.xml", 0);
}

5
target/riscv/op_helper.c
View File

@ -150,6 +150,11 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
uint64_t mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
mstatus = set_field(mstatus, MSTATUS_MIE,
get_field(mstatus, MSTATUS_MPIE));

4
target/riscv/pmp.c
View File

@ -74,7 +74,7 @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
/*
* Count the number of active rules.
*/
static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
uint32_t pmp_get_num_rules(CPURISCVState *env)
{
return env->pmp_state.num_rules;
}
@ -237,7 +237,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
return true;
return (env->priv == PRV_M) ? true : false;
}
if (size == 0) {

1
target/riscv/pmp.h
View File

@ -64,5 +64,6 @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
target_ulong *tlb_size);
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
void pmp_update_rule_nums(CPURISCVState *env);
uint32_t pmp_get_num_rules(CPURISCVState *env);
#endif