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tcg/ppc: Reorg goto_tb implementation
The old ppc64 implementation replaces 2 or 4 insns, which leaves a race condition in which a thread could be stopped at a PC in the middle of the sequence, and when restarted does not see the complete address computation and branches to nowhere. The new implemetation replaces only one insn, swapping between b <dest> and mtctr r31 falling through to a general-case indirect branch. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
d59d83a1c3
commit
20b6643324
@ -1854,104 +1854,6 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
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tcg_out32(s, insn);
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}
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static inline uint64_t make_pair(tcg_insn_unit i1, tcg_insn_unit i2)
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{
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if (HOST_BIG_ENDIAN) {
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return (uint64_t)i1 << 32 | i2;
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}
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return (uint64_t)i2 << 32 | i1;
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}
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static inline void ppc64_replace2(uintptr_t rx, uintptr_t rw,
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tcg_insn_unit i0, tcg_insn_unit i1)
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{
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#if TCG_TARGET_REG_BITS == 64
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qatomic_set((uint64_t *)rw, make_pair(i0, i1));
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flush_idcache_range(rx, rw, 8);
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#else
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qemu_build_not_reached();
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#endif
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}
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static inline void ppc64_replace4(uintptr_t rx, uintptr_t rw,
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tcg_insn_unit i0, tcg_insn_unit i1,
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tcg_insn_unit i2, tcg_insn_unit i3)
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{
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uint64_t p[2];
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p[!HOST_BIG_ENDIAN] = make_pair(i0, i1);
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p[HOST_BIG_ENDIAN] = make_pair(i2, i3);
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/*
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* There's no convenient way to get the compiler to allocate a pair
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* of registers at an even index, so copy into r6/r7 and clobber.
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*/
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asm("mr %%r6, %1\n\t"
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"mr %%r7, %2\n\t"
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"stq %%r6, %0"
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: "=Q"(*(__int128 *)rw) : "r"(p[0]), "r"(p[1]) : "r6", "r7");
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flush_idcache_range(rx, rw, 16);
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}
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void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
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uintptr_t jmp_rx, uintptr_t jmp_rw)
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{
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tcg_insn_unit i0, i1, i2, i3;
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uintptr_t addr = tb->jmp_target_addr[n];
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intptr_t tb_diff = addr - (uintptr_t)tb->tc.ptr;
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intptr_t br_diff = addr - (jmp_rx + 4);
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intptr_t lo, hi;
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if (TCG_TARGET_REG_BITS == 32) {
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intptr_t diff = addr - jmp_rx;
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tcg_debug_assert(in_range_b(diff));
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qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc));
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flush_idcache_range(jmp_rx, jmp_rw, 4);
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return;
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}
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/*
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* For 16-bit displacements, we can use a single add + branch.
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* This happens quite often.
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*/
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if (tb_diff == (int16_t)tb_diff) {
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i0 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
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i1 = B | (br_diff & 0x3fffffc);
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ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
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return;
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}
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lo = (int16_t)tb_diff;
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hi = (int32_t)(tb_diff - lo);
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assert(tb_diff == hi + lo);
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i0 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
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i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
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/*
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* Without stq from 2.07, we can only update two insns,
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* and those must be the ones that load the target address.
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*/
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if (!have_isa_2_07) {
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ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
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return;
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}
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/*
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* For 26-bit displacements, we can use a direct branch.
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* Otherwise we still need the indirect branch, which we
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* must restore after a potential direct branch write.
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*/
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br_diff -= 4;
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if (in_range_b(br_diff)) {
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i2 = B | (br_diff & 0x3fffffc);
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i3 = NOP;
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} else {
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i2 = MTSPR | RS(TCG_REG_TB) | CTR;
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i3 = BCCTR | BO_ALWAYS;
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}
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ppc64_replace4(jmp_rx, jmp_rw, i0, i1, i2, i3);
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}
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static void tcg_out_call_int(TCGContext *s, int lk,
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const tcg_insn_unit *target)
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{
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@ -2625,30 +2527,56 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg)
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static void tcg_out_goto_tb(TCGContext *s, int which)
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{
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/* Direct jump. */
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if (TCG_TARGET_REG_BITS == 64) {
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/* Ensure the next insns are 8 or 16-byte aligned. */
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while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) {
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tcg_out32(s, NOP);
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}
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uintptr_t ptr = get_jmp_target_addr(s, which);
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if (USE_REG_TB) {
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ptrdiff_t offset = tcg_tbrel_diff(s, (void *)ptr);
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tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset);
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/* Direct branch will be patched by tb_target_set_jmp_target. */
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set_jmp_insn_offset(s, which);
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tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
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tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
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tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
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/* When branch is out of range, fall through to indirect. */
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tcg_out32(s, BCCTR | BO_ALWAYS);
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/* For the unlinked case, need to reset TCG_REG_TB. */
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set_jmp_reset_offset(s, which);
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tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB,
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-tcg_current_code_size(s));
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} else {
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/* Direct branch will be patched by tb_target_set_jmp_target. */
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set_jmp_insn_offset(s, which);
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tcg_out32(s, NOP);
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/* When branch is out of range, fall through to indirect. */
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)ptr);
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tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR);
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tcg_out32(s, BCCTR | BO_ALWAYS);
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set_jmp_reset_offset(s, which);
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if (USE_REG_TB) {
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/* For the unlinked case, need to reset TCG_REG_TB. */
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tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB,
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-tcg_current_code_size(s));
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}
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} else {
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set_jmp_insn_offset(s, which);
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tcg_out32(s, B);
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set_jmp_reset_offset(s, which);
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}
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}
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void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
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uintptr_t jmp_rx, uintptr_t jmp_rw)
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{
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uintptr_t addr = tb->jmp_target_addr[n];
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intptr_t diff = addr - jmp_rx;
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tcg_insn_unit insn;
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if (in_range_b(diff)) {
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insn = B | (diff & 0x3fffffc);
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} else if (USE_REG_TB) {
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insn = MTSPR | RS(TCG_REG_TB) | CTR;
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} else {
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insn = NOP;
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}
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qatomic_set((uint32_t *)jmp_rw, insn);
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flush_idcache_range(jmp_rx, jmp_rw, 4);
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}
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static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS])
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@ -27,11 +27,10 @@
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#ifdef _ARCH_PPC64
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# define TCG_TARGET_REG_BITS 64
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# define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB)
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#else
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# define TCG_TARGET_REG_BITS 32
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# define MAX_CODE_GEN_BUFFER_SIZE (32 * MiB)
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#endif
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#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
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#define TCG_TARGET_NB_REGS 64
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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