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target/ppc: Implement the rest of gen_ld_atomic

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These cases were stubbed out.  For now, implement them only within
a serial context, forcing parallel execution to synchronize.  It
would be possible to implement these with cmpxchg loops, if we care.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson 2018-06-26 09:19:20 -07:00 committed by David Gibson
parent b8ce0f8678
commit 20923c1d02
1 changed files with 82 additions and 7 deletions
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89
target/ppc/translate.c
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@ -3078,16 +3078,45 @@ LARX(lbarx, DEF_MEMOP(MO_UB))
LARX(lharx, DEF_MEMOP(MO_UW))
LARX(lwarx, DEF_MEMOP(MO_UL))
static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,
TCGv EA, TCGCond cond, int addend)
{
TCGv t = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGv u = tcg_temp_new();
tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
tcg_gen_addi_tl(u, t, addend);
/* E.g. for fetch and increment bounded... */
/* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
tcg_gen_movcond_tl(cond, u, t, t2, u, t);
tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
/* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
tcg_temp_free(t);
tcg_temp_free(t2);
tcg_temp_free(u);
}
static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
{
uint32_t gpr_FC = FC(ctx->opcode);
TCGv EA = tcg_temp_new();
int rt = rD(ctx->opcode);
bool need_serial;
TCGv src, dst;
gen_addr_register(ctx, EA);
dst = cpu_gpr[rD(ctx->opcode)];
src = cpu_gpr[rD(ctx->opcode) + 1];
dst = cpu_gpr[rt];
src = cpu_gpr[(rt + 1) & 31];
need_serial = false;
memop |= MO_ALIGN;
switch (gpr_FC) {
case 0: /* Fetch and add */
@ -3117,17 +3146,63 @@ static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
case 8: /* Swap */
tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
break;
case 16: /* compare and swap not equal */
case 24: /* Fetch and increment bounded */
case 25: /* Fetch and increment equal */
case 28: /* Fetch and decrement bounded */
gen_invalid(ctx);
case 16: /* Compare and swap not equal */
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
need_serial = true;
} else {
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
tcg_gen_mov_tl(t1, src);
} else {
tcg_gen_ext32u_tl(t1, src);
}
tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
cpu_gpr[(rt + 2) & 31], t0);
tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
tcg_gen_mov_tl(dst, t0);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
break;
case 24: /* Fetch and increment bounded */
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
need_serial = true;
} else {
gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
}
break;
case 25: /* Fetch and increment equal */
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
need_serial = true;
} else {
gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
}
break;
case 28: /* Fetch and decrement bounded */
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
need_serial = true;
} else {
gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
}
break;
default:
/* invoke data storage error handler */
gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
}
tcg_temp_free(EA);
if (need_serial) {
/* Restart with exclusive lock. */
gen_helper_exit_atomic(cpu_env);
ctx->base.is_jmp = DISAS_NORETURN;
}
}
static void gen_lwat(DisasContext *ctx)