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RISC-V: Fix missing break statement in disassembler

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This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Michael Clark 2018-04-30 11:06:31 +12:00
parent 6296a799b1
commit 1dc34be1c9
No known key found for this signature in database
GPG Key ID: 6BF1D7B357EF3E4F
1 changed files with 2 additions and 1 deletions
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3
disas/riscv.c
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@ -1470,8 +1470,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
if (isa == rv128) {
op = rv_op_c_sqsp;
} else {
op = rv_op_c_fsdsp; break;
op = rv_op_c_fsdsp;
}
break;
case 6: op = rv_op_c_swsp; break;
case 7:
if (isa == rv32) {