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spapr: extend the sPAPR IRQ backend for XICS migration
Introduce a new sPAPR IRQ handler to handle resend after migration when the machine is using a KVM XICS interrupt controller model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1730,14 +1730,6 @@ static int spapr_post_load(void *opaque, int version_id)
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return err;
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}
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if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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icp_resend(ICP(cpu->intc));
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}
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}
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/* In earlier versions, there was no separate qdev for the PAPR
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* RTC, so the RTC offset was stored directly in sPAPREnvironment.
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* So when migrating from those versions, poke the incoming offset
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@ -1758,6 +1750,11 @@ static int spapr_post_load(void *opaque, int version_id)
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}
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}
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err = spapr_irq_post_load(spapr, version_id);
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if (err) {
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return err;
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}
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return err;
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}
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@ -197,6 +197,18 @@ static Object *spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
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return icp_create(cpu, spapr->icp_type, XICS_FABRIC(spapr), errp);
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}
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static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
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{
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if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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icp_resend(ICP(cpu->intc));
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}
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}
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return 0;
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}
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#define SPAPR_IRQ_XICS_NR_IRQS 0x1000
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#define SPAPR_IRQ_XICS_NR_MSIS \
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(XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
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@ -212,6 +224,7 @@ sPAPRIrq spapr_irq_xics = {
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.print_info = spapr_irq_print_info_xics,
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.dt_populate = spapr_dt_xics,
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.cpu_intc_create = spapr_irq_cpu_intc_create_xics,
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.post_load = spapr_irq_post_load_xics,
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};
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/*
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@ -295,6 +308,11 @@ static Object *spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
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return xive_tctx_create(cpu, XIVE_ROUTER(spapr->xive), errp);
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}
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static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
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{
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return 0;
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}
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/*
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* XIVE uses the full IRQ number space. Set it to 8K to be compatible
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* with XICS.
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@ -314,6 +332,7 @@ sPAPRIrq spapr_irq_xive = {
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.print_info = spapr_irq_print_info_xive,
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.dt_populate = spapr_dt_xive,
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.cpu_intc_create = spapr_irq_cpu_intc_create_xive,
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.post_load = spapr_irq_post_load_xive,
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};
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/*
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@ -352,6 +371,13 @@ qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
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return smc->irq->qirq(spapr, irq);
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}
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int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id)
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{
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sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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return smc->irq->post_load(spapr, version_id);
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}
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/*
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* XICS legacy routines - to deprecate one day
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*/
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@ -420,4 +446,5 @@ sPAPRIrq spapr_irq_xics_legacy = {
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.print_info = spapr_irq_print_info_xics,
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.dt_populate = spapr_dt_xics,
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.cpu_intc_create = spapr_irq_cpu_intc_create_xics,
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.post_load = spapr_irq_post_load_xics,
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};
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@ -43,6 +43,7 @@ typedef struct sPAPRIrq {
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void *fdt, uint32_t phandle);
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Object *(*cpu_intc_create)(sPAPRMachineState *spapr, Object *cpu,
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Error **errp);
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int (*post_load)(sPAPRMachineState *spapr, int version_id);
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} sPAPRIrq;
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extern sPAPRIrq spapr_irq_xics;
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@ -53,6 +54,7 @@ void spapr_irq_init(sPAPRMachineState *spapr, Error **errp);
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int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp);
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void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num);
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qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq);
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int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id);
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/*
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* XICS legacy routines
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