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hw/ide/ahci: PxCI should not get cleared when ERR_STAT is set

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For NCQ, PxCI is cleared on command queued successfully.
For non-NCQ, PxCI is cleared on command completed successfully.
Successfully means ERR_STAT, BUSY and DRQ are all cleared.

A command that has ERR_STAT set, does not get to clear PxCI.
See AHCI 1.3.1, section 5.3.8, states RegFIS:Entry and RegFIS:ClearCI,
and 5.3.16.5 ERR:FatalTaskfile.

In the case of non-NCQ commands, not clearing PxCI is needed in order
for host software to be able to see which command slot that failed.

Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Message-id: 20230609140844.202795-7-nks@flawful.org
Signed-off-by: John Snow <jsnow@redhat.com>
This commit is contained in:
Niklas Cassel 2023-06-09 16:08:42 +02:00 committed by John Snow
parent d73b84d0b6
commit 1a16ce64fd
3 changed files with 88 additions and 33 deletions
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7
hw/ide/ahci.c
View File

@ -1523,7 +1523,8 @@ static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot)
{
IDEState *ide_state = &ad->port.ifs[0];
if (!(ide_state->status & (BUSY_STAT | DRQ_STAT))) {
if (!(ide_state->status & ERR_STAT) &&
!(ide_state->status & (BUSY_STAT | DRQ_STAT))) {
ad->port_regs.cmd_issue &= ~(1 << slot);
}
}
@ -1532,6 +1533,7 @@ static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot)
static void ahci_cmd_done(const IDEDMA *dma)
{
AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
IDEState *ide_state = &ad->port.ifs[0];
trace_ahci_cmd_done(ad->hba, ad->port_no);
@ -1548,7 +1550,8 @@ static void ahci_cmd_done(const IDEDMA *dma)
*/
ahci_write_fis_d2h(ad, true);
if (ad->port_regs.cmd_issue && !ad->check_bh) {
if (!(ide_state->status & ERR_STAT) &&
ad->port_regs.cmd_issue && !ad->check_bh) {
ad->check_bh = qemu_bh_new_guarded(ahci_check_cmd_bh, ad,
&ad->mem_reentrancy_guard);
qemu_bh_schedule(ad->check_bh);

106
tests/qtest/libqos/ahci.c
View File

@ -404,57 +404,110 @@ void ahci_port_clear(AHCIQState *ahci, uint8_t port)
/**
* Check a port for errors.
*/
void ahci_port_check_error(AHCIQState *ahci, uint8_t port,
uint32_t imask, uint8_t emask)
void ahci_port_check_error(AHCIQState *ahci, AHCICommand *cmd)
{
uint8_t port = cmd->port;
uint32_t reg;
/* The upper 9 bits of the IS register all indicate errors. */
reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
reg &= ~imask;
reg >>= 23;
g_assert_cmphex(reg, ==, 0);
/* If expecting TF error, ensure that TFES is set. */
if (cmd->errors) {
reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
ASSERT_BIT_SET(reg, AHCI_PX_IS_TFES);
} else {
/* The upper 9 bits of the IS register all indicate errors. */
reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
reg &= ~cmd->interrupts;
reg >>= 23;
g_assert_cmphex(reg, ==, 0);
}
/* The Sata Error Register should be empty. */
/* The Sata Error Register should be empty, even when expecting TF error. */
reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
g_assert_cmphex(reg, ==, 0);
/* If expecting TF error, and TFES was set, perform error recovery
* (see AHCI 1.3 section 6.2.2.1) such that we can send new commands. */
if (cmd->errors) {
/* This will clear PxCI. */
ahci_px_clr(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST);
/* The port has 500ms to disengage. */
usleep(500000);
reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
/* Clear PxIS. */
reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
ahci_px_wreg(ahci, port, AHCI_PX_IS, reg);
/* Check if we need to perform a COMRESET.
* Not implemented right now, as there is no reason why our QEMU model
* should need a COMRESET when expecting TF error. */
reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ);
/* Enable issuing new commands. */
ahci_px_set(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST);
}
/* The TFD also has two error sections. */
reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
if (!emask) {
if (!cmd->errors) {
ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
} else {
ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
}
ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR & (~emask << 8));
ASSERT_BIT_SET(reg, AHCI_PX_TFD_ERR & (emask << 8));
ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR & (~cmd->errors << 8));
ASSERT_BIT_SET(reg, AHCI_PX_TFD_ERR & (cmd->errors << 8));
}
void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port,
uint32_t intr_mask)
void ahci_port_check_interrupts(AHCIQState *ahci, AHCICommand *cmd)
{
uint8_t port = cmd->port;
uint32_t reg;
/* If we expect errors, error handling in ahci_port_check_error() will
* already have cleared PxIS, so in that case this function cannot verify
* and clear expected interrupts. */
if (cmd->errors) {
return;
}
/* Check for expected interrupts */
reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
ASSERT_BIT_SET(reg, intr_mask);
ASSERT_BIT_SET(reg, cmd->interrupts);
/* Clear expected interrupts and assert all interrupts now cleared. */
ahci_px_wreg(ahci, port, AHCI_PX_IS, intr_mask);
ahci_px_wreg(ahci, port, AHCI_PX_IS, cmd->interrupts);
g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
}
void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot)
void ahci_port_check_nonbusy(AHCIQState *ahci, AHCICommand *cmd)
{
uint8_t slot = cmd->slot;
uint8_t port = cmd->port;
uint32_t reg;
/* Assert that the command slot is no longer busy (NCQ) */
/* For NCQ command with error PxSACT bit should still be set.
* For NCQ command without error, PxSACT bit should be cleared.
* For non-NCQ command, PxSACT bit should always be cleared. */
reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
ASSERT_BIT_CLEAR(reg, (1 << slot));
if (cmd->props->ncq && cmd->errors) {
ASSERT_BIT_SET(reg, (1 << slot));
} else {
ASSERT_BIT_CLEAR(reg, (1 << slot));
}
/* Non-NCQ */
/* For non-NCQ command with error, PxCI bit should still be set.
* For non-NCQ command without error, PxCI bit should be cleared.
* For NCQ command without error, PxCI bit should be cleared.
* For NCQ command with error, PxCI bit may or may not be cleared. */
reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
ASSERT_BIT_CLEAR(reg, (1 << slot));
if (!cmd->props->ncq && cmd->errors) {
ASSERT_BIT_SET(reg, (1 << slot));
} else if (!cmd->errors) {
ASSERT_BIT_CLEAR(reg, (1 << slot));
}
/* And assert that we are generally not busy. */
reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
@ -1207,9 +1260,10 @@ void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd)
#define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK)))
while (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) ||
RSET(AHCI_PX_CI, 1 << cmd->slot) ||
(cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot))) {
while (!RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_ERR) &&
(RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) ||
RSET(AHCI_PX_CI, 1 << cmd->slot) ||
(cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot)))) {
usleep(50);
}
@ -1226,9 +1280,9 @@ void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd)
uint8_t slot = cmd->slot;
uint8_t port = cmd->port;
ahci_port_check_error(ahci, port, cmd->interrupts, cmd->errors);
ahci_port_check_interrupts(ahci, port, cmd->interrupts);
ahci_port_check_nonbusy(ahci, port, slot);
ahci_port_check_nonbusy(ahci, cmd);
ahci_port_check_error(ahci, cmd);
ahci_port_check_interrupts(ahci, cmd);
ahci_port_check_cmd_sanity(ahci, cmd);
if (cmd->interrupts & AHCI_PX_IS_DHRS) {
ahci_port_check_d2h_sanity(ahci, port, slot);

8
tests/qtest/libqos/ahci.h
View File

@ -590,11 +590,9 @@ void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot);
/* AHCI sanity check routines */
void ahci_port_check_error(AHCIQState *ahci, uint8_t port,
uint32_t imask, uint8_t emask);
void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port,
uint32_t intr_mask);
void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot);
void ahci_port_check_error(AHCIQState *ahci, AHCICommand *cmd);
void ahci_port_check_interrupts(AHCIQState *ahci, AHCICommand *cmd);
void ahci_port_check_nonbusy(AHCIQState *ahci, AHCICommand *cmd);
void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot);
void ahci_port_check_pio_sanity(AHCIQState *ahci, AHCICommand *cmd);
void ahci_port_check_cmd_sanity(AHCIQState *ahci, AHCICommand *cmd);