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hw/isa/piix4: QOM'ify PIIX4 PM creation

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Just like the real hardware, create the PIIX4 ACPI controller as part of
the PIIX4 southbridge. This also mirrors how the IDE and USB functions
are already created.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20220603185045.143789-7-shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Bernhard Beschow 2022-06-03 20:50:40 +02:00 committed by Philippe Mathieu-Daudé
parent e3d198eed1
commit 19e375db22
3 changed files with 18 additions and 13 deletions
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24
hw/isa/piix4.c
View File

@ -49,6 +49,7 @@ struct PIIX4State {
RTCState rtc;
PCIIDEState ide;
UHCIState uhci;
PIIX4PMState pm;
/* Reset Control Register */
MemoryRegion rcr_mem;
uint8_t rcr;
@ -261,6 +262,13 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return;
}
/* ACPI controller */
qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3);
if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
return;
}
qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]);
pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
}
@ -271,6 +279,10 @@ static void piix4_init(Object *obj)
object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", &s->ide, "piix4-ide");
object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci");
object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM);
qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100);
qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0);
}
static void piix4_class_init(ObjectClass *klass, void *data)
@ -312,7 +324,7 @@ static void piix4_register_types(void)
type_init(piix4_register_types)
DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus)
DeviceState *piix4_create(PCIBus *pci_bus)
{
PCIDevice *pci;
DeviceState *dev;
@ -322,15 +334,5 @@ DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus)
TYPE_PIIX4_PCI_DEVICE);
dev = DEVICE(pci);
if (smbus) {
pci = pci_new(devfn + 3, TYPE_PIIX4_PM);
qdev_prop_set_uint32(DEVICE(pci), "smb_io_base", 0x1100);
qdev_prop_set_bit(DEVICE(pci), "smm-enabled", 0);
pci_realize_and_unref(pci, pci_bus, &error_fatal);
qdev_connect_gpio_out(DEVICE(pci), 0,
qdev_get_gpio_in_named(dev, "isa", 9));
*smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pci), "i2c"));
}
return dev;
}

5
hw/mips/malta.c
View File

@ -1238,6 +1238,7 @@ void mips_malta_init(MachineState *machine)
int be;
MaltaState *s;
DeviceState *dev;
DeviceState *pm_dev;
s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA));
sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
@ -1399,8 +1400,10 @@ void mips_malta_init(MachineState *machine)
empty_slot_init("GT64120", 0, 0x20000000);
/* Southbridge */
dev = piix4_create(pci_bus, &smbus);
dev = piix4_create(pci_bus);
isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
pm_dev = DEVICE(object_resolve_path_component(OBJECT(dev), "pm"));
smbus = I2C_BUS(qdev_get_child_bus(pm_dev, "i2c"));
/* Interrupt controller */
qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);

2
include/hw/southbridge/piix.h
View File

@ -70,6 +70,6 @@ DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE,
PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus);
DeviceState *piix4_create(PCIBus *pci_bus);
#endif