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hw/hppa/dino.c: Improve emulation of Dino PCI chip
The tests of the dino chip with the Online-diagnostics CD
("ODE DINOTEST") now succeeds.
Additionally add some qemu trace events.
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191220211512.3289-2-svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Helge Deller
Richard Henderson
parent
105b07f1ba
commit
18092598a5
@ -890,7 +890,7 @@ F: hw/*/etraxfs_*.c
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HP-PARISC Machines
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------------------
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Dino
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HP B160L
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M: Richard Henderson <rth@twiddle.net>
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R: Helge Deller <deller@gmx.de>
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S: Odd Fixes
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@ -1,7 +1,7 @@
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/*
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* HP-PARISC Dino PCI chipset emulation.
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* HP-PARISC Dino PCI chipset emulation, as in B160L and similiar machines
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*
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* (C) 2017 by Helge Deller <deller@gmx.de>
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* (C) 2017-2019 by Helge Deller <deller@gmx.de>
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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@ -21,6 +21,7 @@
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#include "migration/vmstate.h"
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#include "hppa_sys.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"
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@ -82,11 +83,28 @@
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#define DINO_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)
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#define DINO800_REGS ((DINO_TLTIM - DINO_GMASK) / 4)
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static const uint32_t reg800_keep_bits[DINO800_REGS] = {
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MAKE_64BIT_MASK(0, 1),
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MAKE_64BIT_MASK(0, 7),
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MAKE_64BIT_MASK(0, 7),
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MAKE_64BIT_MASK(0, 8),
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MAKE_64BIT_MASK(0, 7),
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MAKE_64BIT_MASK(0, 9),
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MAKE_64BIT_MASK(0, 32),
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MAKE_64BIT_MASK(0, 8),
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MAKE_64BIT_MASK(0, 30),
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MAKE_64BIT_MASK(0, 25),
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MAKE_64BIT_MASK(0, 22),
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MAKE_64BIT_MASK(0, 9),
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};
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typedef struct DinoState {
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PCIHostState parent_obj;
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/* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops,
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so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. */
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uint32_t config_reg_dino; /* keep original copy, including 2 lowest bits */
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uint32_t iar0;
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uint32_t iar1;
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@ -94,8 +112,12 @@ typedef struct DinoState {
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uint32_t ipr;
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uint32_t icr;
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uint32_t ilr;
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uint32_t io_fbb_en;
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uint32_t io_addr_en;
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uint32_t io_control;
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uint32_t toc_addr;
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uint32_t reg800[DINO800_REGS];
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MemoryRegion this_mem;
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MemoryRegion pci_mem;
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@ -106,8 +128,6 @@ typedef struct DinoState {
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MemoryRegion bm_ram_alias;
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MemoryRegion bm_pci_alias;
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MemoryRegion bm_cpu_alias;
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MemoryRegion cpu0_eir_mem;
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} DinoState;
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/*
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@ -122,6 +142,8 @@ static void gsc_to_pci_forwarding(DinoState *s)
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tmp = extract32(s->io_control, 7, 2);
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enabled = (tmp == 0x01);
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io_addr_en = s->io_addr_en;
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/* Mask out first (=firmware) and last (=Dino) areas. */
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io_addr_en &= ~(BIT(31) | BIT(0));
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memory_region_transaction_begin();
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for (i = 1; i < 31; i++) {
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@ -142,6 +164,8 @@ static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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bool ret = false;
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switch (addr) {
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case DINO_IAR0:
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case DINO_IAR1:
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@ -152,16 +176,22 @@ static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
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case DINO_ICR:
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case DINO_ILR:
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case DINO_IO_CONTROL:
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case DINO_IO_FBB_EN:
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case DINO_IO_ADDR_EN:
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case DINO_PCI_IO_DATA:
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return true;
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case DINO_TOC_ADDR:
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case DINO_GMASK ... DINO_TLTIM:
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ret = true;
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break;
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case DINO_PCI_IO_DATA + 2:
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return size <= 2;
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ret = (size <= 2);
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break;
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case DINO_PCI_IO_DATA + 1:
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case DINO_PCI_IO_DATA + 3:
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return size == 1;
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ret = (size == 1);
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}
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return false;
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trace_dino_chip_mem_valid(addr, ret);
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return ret;
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}
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static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
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@ -194,6 +224,9 @@ static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
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}
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break;
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case DINO_IO_FBB_EN:
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val = s->io_fbb_en;
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break;
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case DINO_IO_ADDR_EN:
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val = s->io_addr_en;
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break;
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@ -227,12 +260,28 @@ static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
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case DINO_IRR1:
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val = s->ilr & s->imr & s->icr;
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break;
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case DINO_TOC_ADDR:
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val = s->toc_addr;
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break;
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case DINO_GMASK ... DINO_TLTIM:
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val = s->reg800[(addr - DINO_GMASK) / 4];
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if (addr == DINO_PAMR) {
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val &= ~0x01; /* LSB is hardwired to 0 */
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}
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if (addr == DINO_MLTIM) {
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val &= ~0x07; /* 3 LSB are hardwired to 0 */
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}
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if (addr == DINO_BRDG_FEAT) {
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val &= ~(0x10710E0ul | 8); /* bits 5-7, 24 & 15 reserved */
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}
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break;
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default:
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/* Controlled by dino_chip_mem_valid above. */
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g_assert_not_reached();
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}
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trace_dino_chip_read(addr, val);
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*data = val;
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return ret;
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}
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@ -245,6 +294,9 @@ static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
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AddressSpace *io;
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MemTxResult ret;
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uint16_t ioaddr;
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int i;
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trace_dino_chip_write(addr, val);
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switch (addr) {
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case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
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@ -266,9 +318,11 @@ static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
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}
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return ret;
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case DINO_IO_FBB_EN:
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s->io_fbb_en = val & 0x03;
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break;
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case DINO_IO_ADDR_EN:
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/* Never allow first (=firmware) and last (=Dino) areas. */
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s->io_addr_en = val & 0x7ffffffe;
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s->io_addr_en = val;
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gsc_to_pci_forwarding(s);
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break;
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case DINO_IO_CONTROL:
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@ -292,6 +346,10 @@ static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
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/* Any write to IPR clears the register. */
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s->ipr = 0;
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break;
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case DINO_TOC_ADDR:
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/* IO_COMMAND of CPU with client_id bits */
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s->toc_addr = 0xFFFA0030 | (val & 0x1e000);
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break;
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case DINO_ILR:
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case DINO_IRR0:
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@ -299,6 +357,12 @@ static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
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/* These registers are read-only. */
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break;
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case DINO_GMASK ... DINO_TLTIM:
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i = (addr - DINO_GMASK) / 4;
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val &= reg800_keep_bits[i];
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s->reg800[i] = val;
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break;
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default:
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/* Controlled by dino_chip_mem_valid above. */
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g_assert_not_reached();
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@ -323,7 +387,7 @@ static const MemoryRegionOps dino_chip_ops = {
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static const VMStateDescription vmstate_dino = {
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.name = "Dino",
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.version_id = 1,
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.version_id = 2,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(iar0, DinoState),
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@ -332,13 +396,14 @@ static const VMStateDescription vmstate_dino = {
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VMSTATE_UINT32(ipr, DinoState),
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VMSTATE_UINT32(icr, DinoState),
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VMSTATE_UINT32(ilr, DinoState),
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VMSTATE_UINT32(io_fbb_en, DinoState),
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VMSTATE_UINT32(io_addr_en, DinoState),
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VMSTATE_UINT32(io_control, DinoState),
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VMSTATE_UINT32(toc_addr, DinoState),
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VMSTATE_END_OF_LIST()
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}
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};
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/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. */
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static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
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@ -362,14 +427,16 @@ static const MemoryRegionOps dino_config_data_ops = {
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static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
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{
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PCIHostState *s = opaque;
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return s->config_reg;
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DinoState *s = opaque;
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return s->config_reg_dino;
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}
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static void dino_config_addr_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned len)
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{
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PCIHostState *s = opaque;
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DinoState *ds = opaque;
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ds->config_reg_dino = val; /* keep a copy of original value */
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s->config_reg = val & ~3U;
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}
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@ -453,6 +520,8 @@ PCIBus *dino_init(MemoryRegion *addr_space,
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dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE);
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s = DINO_PCI_HOST_BRIDGE(dev);
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s->iar0 = s->iar1 = CPU_HPA + 3;
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s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */
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/* Dino PCI access from main memory. */
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memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops,
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@ -2,3 +2,8 @@
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# pci.c
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hppa_pci_iack_write(void) ""
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# dino.c
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dino_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d"
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dino_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
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dino_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
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