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tricore patches
-----BEGIN PGP SIGNATURE----- iQJTBAABCgA9FiEEbmNqfoPy3Qz6bm43CtLGOWtpyhQFAlqZLo4fHGtiYXN0aWFu QG1haWwudW5pLXBhZGVyYm9ybi5kZQAKCRAK0sY5a2nKFP8VEAClWrhJeaOFTKzj hJNHs8SdvMHds6ikjXK45luMsz2UMKnOI3t8EOaYNaXjp29zNQIe43XNQKShfDt4 MrkJGOaHORxiIaZK0PQ3grRi/UnXvdO94jw4EjT+YaZFGpg9v4+h3NYd160tAbGj KLdkKQjIC4Gi/168RXUv3MmzJb/P0SWgmyYMss1D9wZXqdUrWAt7kGczrfakrx64 yiPUm01UJ4IDLj9BqGbn2lkvW8Qf+mKuvQOz+iUreZUV52Qi+PrfqvASE6d6Q/ik yoKWKCf/YKKsTcs0ZZhwyPUHNRL+G/wuk4+J5Mmo6CS54ze9NiPiNJEXU8RsLGX0 eh53of/xFk64wvPQAFXQ/h3aSoqTfBxy+4YTn/RTLZ67cd6EWZOcCegD+NccPuUx xpT98pU8FNck3QolvyHjhtsJ/DBc595Ihh33nUvI8uLm8wezDUcTA6LXwyUir6/9 ms25kX8CgsK165r8/FBSJzsouTjaaje9tRYsosvkOd308WNd0uZ6RyLX3jxrRs/g IwtgEnh3RY3I+WPuoq5HaHx4eW8KIfPjc/WRrU30XAMeznP4wXP3nS0Zx9xWgjVd tHxKeOIfc85sy2r6Jz47Wu7G7LTDYjY3tuZCBhQKkokQ8Rpex5i4HVhS8L+oOj8K 0RNHh4TARrELE3TDYsD1qj3WvalLCQ== =ubuC -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-2018-03-02' into staging tricore patches # gpg: Signature made Fri 02 Mar 2018 10:59:26 GMT # gpg: using RSA key 0AD2C6396B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" # Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14 * remotes/bkoppelmann/tags/pull-tricore-2018-03-02: tricore: renamed masking of PIE tricore: renamed masking of IE tricore: added CORE_ID tricore: added some missing cpu instructions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
136c67e078
@ -58,6 +58,7 @@ struct CPUTriCoreState {
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uint32_t PC;
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uint32_t SYSCON;
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uint32_t CPU_ID;
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uint32_t CORE_ID;
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uint32_t BIV;
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uint32_t BTV;
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uint32_t ISP;
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@ -228,7 +229,8 @@ void tricore_cpu_dump_state(CPUState *cpu, FILE *f,
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#define MASK_PCXI_PCPN 0xff000000
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#define MASK_PCXI_PIE 0x00800000
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#define MASK_PCXI_PIE_1_3 0x00800000
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#define MASK_PCXI_PIE_1_6 0x00200000
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#define MASK_PCXI_UL 0x00400000
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#define MASK_PCXI_PCXS 0x000f0000
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#define MASK_PCXI_PCXO 0x0000ffff
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@ -255,7 +257,8 @@ void tricore_cpu_dump_state(CPUState *cpu, FILE *f,
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#define MASK_CPUID_REV 0x000000ff
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#define MASK_ICR_PIPN 0x00ff0000
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#define MASK_ICR_IE 0x00000100
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#define MASK_ICR_IE_1_3 0x00000100
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#define MASK_ICR_IE_1_6 0x00008000
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#define MASK_ICR_CCPN 0x000000ff
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#define MASK_FCX_FCXS 0x000f0000
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@ -10,6 +10,7 @@ A(0xfe00, PCXI, TRICORE_FEATURE_13)
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A(0xfe08, PC, TRICORE_FEATURE_13)
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A(0xfe14, SYSCON, TRICORE_FEATURE_13)
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R(0xfe18, CPU_ID, TRICORE_FEATURE_13)
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R(0xfe1c, CORE_ID, TRICORE_FEATURE_161)
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E(0xfe20, BIV, TRICORE_FEATURE_13)
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E(0xfe24, BTV, TRICORE_FEATURE_13)
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E(0xfe28, ISP, TRICORE_FEATURE_13)
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@ -84,8 +84,8 @@ raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin,
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ICR.IE and ICR.CCPN are saved */
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/* PCXI.PIE = ICR.IE */
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env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
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((env->ICR & MASK_ICR_IE) << 15));
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env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
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((env->ICR & MASK_ICR_IE_1_3) << 15));
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/* PCXI.PCPN = ICR.CCPN */
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env->PCXI = (env->PCXI & 0xffffff) +
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((env->ICR & MASK_ICR_CCPN) << 24);
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@ -2464,8 +2464,8 @@ void helper_call(CPUTriCoreState *env, uint32_t next_pc)
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env->PCXI = (env->PCXI & 0xffffff) +
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((env->ICR & MASK_ICR_CCPN) << 24);
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/* PCXI.PIE = ICR.IE; */
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env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
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((env->ICR & MASK_ICR_IE) << 15));
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env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
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((env->ICR & MASK_ICR_IE_1_3) << 15));
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/* PCXI.UL = 1; */
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env->PCXI |= MASK_PCXI_UL;
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@ -2562,8 +2562,8 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9)
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env->PCXI = (env->PCXI & 0xffffff) +
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((env->ICR & MASK_ICR_CCPN) << 24);
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/* PCXI.PIE = ICR.IE */
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env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
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((env->ICR & MASK_ICR_IE) << 15));
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env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
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((env->ICR & MASK_ICR_IE_1_3) << 15));
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/* PCXI.UL = 0 */
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env->PCXI &= ~(MASK_PCXI_UL);
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/* PCXI[19: 0] = FCX[19: 0] */
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@ -2571,7 +2571,7 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9)
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/* FXC[19: 0] = new_FCX[19: 0] */
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env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
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/* ICR.IE = 1 */
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env->ICR |= MASK_ICR_IE;
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env->ICR |= MASK_ICR_IE_1_3;
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env->ICR |= const9; /* ICR.CCPN = const9[7: 0];*/
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@ -2603,7 +2603,8 @@ void helper_rfe(CPUTriCoreState *env)
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}
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env->PC = env->gpr_a[11] & ~0x1;
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/* ICR.IE = PCXI.PIE; */
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env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15);
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env->ICR = (env->ICR & ~MASK_ICR_IE_1_3)
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+ ((env->PCXI & MASK_PCXI_PIE_1_3) >> 15);
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/* ICR.CCPN = PCXI.PCPN; */
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env->ICR = (env->ICR & ~MASK_ICR_CCPN) +
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((env->PCXI & MASK_PCXI_PCPN) >> 24);
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@ -2627,8 +2628,8 @@ void helper_rfm(CPUTriCoreState *env)
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{
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env->PC = (env->gpr_a[11] & ~0x1);
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/* ICR.IE = PCXI.PIE; */
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env->ICR = (env->ICR & ~MASK_ICR_IE) |
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((env->PCXI & MASK_PCXI_PIE) >> 15);
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env->ICR = (env->ICR & ~MASK_ICR_IE_1_3)
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| ((env->PCXI & MASK_PCXI_PIE_1_3) >> 15);
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/* ICR.CCPN = PCXI.PCPN; */
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env->ICR = (env->ICR & ~MASK_ICR_CCPN) |
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((env->PCXI & MASK_PCXI_PCPN) >> 24);
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@ -2693,8 +2694,8 @@ void helper_svlcx(CPUTriCoreState *env)
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env->PCXI = (env->PCXI & 0xffffff) +
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((env->ICR & MASK_ICR_CCPN) << 24);
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/* PCXI.PIE = ICR.IE; */
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env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
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((env->ICR & MASK_ICR_IE) << 15));
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env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
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((env->ICR & MASK_ICR_IE_1_3) << 15));
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/* PCXI.UL = 0; */
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env->PCXI &= ~MASK_PCXI_UL;
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@ -2736,8 +2737,8 @@ void helper_svucx(CPUTriCoreState *env)
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env->PCXI = (env->PCXI & 0xffffff) +
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((env->ICR & MASK_ICR_CCPN) << 24);
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/* PCXI.PIE = ICR.IE; */
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env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
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((env->ICR & MASK_ICR_IE) << 15));
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env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
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((env->ICR & MASK_ICR_IE_1_3) << 15));
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/* PCXI.UL = 1; */
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env->PCXI |= MASK_PCXI_UL;
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@ -3389,10 +3389,18 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
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gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
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offset);
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break;
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case OPC1_16_SBR_JEQ2:
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gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
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offset + 16);
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break;
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case OPC1_16_SBR_JNE:
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gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
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offset);
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break;
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case OPC1_16_SBR_JNE2:
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gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
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offset + 16);
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break;
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case OPC1_16_SBR_JNZ:
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gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
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break;
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@ -4121,6 +4129,16 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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gen_compute_branch(ctx, op1, 0, 0, const16, address);
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break;
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/* SBR-format */
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case OPC1_16_SBR_JEQ2:
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case OPC1_16_SBR_JNE2:
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if (tricore_feature(env, TRICORE_FEATURE_16)) {
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r1 = MASK_OP_SBR_S2(ctx->opcode);
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address = MASK_OP_SBR_DISP4(ctx->opcode);
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gen_compute_branch(ctx, op1, r1, 0, 0, address);
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} else {
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generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
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}
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break;
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case OPC1_16_SBR_JEQ:
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case OPC1_16_SBR_JGEZ:
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case OPC1_16_SBR_JGTZ:
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@ -6256,6 +6274,15 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
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generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
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}
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break;
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case OPC2_32_RR_MOVS_64:
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if (tricore_feature(env, TRICORE_FEATURE_16)) {
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CHECK_REG_PAIR(r3);
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tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
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tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
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} else {
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generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
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}
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break;
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case OPC2_32_RR_NE:
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tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
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cpu_gpr_d[r2]);
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@ -8352,12 +8379,12 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
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/* raise EXCP_DEBUG */
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break;
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case OPC2_32_SYS_DISABLE:
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tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE);
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tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3);
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break;
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case OPC2_32_SYS_DSYNC:
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break;
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case OPC2_32_SYS_ENABLE:
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tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE);
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tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3);
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break;
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case OPC2_32_SYS_ISYNC:
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break;
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@ -313,6 +313,7 @@ enum {
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OPC1_16_SBC_JEQ = 0x1e,
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OPC1_16_SBC_JEQ2 = 0x9e,
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OPC1_16_SBR_JEQ = 0x3e,
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OPC1_16_SBR_JEQ2 = 0xbe,
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OPC1_16_SBR_JGEZ = 0xce,
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OPC1_16_SBR_JGTZ = 0x4e,
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OPC1_16_SR_JI = 0xdc,
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@ -321,6 +322,7 @@ enum {
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OPC1_16_SBC_JNE = 0x5e,
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OPC1_16_SBC_JNE2 = 0xde,
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OPC1_16_SBR_JNE = 0x7e,
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OPC1_16_SBR_JNE2 = 0xfe,
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OPC1_16_SB_JNZ = 0xee,
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OPC1_16_SBR_JNZ = 0xf6,
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OPC1_16_SBR_JNZ_A = 0x7c,
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@ -1064,6 +1066,7 @@ enum {
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OPC2_32_RR_MIN_H = 0x78,
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OPC2_32_RR_MIN_HU = 0x79,
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OPC2_32_RR_MOV = 0x1f,
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OPC2_32_RR_MOVS_64 = 0x80,
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OPC2_32_RR_MOV_64 = 0x81,
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OPC2_32_RR_NE = 0x11,
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OPC2_32_RR_OR_EQ = 0x27,
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