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target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6

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Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.

For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-12-16 12:14:00 +01:00
parent d913c3992d
commit 13514fc93e
5 changed files with 7 additions and 9 deletions
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3
linux-user/mips/cpu_loop.c
View File

@ -385,8 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
prog_req.fre &= interp_req.fre; prog_req.fre &= interp_req.fre;
bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 || bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
env->insn_flags & ISA_MIPS32R6 || env->insn_flags & ISA_MIPS32R6;
env->insn_flags & ISA_MIPS64R6;
if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
env->CP0_Config5 |= (1 << CP0C5_FRE); env->CP0_Config5 |= (1 << CP0C5_FRE);

6
target/mips/helper.c
View File

@ -1145,7 +1145,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
enter_debug_mode: enter_debug_mode:
if (env->insn_flags & ISA_MIPS3) { if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64; env->hflags |= MIPS_HFLAG_64;
if (!(env->insn_flags & ISA_MIPS64R6) || if (!(env->insn_flags & ISA_MIPS32R6) ||
env->CP0_Status & (1 << CP0St_KX)) { env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP; env->hflags &= ~MIPS_HFLAG_AWRAP;
} }
@ -1174,7 +1174,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
if (env->insn_flags & ISA_MIPS3) { if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64; env->hflags |= MIPS_HFLAG_64;
if (!(env->insn_flags & ISA_MIPS64R6) || if (!(env->insn_flags & ISA_MIPS32R6) ||
env->CP0_Status & (1 << CP0St_KX)) { env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP; env->hflags &= ~MIPS_HFLAG_AWRAP;
} }
@ -1360,7 +1360,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Status |= (1 << CP0St_EXL); env->CP0_Status |= (1 << CP0St_EXL);
if (env->insn_flags & ISA_MIPS3) { if (env->insn_flags & ISA_MIPS3) {
env->hflags |= MIPS_HFLAG_64; env->hflags |= MIPS_HFLAG_64;
if (!(env->insn_flags & ISA_MIPS64R6) || if (!(env->insn_flags & ISA_MIPS32R6) ||
env->CP0_Status & (1 << CP0St_KX)) { env->CP0_Status & (1 << CP0St_KX)) {
env->hflags &= ~MIPS_HFLAG_AWRAP; env->hflags &= ~MIPS_HFLAG_AWRAP;
} }

2
target/mips/internal.h
View File

@ -354,7 +354,7 @@ static inline void compute_hflags(CPUMIPSState *env)
} else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
!(env->CP0_Status & (1 << CP0St_UX))) { !(env->CP0_Status & (1 << CP0St_UX))) {
env->hflags |= MIPS_HFLAG_AWRAP; env->hflags |= MIPS_HFLAG_AWRAP;
} else if (env->insn_flags & ISA_MIPS64R6) { } else if (env->insn_flags & ISA_MIPS32R6) {
/* Address wrapping for Supervisor and Kernel is specified in R6 */ /* Address wrapping for Supervisor and Kernel is specified in R6 */
if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
!(env->CP0_Status & (1 << CP0St_SX))) || !(env->CP0_Status & (1 << CP0St_SX))) ||

3
target/mips/mips-defs.h
View File

@ -21,7 +21,6 @@
#define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_MIPS32R6 0x0000000000002000ULL
#define ISA_MIPS64R6 0x0000000000004000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL
/* /*
* bits 24-39: MIPS ASEs * bits 24-39: MIPS ASEs
@ -87,7 +86,7 @@
/* MIPS Technologies "Release 6" */ /* MIPS Technologies "Release 6" */
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
/* Wave Computing: "nanoMIPS" */ /* Wave Computing: "nanoMIPS" */
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)

2
target/mips/translate.c
View File

@ -31438,7 +31438,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
#else #else
ctx->mem_idx = hflags_mmu_index(ctx->hflags); ctx->mem_idx = hflags_mmu_index(ctx->hflags);
#endif #endif
ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | ISA_MIPS64R6 | ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 |
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,