mirror of
https://github.com/qemu/qemu.git
synced 2024-11-24 19:33:39 +08:00
Clean up fdc qdev conversion
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
a71836de38
commit
12a71a027c
139
hw/fdc.c
139
hw/fdc.c
@ -477,7 +477,6 @@ struct fdctrl_t {
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/* HW */
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qemu_irq irq;
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int dma_chann;
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target_phys_addr_t io_base;
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/* Controller state */
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QEMUTimer *result_timer;
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uint8_t sra;
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@ -512,8 +511,6 @@ struct fdctrl_t {
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/* Floppy drives */
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fdrive_t drives[MAX_FD];
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int reset_sensei;
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uint32_t strict_io;
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uint32_t mem_mapped;
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};
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static uint32_t fdctrl_read (void *opaque, uint32_t reg)
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@ -1855,39 +1852,12 @@ static void fdctrl_result_timer(void *opaque)
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}
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/* Init functions */
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static void fdctrl_init_common (fdctrl_t *fdctrl, int dma_chann,
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target_phys_addr_t io_base,
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BlockDriverState **fds)
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static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds)
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{
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int i, j;
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unsigned int i;
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/* Fill 'command_to_handler' lookup table */
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for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
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for (j = 0; j < sizeof(command_to_handler); j++) {
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if ((j & handlers[i].mask) == handlers[i].value)
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command_to_handler[j] = i;
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}
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}
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FLOPPY_DPRINTF("init controller\n");
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fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
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fdctrl->result_timer = qemu_new_timer(vm_clock,
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fdctrl_result_timer, fdctrl);
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fdctrl->version = 0x90; /* Intel 82078 controller */
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fdctrl->dma_chann = dma_chann;
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fdctrl->io_base = io_base;
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fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
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if (fdctrl->dma_chann != -1) {
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DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
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}
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for (i = 0; i < MAX_FD; i++) {
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fd_init(&fdctrl->drives[i], fds[i]);
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}
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fdctrl_external_reset(fdctrl);
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register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
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qemu_register_reset(fdctrl_external_reset, fdctrl);
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for (i = 0; i < MAX_FD; i++) {
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fd_revalidate(&fdctrl->drives[i]);
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}
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}
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@ -1901,9 +1871,6 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
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fdctrl_t *fdctrl;
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dev = qdev_create(NULL, "fdc");
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qdev_prop_set_uint32(dev, "strict_io", 0);
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qdev_prop_set_uint32(dev, "mem_mapped", mem_mapped);
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qdev_prop_set_uint32(dev, "sun4m", 0);
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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sysbus_connect_irq(s, 0, irq);
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@ -1920,8 +1887,10 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
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register_ioport_write((uint32_t)io_base + 0x07, 1, 1,
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&fdctrl_write_port, fdctrl);
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}
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fdctrl->dma_chann = dma_chann;
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DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
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fdctrl_init_common(fdctrl, dma_chann, io_base, fds);
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fdctrl_connect_drives(fdctrl, fds);
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return fdctrl;
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}
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@ -1933,10 +1902,7 @@ fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
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SysBusDevice *s;
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fdctrl_t *fdctrl;
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dev = qdev_create(NULL, "fdc");
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qdev_prop_set_uint32(dev, "strict_io", 1);
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qdev_prop_set_uint32(dev, "mem_mapped", 1);
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qdev_prop_set_uint32(dev, "sun4m", 1);
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dev = qdev_create(NULL, "SUNW,fdtwo");
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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sysbus_connect_irq(s, 0, irq);
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@ -1944,60 +1910,85 @@ fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
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*fdc_tc = qdev_get_gpio_in(dev, 0);
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fdctrl = FROM_SYSBUS(fdctrl_t, s);
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fdctrl_init_common(fdctrl, -1, io_base, fds);
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fdctrl->dma_chann = -1;
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fdctrl_connect_drives(fdctrl, fds);
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return fdctrl;
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}
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static void fdc_init1(SysBusDevice *dev)
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static void fdctrl_init_common(SysBusDevice *dev, fdctrl_t *fdctrl,
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int is_sun4m, int io)
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{
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fdctrl_t *s = FROM_SYSBUS(fdctrl_t, dev);
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int io;
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int i, j;
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static int command_tables_inited = 0;
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sysbus_init_irq(dev, &s->irq);
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sysbus_init_irq(dev, &fdctrl->irq);
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qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
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if (s->strict_io) {
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io = cpu_register_io_memory(fdctrl_mem_read_strict,
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fdctrl_mem_write_strict, s);
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} else {
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io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, s);
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}
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sysbus_init_mmio(dev, 0x08, io);
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/* Fill 'command_to_handler' lookup table */
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if (!command_tables_inited) {
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command_tables_inited = 1;
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for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
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for (j = 0; j < sizeof(command_to_handler); j++) {
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if ((j & handlers[i].mask) == handlers[i].value) {
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command_to_handler[j] = i;
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}
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}
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}
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}
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FLOPPY_DPRINTF("init controller\n");
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fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
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fdctrl->result_timer = qemu_new_timer(vm_clock,
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fdctrl_result_timer, fdctrl);
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fdctrl->version = 0x90; /* Intel 82078 controller */
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fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
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fdctrl->sun4m = is_sun4m;
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fdctrl_external_reset(fdctrl);
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register_savevm("fdc", -1, 2, fdc_save, fdc_load, fdctrl);
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qemu_register_reset(fdctrl_external_reset, fdctrl);
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}
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static void fdc_init1(SysBusDevice *dev)
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{
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fdctrl_t *fdctrl = FROM_SYSBUS(fdctrl_t, dev);
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int io;
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io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
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fdctrl_init_common(dev, fdctrl, 0, io);
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}
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static void sun4m_fdc_init1(SysBusDevice *dev)
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{
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fdctrl_t *fdctrl = FROM_SYSBUS(fdctrl_t, dev);
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int io;
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io = cpu_register_io_memory(fdctrl_mem_read_strict,
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fdctrl_mem_write_strict, fdctrl);
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fdctrl_init_common(dev, fdctrl, 1, io);
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}
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static SysBusDeviceInfo fdc_info = {
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.init = fdc_init1,
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.qdev.name = "fdc",
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.qdev.size = sizeof(fdctrl_t),
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.qdev.props = (Property[]) {
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{
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.name = "io_base",
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.info = &qdev_prop_taddr,
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.offset = offsetof(fdctrl_t, io_base),
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},
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{
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.name = "strict_io",
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.info = &qdev_prop_uint32,
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.offset = offsetof(fdctrl_t, strict_io),
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},
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{
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.name = "mem_mapped",
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.info = &qdev_prop_uint32,
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.offset = offsetof(fdctrl_t, mem_mapped),
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},
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{
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.name = "sun4m",
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.info = &qdev_prop_uint32,
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.offset = offsetof(fdctrl_t, sun4m),
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},
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{/* end of properties */}
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}
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};
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static SysBusDeviceInfo sun4m_fdc_info = {
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.init = sun4m_fdc_init1,
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.qdev.name = "SUNW,fdtwo",
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.qdev.size = sizeof(fdctrl_t),
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};
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static void fdc_register_devices(void)
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{
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sysbus_register_withprop(&fdc_info);
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sysbus_register_withprop(&sun4m_fdc_info);
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}
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device_init(fdc_register_devices)
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