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target/arm: Rewrite vector gather first-fault loads
This implements the feature for softmmu, and moves the main loop out of a macro and into a function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181005175350.30752-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
78cf1b886a
commit
116347ce20
@ -1401,69 +1401,111 @@ DEF_HELPER_FLAGS_6(sve_ldsds_be_zd, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffbsu_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhsu_zsu, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhsu_le_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffssu_zsu, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhsu_be_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffss_le_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffss_be_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffbss_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhss_zsu, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhss_le_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhss_be_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffbsu_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhsu_zss, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhsu_le_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffssu_zss, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhsu_be_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffss_le_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffss_be_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffbss_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhss_zss, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhss_le_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhss_be_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffbdu_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhdu_zsu, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhdu_le_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsdu_zsu, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhdu_be_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffddu_zsu, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffsdu_le_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsdu_be_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffdd_le_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffdd_be_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffbds_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhds_zsu, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhds_le_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsds_zsu, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhds_be_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsds_le_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsds_be_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffbdu_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhdu_zss, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhdu_le_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsdu_zss, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhdu_be_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffddu_zss, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffsdu_le_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsdu_be_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffdd_le_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffdd_be_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffbds_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhds_zss, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhds_le_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsds_zss, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhds_be_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsds_le_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsds_be_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffbdu_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhdu_zd, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhdu_le_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsdu_zd, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhdu_be_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffddu_zd, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffsdu_le_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsdu_be_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffdd_le_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffdd_be_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffbds_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffhds_zd, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhds_le_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsds_zd, TCG_CALL_NO_WG,
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DEF_HELPER_FLAGS_6(sve_ldffhds_be_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsds_le_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldffsds_be_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stbs_zsu, TCG_CALL_NO_WG,
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@ -5048,91 +5048,233 @@ DO_LD1_ZPZ_D(dd_be, zd)
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/* First fault loads with a vector index. */
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#ifdef CONFIG_USER_ONLY
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/* Load one element into VD+REG_OFF from (ENV,VADDR) without faulting.
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* The controlling predicate is known to be true. Return true if the
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* load was successful.
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*/
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typedef bool sve_ld1_nf_fn(CPUARMState *env, void *vd, intptr_t reg_off,
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target_ulong vaddr, int mmu_idx);
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#define DO_LDFF1_ZPZ(NAME, TYPEE, TYPEI, TYPEM, FN, H) \
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void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm, \
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target_ulong base, uint32_t desc) \
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{ \
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intptr_t i, oprsz = simd_oprsz(desc); \
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unsigned scale = simd_data(desc); \
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uintptr_t ra = GETPC(); \
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bool first = true; \
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mmap_lock(); \
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for (i = 0; i < oprsz; ) { \
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
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do { \
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TYPEM m = 0; \
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if (pg & 1) { \
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target_ulong off = *(TYPEI *)(vm + H(i)); \
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target_ulong addr = base + (off << scale); \
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if (!first && \
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page_check_range(addr, sizeof(TYPEM), PAGE_READ)) { \
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record_fault(env, i, oprsz); \
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goto exit; \
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} \
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m = FN(env, addr, ra); \
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first = false; \
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} \
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*(TYPEE *)(vd + H(i)) = m; \
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i += sizeof(TYPEE), pg >>= sizeof(TYPEE); \
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} while (i & 15); \
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} \
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exit: \
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mmap_unlock(); \
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#ifdef CONFIG_SOFTMMU
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#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
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static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
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target_ulong addr, int mmu_idx) \
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{ \
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target_ulong next_page = -(addr | TARGET_PAGE_MASK); \
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if (likely(next_page - addr >= sizeof(TYPEM))) { \
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void *host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_idx); \
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if (likely(host)) { \
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TYPEM val = HOST(host); \
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*(TYPEE *)(vd + H(reg_off)) = val; \
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return true; \
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} \
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} \
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return false; \
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}
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#else
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#define DO_LDFF1_ZPZ(NAME, TYPEE, TYPEI, TYPEM, FN, H) \
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void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm, \
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target_ulong base, uint32_t desc) \
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{ \
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g_assert_not_reached(); \
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#define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \
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static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off, \
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target_ulong addr, int mmu_idx) \
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{ \
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if (likely(page_check_range(addr, sizeof(TYPEM), PAGE_READ))) { \
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TYPEM val = HOST(g2h(addr)); \
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*(TYPEE *)(vd + H(reg_off)) = val; \
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return true; \
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} \
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return false; \
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}
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#endif
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#define DO_LDFF1_ZPZ_S(NAME, TYPEI, TYPEM, FN) \
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DO_LDFF1_ZPZ(NAME, uint32_t, TYPEI, TYPEM, FN, H1_4)
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#define DO_LDFF1_ZPZ_D(NAME, TYPEI, TYPEM, FN) \
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DO_LDFF1_ZPZ(NAME, uint64_t, TYPEI, TYPEM, FN, )
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DO_LD_NF(bsu, H1_4, uint32_t, uint8_t, ldub_p)
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DO_LD_NF(bss, H1_4, uint32_t, int8_t, ldsb_p)
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DO_LD_NF(bdu, , uint64_t, uint8_t, ldub_p)
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DO_LD_NF(bds, , uint64_t, int8_t, ldsb_p)
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DO_LDFF1_ZPZ_S(sve_ldffbsu_zsu, uint32_t, uint8_t, cpu_ldub_data_ra)
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DO_LDFF1_ZPZ_S(sve_ldffhsu_zsu, uint32_t, uint16_t, cpu_lduw_data_ra)
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DO_LDFF1_ZPZ_S(sve_ldffssu_zsu, uint32_t, uint32_t, cpu_ldl_data_ra)
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DO_LDFF1_ZPZ_S(sve_ldffbss_zsu, uint32_t, int8_t, cpu_ldub_data_ra)
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DO_LDFF1_ZPZ_S(sve_ldffhss_zsu, uint32_t, int16_t, cpu_lduw_data_ra)
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DO_LD_NF(hsu_le, H1_4, uint32_t, uint16_t, lduw_le_p)
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DO_LD_NF(hss_le, H1_4, uint32_t, int16_t, ldsw_le_p)
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DO_LD_NF(hsu_be, H1_4, uint32_t, uint16_t, lduw_be_p)
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DO_LD_NF(hss_be, H1_4, uint32_t, int16_t, ldsw_be_p)
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DO_LD_NF(hdu_le, , uint64_t, uint16_t, lduw_le_p)
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DO_LD_NF(hds_le, , uint64_t, int16_t, ldsw_le_p)
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DO_LD_NF(hdu_be, , uint64_t, uint16_t, lduw_be_p)
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DO_LD_NF(hds_be, , uint64_t, int16_t, ldsw_be_p)
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DO_LDFF1_ZPZ_S(sve_ldffbsu_zss, int32_t, uint8_t, cpu_ldub_data_ra)
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DO_LDFF1_ZPZ_S(sve_ldffhsu_zss, int32_t, uint16_t, cpu_lduw_data_ra)
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DO_LDFF1_ZPZ_S(sve_ldffssu_zss, int32_t, uint32_t, cpu_ldl_data_ra)
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DO_LDFF1_ZPZ_S(sve_ldffbss_zss, int32_t, int8_t, cpu_ldub_data_ra)
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DO_LDFF1_ZPZ_S(sve_ldffhss_zss, int32_t, int16_t, cpu_lduw_data_ra)
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DO_LD_NF(ss_le, H1_4, uint32_t, uint32_t, ldl_le_p)
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DO_LD_NF(ss_be, H1_4, uint32_t, uint32_t, ldl_be_p)
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DO_LD_NF(sdu_le, , uint64_t, uint32_t, ldl_le_p)
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DO_LD_NF(sds_le, , uint64_t, int32_t, ldl_le_p)
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DO_LD_NF(sdu_be, , uint64_t, uint32_t, ldl_be_p)
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DO_LD_NF(sds_be, , uint64_t, int32_t, ldl_be_p)
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DO_LDFF1_ZPZ_D(sve_ldffbdu_zsu, uint32_t, uint8_t, cpu_ldub_data_ra)
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DO_LDFF1_ZPZ_D(sve_ldffhdu_zsu, uint32_t, uint16_t, cpu_lduw_data_ra)
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DO_LDFF1_ZPZ_D(sve_ldffsdu_zsu, uint32_t, uint32_t, cpu_ldl_data_ra)
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DO_LDFF1_ZPZ_D(sve_ldffddu_zsu, uint32_t, uint64_t, cpu_ldq_data_ra)
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DO_LDFF1_ZPZ_D(sve_ldffbds_zsu, uint32_t, int8_t, cpu_ldub_data_ra)
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DO_LDFF1_ZPZ_D(sve_ldffhds_zsu, uint32_t, int16_t, cpu_lduw_data_ra)
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DO_LDFF1_ZPZ_D(sve_ldffsds_zsu, uint32_t, int32_t, cpu_ldl_data_ra)
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DO_LD_NF(dd_le, , uint64_t, uint64_t, ldq_le_p)
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DO_LD_NF(dd_be, , uint64_t, uint64_t, ldq_be_p)
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DO_LDFF1_ZPZ_D(sve_ldffbdu_zss, int32_t, uint8_t, cpu_ldub_data_ra)
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DO_LDFF1_ZPZ_D(sve_ldffhdu_zss, int32_t, uint16_t, cpu_lduw_data_ra)
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DO_LDFF1_ZPZ_D(sve_ldffsdu_zss, int32_t, uint32_t, cpu_ldl_data_ra)
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DO_LDFF1_ZPZ_D(sve_ldffddu_zss, int32_t, uint64_t, cpu_ldq_data_ra)
|
||||
DO_LDFF1_ZPZ_D(sve_ldffbds_zss, int32_t, int8_t, cpu_ldub_data_ra)
|
||||
DO_LDFF1_ZPZ_D(sve_ldffhds_zss, int32_t, int16_t, cpu_lduw_data_ra)
|
||||
DO_LDFF1_ZPZ_D(sve_ldffsds_zss, int32_t, int32_t, cpu_ldl_data_ra)
|
||||
/*
|
||||
* Common helper for all gather first-faulting loads.
|
||||
*/
|
||||
static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm,
|
||||
target_ulong base, uint32_t desc, uintptr_t ra,
|
||||
zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
|
||||
sve_ld1_nf_fn *nonfault_fn)
|
||||
{
|
||||
const int mmu_idx = cpu_mmu_index(env, false);
|
||||
intptr_t reg_off, reg_max = simd_oprsz(desc);
|
||||
unsigned scale = simd_data(desc);
|
||||
target_ulong addr;
|
||||
|
||||
DO_LDFF1_ZPZ_D(sve_ldffbdu_zd, uint64_t, uint8_t, cpu_ldub_data_ra)
|
||||
DO_LDFF1_ZPZ_D(sve_ldffhdu_zd, uint64_t, uint16_t, cpu_lduw_data_ra)
|
||||
DO_LDFF1_ZPZ_D(sve_ldffsdu_zd, uint64_t, uint32_t, cpu_ldl_data_ra)
|
||||
DO_LDFF1_ZPZ_D(sve_ldffddu_zd, uint64_t, uint64_t, cpu_ldq_data_ra)
|
||||
DO_LDFF1_ZPZ_D(sve_ldffbds_zd, uint64_t, int8_t, cpu_ldub_data_ra)
|
||||
DO_LDFF1_ZPZ_D(sve_ldffhds_zd, uint64_t, int16_t, cpu_lduw_data_ra)
|
||||
DO_LDFF1_ZPZ_D(sve_ldffsds_zd, uint64_t, int32_t, cpu_ldl_data_ra)
|
||||
/* Skip to the first true predicate. */
|
||||
reg_off = find_next_active(vg, 0, reg_max, MO_32);
|
||||
if (likely(reg_off < reg_max)) {
|
||||
/* Perform one normal read, which will fault or not. */
|
||||
set_helper_retaddr(ra);
|
||||
addr = off_fn(vm, reg_off);
|
||||
addr = base + (addr << scale);
|
||||
tlb_fn(env, vd, reg_off, addr, mmu_idx, ra);
|
||||
|
||||
/* The rest of the reads will be non-faulting. */
|
||||
set_helper_retaddr(0);
|
||||
}
|
||||
|
||||
/* After any fault, zero the leading predicated false elements. */
|
||||
swap_memzero(vd, reg_off);
|
||||
|
||||
while (likely((reg_off += 4) < reg_max)) {
|
||||
uint64_t pg = *(uint64_t *)(vg + (reg_off >> 6) * 8);
|
||||
if (likely((pg >> (reg_off & 63)) & 1)) {
|
||||
addr = off_fn(vm, reg_off);
|
||||
addr = base + (addr << scale);
|
||||
if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
|
||||
record_fault(env, reg_off, reg_max);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
*(uint32_t *)(vd + H1_4(reg_off)) = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm,
|
||||
target_ulong base, uint32_t desc, uintptr_t ra,
|
||||
zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn,
|
||||
sve_ld1_nf_fn *nonfault_fn)
|
||||
{
|
||||
const int mmu_idx = cpu_mmu_index(env, false);
|
||||
intptr_t reg_off, reg_max = simd_oprsz(desc);
|
||||
unsigned scale = simd_data(desc);
|
||||
target_ulong addr;
|
||||
|
||||
/* Skip to the first true predicate. */
|
||||
reg_off = find_next_active(vg, 0, reg_max, MO_64);
|
||||
if (likely(reg_off < reg_max)) {
|
||||
/* Perform one normal read, which will fault or not. */
|
||||
set_helper_retaddr(ra);
|
||||
addr = off_fn(vm, reg_off);
|
||||
addr = base + (addr << scale);
|
||||
tlb_fn(env, vd, reg_off, addr, mmu_idx, ra);
|
||||
|
||||
/* The rest of the reads will be non-faulting. */
|
||||
set_helper_retaddr(0);
|
||||
}
|
||||
|
||||
/* After any fault, zero the leading predicated false elements. */
|
||||
swap_memzero(vd, reg_off);
|
||||
|
||||
while (likely((reg_off += 8) < reg_max)) {
|
||||
uint8_t pg = *(uint8_t *)(vg + H1(reg_off >> 3));
|
||||
if (likely(pg & 1)) {
|
||||
addr = off_fn(vm, reg_off);
|
||||
addr = base + (addr << scale);
|
||||
if (!nonfault_fn(env, vd, reg_off, addr, mmu_idx)) {
|
||||
record_fault(env, reg_off, reg_max);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
*(uint64_t *)(vd + reg_off) = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define DO_LDFF1_ZPZ_S(MEM, OFS) \
|
||||
void HELPER(sve_ldff##MEM##_##OFS) \
|
||||
(CPUARMState *env, void *vd, void *vg, void *vm, \
|
||||
target_ulong base, uint32_t desc) \
|
||||
{ \
|
||||
sve_ldff1_zs(env, vd, vg, vm, base, desc, GETPC(), \
|
||||
off_##OFS##_s, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
|
||||
}
|
||||
|
||||
#define DO_LDFF1_ZPZ_D(MEM, OFS) \
|
||||
void HELPER(sve_ldff##MEM##_##OFS) \
|
||||
(CPUARMState *env, void *vd, void *vg, void *vm, \
|
||||
target_ulong base, uint32_t desc) \
|
||||
{ \
|
||||
sve_ldff1_zd(env, vd, vg, vm, base, desc, GETPC(), \
|
||||
off_##OFS##_d, sve_ld1##MEM##_tlb, sve_ld##MEM##_nf); \
|
||||
}
|
||||
|
||||
DO_LDFF1_ZPZ_S(bsu, zsu)
|
||||
DO_LDFF1_ZPZ_S(bsu, zss)
|
||||
DO_LDFF1_ZPZ_D(bdu, zsu)
|
||||
DO_LDFF1_ZPZ_D(bdu, zss)
|
||||
DO_LDFF1_ZPZ_D(bdu, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_S(bss, zsu)
|
||||
DO_LDFF1_ZPZ_S(bss, zss)
|
||||
DO_LDFF1_ZPZ_D(bds, zsu)
|
||||
DO_LDFF1_ZPZ_D(bds, zss)
|
||||
DO_LDFF1_ZPZ_D(bds, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_S(hsu_le, zsu)
|
||||
DO_LDFF1_ZPZ_S(hsu_le, zss)
|
||||
DO_LDFF1_ZPZ_D(hdu_le, zsu)
|
||||
DO_LDFF1_ZPZ_D(hdu_le, zss)
|
||||
DO_LDFF1_ZPZ_D(hdu_le, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_S(hsu_be, zsu)
|
||||
DO_LDFF1_ZPZ_S(hsu_be, zss)
|
||||
DO_LDFF1_ZPZ_D(hdu_be, zsu)
|
||||
DO_LDFF1_ZPZ_D(hdu_be, zss)
|
||||
DO_LDFF1_ZPZ_D(hdu_be, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_S(hss_le, zsu)
|
||||
DO_LDFF1_ZPZ_S(hss_le, zss)
|
||||
DO_LDFF1_ZPZ_D(hds_le, zsu)
|
||||
DO_LDFF1_ZPZ_D(hds_le, zss)
|
||||
DO_LDFF1_ZPZ_D(hds_le, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_S(hss_be, zsu)
|
||||
DO_LDFF1_ZPZ_S(hss_be, zss)
|
||||
DO_LDFF1_ZPZ_D(hds_be, zsu)
|
||||
DO_LDFF1_ZPZ_D(hds_be, zss)
|
||||
DO_LDFF1_ZPZ_D(hds_be, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_S(ss_le, zsu)
|
||||
DO_LDFF1_ZPZ_S(ss_le, zss)
|
||||
DO_LDFF1_ZPZ_D(sdu_le, zsu)
|
||||
DO_LDFF1_ZPZ_D(sdu_le, zss)
|
||||
DO_LDFF1_ZPZ_D(sdu_le, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_S(ss_be, zsu)
|
||||
DO_LDFF1_ZPZ_S(ss_be, zss)
|
||||
DO_LDFF1_ZPZ_D(sdu_be, zsu)
|
||||
DO_LDFF1_ZPZ_D(sdu_be, zss)
|
||||
DO_LDFF1_ZPZ_D(sdu_be, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_D(sds_le, zsu)
|
||||
DO_LDFF1_ZPZ_D(sds_le, zss)
|
||||
DO_LDFF1_ZPZ_D(sds_le, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_D(sds_be, zsu)
|
||||
DO_LDFF1_ZPZ_D(sds_be, zss)
|
||||
DO_LDFF1_ZPZ_D(sds_be, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_D(dd_le, zsu)
|
||||
DO_LDFF1_ZPZ_D(dd_le, zss)
|
||||
DO_LDFF1_ZPZ_D(dd_le, zd)
|
||||
|
||||
DO_LDFF1_ZPZ_D(dd_be, zsu)
|
||||
DO_LDFF1_ZPZ_D(dd_be, zss)
|
||||
DO_LDFF1_ZPZ_D(dd_be, zd)
|
||||
|
||||
/* Stores with a vector index. */
|
||||
|
||||
|
@ -5095,17 +5095,17 @@ static gen_helper_gvec_mem_scatter * const gather_load_fn32[2][2][2][2][3] = {
|
||||
|
||||
/* First-fault */
|
||||
{ { { gen_helper_sve_ldffbss_zsu,
|
||||
gen_helper_sve_ldffhss_zsu,
|
||||
gen_helper_sve_ldffhss_le_zsu,
|
||||
NULL, },
|
||||
{ gen_helper_sve_ldffbsu_zsu,
|
||||
gen_helper_sve_ldffhsu_zsu,
|
||||
gen_helper_sve_ldffssu_zsu, } },
|
||||
gen_helper_sve_ldffhsu_le_zsu,
|
||||
gen_helper_sve_ldffss_le_zsu, } },
|
||||
{ { gen_helper_sve_ldffbss_zss,
|
||||
gen_helper_sve_ldffhss_zss,
|
||||
gen_helper_sve_ldffhss_le_zss,
|
||||
NULL, },
|
||||
{ gen_helper_sve_ldffbsu_zss,
|
||||
gen_helper_sve_ldffhsu_zss,
|
||||
gen_helper_sve_ldffssu_zss, } } } },
|
||||
gen_helper_sve_ldffhsu_le_zss,
|
||||
gen_helper_sve_ldffss_le_zss, } } } },
|
||||
|
||||
/* Big-endian */
|
||||
{ { { { gen_helper_sve_ldbss_zsu,
|
||||
@ -5123,17 +5123,17 @@ static gen_helper_gvec_mem_scatter * const gather_load_fn32[2][2][2][2][3] = {
|
||||
|
||||
/* First-fault */
|
||||
{ { { gen_helper_sve_ldffbss_zsu,
|
||||
gen_helper_sve_ldffhss_zsu,
|
||||
gen_helper_sve_ldffhss_be_zsu,
|
||||
NULL, },
|
||||
{ gen_helper_sve_ldffbsu_zsu,
|
||||
gen_helper_sve_ldffhsu_zsu,
|
||||
gen_helper_sve_ldffssu_zsu, } },
|
||||
gen_helper_sve_ldffhsu_be_zsu,
|
||||
gen_helper_sve_ldffss_be_zsu, } },
|
||||
{ { gen_helper_sve_ldffbss_zss,
|
||||
gen_helper_sve_ldffhss_zss,
|
||||
gen_helper_sve_ldffhss_be_zss,
|
||||
NULL, },
|
||||
{ gen_helper_sve_ldffbsu_zss,
|
||||
gen_helper_sve_ldffhsu_zss,
|
||||
gen_helper_sve_ldffssu_zss, } } } },
|
||||
gen_helper_sve_ldffhsu_be_zss,
|
||||
gen_helper_sve_ldffss_be_zss, } } } },
|
||||
};
|
||||
|
||||
/* Note that we overload xs=2 to indicate 64-bit offset. */
|
||||
@ -5166,29 +5166,29 @@ static gen_helper_gvec_mem_scatter * const gather_load_fn64[2][2][3][2][4] = {
|
||||
|
||||
/* First-fault */
|
||||
{ { { gen_helper_sve_ldffbds_zsu,
|
||||
gen_helper_sve_ldffhds_zsu,
|
||||
gen_helper_sve_ldffsds_zsu,
|
||||
gen_helper_sve_ldffhds_le_zsu,
|
||||
gen_helper_sve_ldffsds_le_zsu,
|
||||
NULL, },
|
||||
{ gen_helper_sve_ldffbdu_zsu,
|
||||
gen_helper_sve_ldffhdu_zsu,
|
||||
gen_helper_sve_ldffsdu_zsu,
|
||||
gen_helper_sve_ldffddu_zsu, } },
|
||||
gen_helper_sve_ldffhdu_le_zsu,
|
||||
gen_helper_sve_ldffsdu_le_zsu,
|
||||
gen_helper_sve_ldffdd_le_zsu, } },
|
||||
{ { gen_helper_sve_ldffbds_zss,
|
||||
gen_helper_sve_ldffhds_zss,
|
||||
gen_helper_sve_ldffsds_zss,
|
||||
gen_helper_sve_ldffhds_le_zss,
|
||||
gen_helper_sve_ldffsds_le_zss,
|
||||
NULL, },
|
||||
{ gen_helper_sve_ldffbdu_zss,
|
||||
gen_helper_sve_ldffhdu_zss,
|
||||
gen_helper_sve_ldffsdu_zss,
|
||||
gen_helper_sve_ldffddu_zss, } },
|
||||
gen_helper_sve_ldffhdu_le_zss,
|
||||
gen_helper_sve_ldffsdu_le_zss,
|
||||
gen_helper_sve_ldffdd_le_zss, } },
|
||||
{ { gen_helper_sve_ldffbds_zd,
|
||||
gen_helper_sve_ldffhds_zd,
|
||||
gen_helper_sve_ldffsds_zd,
|
||||
gen_helper_sve_ldffhds_le_zd,
|
||||
gen_helper_sve_ldffsds_le_zd,
|
||||
NULL, },
|
||||
{ gen_helper_sve_ldffbdu_zd,
|
||||
gen_helper_sve_ldffhdu_zd,
|
||||
gen_helper_sve_ldffsdu_zd,
|
||||
gen_helper_sve_ldffddu_zd, } } } },
|
||||
gen_helper_sve_ldffhdu_le_zd,
|
||||
gen_helper_sve_ldffsdu_le_zd,
|
||||
gen_helper_sve_ldffdd_le_zd, } } } },
|
||||
|
||||
/* Big-endian */
|
||||
{ { { { gen_helper_sve_ldbds_zsu,
|
||||
@ -5218,29 +5218,29 @@ static gen_helper_gvec_mem_scatter * const gather_load_fn64[2][2][3][2][4] = {
|
||||
|
||||
/* First-fault */
|
||||
{ { { gen_helper_sve_ldffbds_zsu,
|
||||
gen_helper_sve_ldffhds_zsu,
|
||||
gen_helper_sve_ldffsds_zsu,
|
||||
gen_helper_sve_ldffhds_be_zsu,
|
||||
gen_helper_sve_ldffsds_be_zsu,
|
||||
NULL, },
|
||||
{ gen_helper_sve_ldffbdu_zsu,
|
||||
gen_helper_sve_ldffhdu_zsu,
|
||||
gen_helper_sve_ldffsdu_zsu,
|
||||
gen_helper_sve_ldffddu_zsu, } },
|
||||
gen_helper_sve_ldffhdu_be_zsu,
|
||||
gen_helper_sve_ldffsdu_be_zsu,
|
||||
gen_helper_sve_ldffdd_be_zsu, } },
|
||||
{ { gen_helper_sve_ldffbds_zss,
|
||||
gen_helper_sve_ldffhds_zss,
|
||||
gen_helper_sve_ldffsds_zss,
|
||||
gen_helper_sve_ldffhds_be_zss,
|
||||
gen_helper_sve_ldffsds_be_zss,
|
||||
NULL, },
|
||||
{ gen_helper_sve_ldffbdu_zss,
|
||||
gen_helper_sve_ldffhdu_zss,
|
||||
gen_helper_sve_ldffsdu_zss,
|
||||
gen_helper_sve_ldffddu_zss, } },
|
||||
gen_helper_sve_ldffhdu_be_zss,
|
||||
gen_helper_sve_ldffsdu_be_zss,
|
||||
gen_helper_sve_ldffdd_be_zss, } },
|
||||
{ { gen_helper_sve_ldffbds_zd,
|
||||
gen_helper_sve_ldffhds_zd,
|
||||
gen_helper_sve_ldffsds_zd,
|
||||
gen_helper_sve_ldffhds_be_zd,
|
||||
gen_helper_sve_ldffsds_be_zd,
|
||||
NULL, },
|
||||
{ gen_helper_sve_ldffbdu_zd,
|
||||
gen_helper_sve_ldffhdu_zd,
|
||||
gen_helper_sve_ldffsdu_zd,
|
||||
gen_helper_sve_ldffddu_zd, } } } },
|
||||
gen_helper_sve_ldffhdu_be_zd,
|
||||
gen_helper_sve_ldffsdu_be_zd,
|
||||
gen_helper_sve_ldffdd_be_zd, } } } },
|
||||
};
|
||||
|
||||
static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a, uint32_t insn)
|
||||
|
Loading…
Reference in New Issue
Block a user