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xics: pass appropriate types to realize() handlers.

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It makes more sense to pass an IPCState * to handlers of ICPStateClass
instead of a DeviceState *, if only to benefit from compile time type
checking. The same goes with ICSStateClass.

While here, we also change the declaration of ICPStateClass in xics.h
for consistency.

Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Greg Kurz 2017-06-08 15:42:50 +02:00 committed by David Gibson
parent ad265631c0
commit 100f738850
4 changed files with 13 additions and 17 deletions
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10
hw/intc/xics.c
View File

@ -356,7 +356,7 @@ static void icp_realize(DeviceState *dev, Error **errp)
icp->xics = XICS_FABRIC(obj);
if (icpc->realize) {
icpc->realize(dev, errp);
icpc->realize(icp, errp);
}
qemu_register_reset(icp_reset, dev);
@ -606,10 +606,8 @@ static void ics_simple_initfn(Object *obj)
ics->offset = XICS_IRQ_BASE;
}
static void ics_simple_realize(DeviceState *dev, Error **errp)
static void ics_simple_realize(ICSState *ics, Error **errp)
{
ICSState *ics = ICS_SIMPLE(dev);
if (!ics->nr_irqs) {
error_setg(errp, "Number of interrupts needs to be greater 0");
return;
@ -617,7 +615,7 @@ static void ics_simple_realize(DeviceState *dev, Error **errp)
ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
qemu_register_reset(ics_simple_reset, dev);
qemu_register_reset(ics_simple_reset, ics);
}
static Property ics_simple_properties[] = {
@ -664,7 +662,7 @@ static void ics_base_realize(DeviceState *dev, Error **errp)
if (icsc->realize) {
icsc->realize(dev, errp);
icsc->realize(ics, errp);
}
}

6
hw/intc/xics_kvm.c
View File

@ -328,10 +328,8 @@ static void ics_kvm_reset(void *dev)
ics_set_kvm_state(ics, 1);
}
static void ics_kvm_realize(DeviceState *dev, Error **errp)
static void ics_kvm_realize(ICSState *ics, Error **errp)
{
ICSState *ics = ICS_SIMPLE(dev);
if (!ics->nr_irqs) {
error_setg(errp, "Number of interrupts needs to be greater 0");
return;
@ -339,7 +337,7 @@ static void ics_kvm_realize(DeviceState *dev, Error **errp)
ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
ics->qirqs = qemu_allocate_irqs(ics_kvm_set_irq, ics, ics->nr_irqs);
qemu_register_reset(ics_kvm_reset, dev);
qemu_register_reset(ics_kvm_reset, ics);
}
static void ics_kvm_class_init(ObjectClass *klass, void *data)

6
hw/intc/xics_pnv.c
View File

@ -159,11 +159,11 @@ static const MemoryRegionOps pnv_icp_ops = {
},
};
static void pnv_icp_realize(DeviceState *dev, Error **errp)
static void pnv_icp_realize(ICPState *icp, Error **errp)
{
PnvICPState *icp = PNV_ICP(dev);
PnvICPState *pnv_icp = PNV_ICP(icp);
memory_region_init_io(&icp->mmio, OBJECT(dev), &pnv_icp_ops,
memory_region_init_io(&pnv_icp->mmio, OBJECT(icp), &pnv_icp_ops,
icp, "icp-thread", 0x1000);
}

8
include/hw/ppc/xics.h
View File

@ -65,9 +65,9 @@ typedef struct XICSFabric XICSFabric;
struct ICPStateClass {
DeviceClass parent_class;
void (*realize)(DeviceState *dev, Error **errp);
void (*pre_save)(ICPState *s);
int (*post_load)(ICPState *s, int version_id);
void (*realize)(ICPState *icp, Error **errp);
void (*pre_save)(ICPState *icp);
int (*post_load)(ICPState *icp, int version_id);
void (*cpu_setup)(ICPState *icp, PowerPCCPU *cpu);
void (*reset)(ICPState *icp);
};
@ -113,7 +113,7 @@ struct PnvICPState {
struct ICSStateClass {
DeviceClass parent_class;
void (*realize)(DeviceState *dev, Error **errp);
void (*realize)(ICSState *s, Error **errp);
void (*pre_save)(ICSState *s);
int (*post_load)(ICSState *s, int version_id);
void (*reject)(ICSState *s, uint32_t irq);