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target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions
are supposed to be testing fields in ID_MMFR3; but a cut-and-paste
error meant we were looking at MVFR0 instead.
Fix the functions to look at the right register; this requires
us to move at least id_mmfr3 to the ARMISARegisters struct; we
choose to move all the ID_MMFRn registers for consistency.
Fixes: 3d6ad6bb46
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214175116.9164-19-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
62d96ff485
commit
10054016ed
@ -1231,13 +1231,13 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
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case 0xd4c: /* AFR0. */
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return cpu->id_afr0;
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case 0xd50: /* MMFR0. */
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return cpu->id_mmfr0;
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return cpu->isar.id_mmfr0;
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case 0xd54: /* MMFR1. */
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return cpu->id_mmfr1;
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return cpu->isar.id_mmfr1;
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case 0xd58: /* MMFR2. */
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return cpu->id_mmfr2;
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return cpu->isar.id_mmfr2;
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case 0xd5c: /* MMFR3. */
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return cpu->id_mmfr3;
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return cpu->isar.id_mmfr3;
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case 0xd60: /* ISAR0. */
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return cpu->isar.id_isar0;
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case 0xd64: /* ISAR1. */
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104
target/arm/cpu.c
104
target/arm/cpu.c
@ -1960,9 +1960,9 @@ static void arm1136_r2_initfn(Object *obj)
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->isar.id_mmfr0 = 0x01130003;
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cpu->isar.id_mmfr1 = 0x10030302;
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cpu->isar.id_mmfr2 = 0x01222110;
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cpu->isar.id_isar0 = 0x00140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231111;
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@ -1992,9 +1992,9 @@ static void arm1136_initfn(Object *obj)
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->isar.id_mmfr0 = 0x01130003;
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cpu->isar.id_mmfr1 = 0x10030302;
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cpu->isar.id_mmfr2 = 0x01222110;
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cpu->isar.id_isar0 = 0x00140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231111;
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@ -2025,9 +2025,9 @@ static void arm1176_initfn(Object *obj)
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x33;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222100;
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cpu->isar.id_mmfr0 = 0x01130003;
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cpu->isar.id_mmfr1 = 0x10030302;
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cpu->isar.id_mmfr2 = 0x01222100;
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cpu->isar.id_isar0 = 0x0140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231121;
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@ -2055,9 +2055,9 @@ static void arm11mpcore_initfn(Object *obj)
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0;
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cpu->id_afr0 = 0x2;
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cpu->id_mmfr0 = 0x01100103;
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cpu->id_mmfr1 = 0x10020302;
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cpu->id_mmfr2 = 0x01222000;
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cpu->isar.id_mmfr0 = 0x01100103;
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cpu->isar.id_mmfr1 = 0x10020302;
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cpu->isar.id_mmfr2 = 0x01222000;
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cpu->isar.id_isar0 = 0x00100011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11221011;
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@ -2087,10 +2087,10 @@ static void cortex_m3_initfn(Object *obj)
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00000030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x00000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x00000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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@ -2118,10 +2118,10 @@ static void cortex_m4_initfn(Object *obj)
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00000030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x00000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x00000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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@ -2149,10 +2149,10 @@ static void cortex_m7_initfn(Object *obj)
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00100030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00100030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01101110;
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cpu->isar.id_isar1 = 0x02112000;
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cpu->isar.id_isar2 = 0x20232231;
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@ -2182,10 +2182,10 @@ static void cortex_m33_initfn(Object *obj)
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cpu->id_pfr1 = 0x00000210;
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cpu->isar.id_dfr0 = 0x00200000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00101F40;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00101F40;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01101110;
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cpu->isar.id_isar1 = 0x02212000;
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cpu->isar.id_isar2 = 0x20232232;
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@ -2234,10 +2234,10 @@ static void cortex_r5_initfn(Object *obj)
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cpu->id_pfr1 = 0x001;
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cpu->isar.id_dfr0 = 0x010400;
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cpu->id_afr0 = 0x0;
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cpu->id_mmfr0 = 0x0210030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01200000;
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cpu->id_mmfr3 = 0x0211;
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cpu->isar.id_mmfr0 = 0x0210030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01200000;
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cpu->isar.id_mmfr3 = 0x0211;
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cpu->isar.id_isar0 = 0x02101111;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232141;
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@ -2289,10 +2289,10 @@ static void cortex_a8_initfn(Object *obj)
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x400;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x31100003;
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01202000;
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cpu->id_mmfr3 = 0x11;
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cpu->isar.id_mmfr0 = 0x31100003;
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cpu->isar.id_mmfr1 = 0x20000000;
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cpu->isar.id_mmfr2 = 0x01202000;
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cpu->isar.id_mmfr3 = 0x11;
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cpu->isar.id_isar0 = 0x00101111;
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cpu->isar.id_isar1 = 0x12112111;
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cpu->isar.id_isar2 = 0x21232031;
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@ -2362,10 +2362,10 @@ static void cortex_a9_initfn(Object *obj)
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x000;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x00100103;
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01230000;
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cpu->id_mmfr3 = 0x00002111;
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cpu->isar.id_mmfr0 = 0x00100103;
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cpu->isar.id_mmfr1 = 0x20000000;
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cpu->isar.id_mmfr2 = 0x01230000;
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cpu->isar.id_mmfr3 = 0x00002111;
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cpu->isar.id_isar0 = 0x00101111;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232041;
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@ -2427,10 +2427,10 @@ static void cortex_a7_initfn(Object *obj)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x02010555;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01240000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10101105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01240000;
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cpu->isar.id_mmfr3 = 0x02102211;
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/* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
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* table 4-41 gives 0x02101110, which includes the arm div insns.
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*/
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@ -2473,10 +2473,10 @@ static void cortex_a15_initfn(Object *obj)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x02010555;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10201105;
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01240000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10201105;
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cpu->isar.id_mmfr1 = 0x20000000;
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cpu->isar.id_mmfr2 = 0x01240000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232041;
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@ -2712,13 +2712,13 @@ static void arm_max_initfn(Object *obj)
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t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
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cpu->isar.mvfr2 = t;
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t = cpu->id_mmfr3;
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t = cpu->isar.id_mmfr3;
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t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
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cpu->id_mmfr3 = t;
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cpu->isar.id_mmfr3 = t;
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t = cpu->id_mmfr4;
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t = cpu->isar.id_mmfr4;
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t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
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cpu->id_mmfr4 = t;
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cpu->isar.id_mmfr4 = t;
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}
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#endif
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}
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@ -867,6 +867,11 @@ struct ARMCPU {
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uint32_t id_isar4;
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uint32_t id_isar5;
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uint32_t id_isar6;
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uint32_t id_mmfr0;
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uint32_t id_mmfr1;
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uint32_t id_mmfr2;
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uint32_t id_mmfr3;
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uint32_t id_mmfr4;
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uint32_t mvfr0;
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uint32_t mvfr1;
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uint32_t mvfr2;
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@ -892,11 +897,6 @@ struct ARMCPU {
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uint64_t pmceid0;
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uint64_t pmceid1;
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uint32_t id_afr0;
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uint32_t id_mmfr0;
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uint32_t id_mmfr1;
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uint32_t id_mmfr2;
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uint32_t id_mmfr3;
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uint32_t id_mmfr4;
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uint64_t id_aa64afr0;
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uint64_t id_aa64afr1;
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uint32_t clidr;
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@ -3504,12 +3504,12 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
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static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0;
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return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
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}
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static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
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return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
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}
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static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
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@ -123,10 +123,10 @@ static void aarch64_a57_initfn(Object *obj)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10101105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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@ -177,10 +177,10 @@ static void aarch64_a53_initfn(Object *obj)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10101105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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@ -230,10 +230,10 @@ static void aarch64_a72_initfn(Object *obj)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10201105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10201105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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@ -699,9 +699,9 @@ static void aarch64_max_initfn(Object *obj)
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u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
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cpu->isar.id_isar6 = u;
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u = cpu->id_mmfr3;
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u = cpu->isar.id_mmfr3;
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u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
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cpu->id_mmfr3 = u;
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cpu->isar.id_mmfr3 = u;
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u = cpu->isar.id_aa64dfr0;
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u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
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@ -6910,22 +6910,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_mmfr0 },
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.resetvalue = cpu->isar.id_mmfr0 },
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{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.accessfn = access_aa32_tid3,
|
||||
.resetvalue = cpu->id_mmfr1 },
|
||||
.resetvalue = cpu->isar.id_mmfr1 },
|
||||
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.accessfn = access_aa32_tid3,
|
||||
.resetvalue = cpu->id_mmfr2 },
|
||||
.resetvalue = cpu->isar.id_mmfr2 },
|
||||
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.accessfn = access_aa32_tid3,
|
||||
.resetvalue = cpu->id_mmfr3 },
|
||||
.resetvalue = cpu->isar.id_mmfr3 },
|
||||
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
@ -6960,7 +6960,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.accessfn = access_aa32_tid3,
|
||||
.resetvalue = cpu->id_mmfr4 },
|
||||
.resetvalue = cpu->isar.id_mmfr4 },
|
||||
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
@ -7409,7 +7409,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
||||
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
|
||||
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
|
||||
/* TTCBR2 is introduced with ARMv8.2-A32HPD. */
|
||||
if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) != 0) {
|
||||
if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) != 0) {
|
||||
define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
|
||||
}
|
||||
}
|
||||
|
||||
@ -111,6 +111,23 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
|
||||
* Fortunately there is not yet anything in there that affects migration.
|
||||
*/
|
||||
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
|
||||
ARM_CP15_REG32(0, 0, 1, 4));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
|
||||
ARM_CP15_REG32(0, 0, 1, 5));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
|
||||
ARM_CP15_REG32(0, 0, 1, 6));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
|
||||
ARM_CP15_REG32(0, 0, 1, 7));
|
||||
if (read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
|
||||
ARM_CP15_REG32(0, 0, 2, 6))) {
|
||||
/*
|
||||
* Older kernels don't support reading ID_MMFR4 (a new in v8
|
||||
* register); assume it's zero.
|
||||
*/
|
||||
ahcf->isar.id_mmfr4 = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* There is no way to read DBGDIDR, because currently 32-bit KVM
|
||||
* doesn't implement debug at all. Leave it at zero.
|
||||
|
||||
@ -565,6 +565,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
|
||||
*/
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
|
||||
ARM64_SYS_REG(3, 0, 0, 1, 2));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
|
||||
ARM64_SYS_REG(3, 0, 0, 1, 4));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
|
||||
ARM64_SYS_REG(3, 0, 0, 1, 5));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
|
||||
ARM64_SYS_REG(3, 0, 0, 1, 6));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
|
||||
ARM64_SYS_REG(3, 0, 0, 1, 7));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
|
||||
ARM64_SYS_REG(3, 0, 0, 2, 0));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
|
||||
@ -577,6 +585,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
|
||||
ARM64_SYS_REG(3, 0, 0, 2, 4));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
|
||||
ARM64_SYS_REG(3, 0, 0, 2, 5));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
|
||||
ARM64_SYS_REG(3, 0, 0, 2, 6));
|
||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
|
||||
ARM64_SYS_REG(3, 0, 0, 2, 7));
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user