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ARM: Remove unnecessary subpage workarounds

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In the ARM per-CPU peripherals (GIC, private timers, SCU, etc),
remove workarounds for subpage memory region read/write functions
being passed offsets from the start of the page rather than the
start of the region. Following commit 5312bd8b3 the masking off
of high bits of the address offset is now harmless but unnecessary.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Peter Maydell 2012-03-14 15:37:53 +00:00
parent 54e17933bf
commit 0e4a398ab2
3 changed files with 4 additions and 8 deletions
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2
hw/arm11mpcore.c
View File

@ -42,7 +42,6 @@ static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
{ {
mpcore_priv_state *s = (mpcore_priv_state *)opaque; mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id; int id;
offset &= 0xff;
/* SCU */ /* SCU */
switch (offset) { switch (offset) {
case 0x00: /* Control. */ case 0x00: /* Control. */
@ -63,7 +62,6 @@ static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
uint64_t value, unsigned size) uint64_t value, unsigned size)
{ {
mpcore_priv_state *s = (mpcore_priv_state *)opaque; mpcore_priv_state *s = (mpcore_priv_state *)opaque;
offset &= 0xff;
/* SCU */ /* SCU */
switch (offset) { switch (offset) {
case 0: /* Control register. */ case 0: /* Control register. */

8
hw/arm_gic.c
View File

@ -658,14 +658,14 @@ static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
unsigned size) unsigned size)
{ {
gic_state *s = (gic_state *)opaque; gic_state *s = (gic_state *)opaque;
return gic_cpu_read(s, gic_get_current_cpu(), addr & 0xff); return gic_cpu_read(s, gic_get_current_cpu(), addr);
} }
static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr, static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size) uint64_t value, unsigned size)
{ {
gic_state *s = (gic_state *)opaque; gic_state *s = (gic_state *)opaque;
gic_cpu_write(s, gic_get_current_cpu(), addr & 0xff, value); gic_cpu_write(s, gic_get_current_cpu(), addr, value);
} }
/* Wrappers to read/write the GIC CPU interface for a specific CPU. /* Wrappers to read/write the GIC CPU interface for a specific CPU.
@ -677,7 +677,7 @@ static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
gic_state **backref = (gic_state **)opaque; gic_state **backref = (gic_state **)opaque;
gic_state *s = *backref; gic_state *s = *backref;
int id = (backref - s->backref); int id = (backref - s->backref);
return gic_cpu_read(s, id, addr & 0xff); return gic_cpu_read(s, id, addr);
} }
static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
@ -686,7 +686,7 @@ static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
gic_state **backref = (gic_state **)opaque; gic_state **backref = (gic_state **)opaque;
gic_state *s = *backref; gic_state *s = *backref;
int id = (backref - s->backref); int id = (backref - s->backref);
gic_cpu_write(s, id, addr & 0xff, value); gic_cpu_write(s, id, addr, value);
} }
static const MemoryRegionOps gic_thiscpu_ops = { static const MemoryRegionOps gic_thiscpu_ops = {

2
hw/arm_mptimer.c
View File

@ -97,7 +97,6 @@ static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr,
{ {
timerblock *tb = (timerblock *)opaque; timerblock *tb = (timerblock *)opaque;
int64_t val; int64_t val;
addr &= 0x1f;
switch (addr) { switch (addr) {
case 0: /* Load */ case 0: /* Load */
return tb->load; return tb->load;
@ -126,7 +125,6 @@ static void timerblock_write(void *opaque, target_phys_addr_t addr,
{ {
timerblock *tb = (timerblock *)opaque; timerblock *tb = (timerblock *)opaque;
int64_t old; int64_t old;
addr &= 0x1f;
switch (addr) { switch (addr) {
case 0: /* Load */ case 0: /* Load */
tb->load = value; tb->load = value;