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tcg-s390: Use load-address for addition
Since we're always in 64-bit mode, load address performs a full 64-bit add. Use that for 3-address addition, as well as for larger constant addends when we lack extended-immediates facility. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
65a62a753c
commit
0db921e6d8
@ -35,8 +35,6 @@
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#define USE_LONG_BRANCHES 0
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#define TCG_CT_CONST_32 0x0100
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#define TCG_CT_CONST_NEG 0x0200
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#define TCG_CT_CONST_ADDI 0x0400
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#define TCG_CT_CONST_MULI 0x0800
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#define TCG_CT_CONST_ORI 0x2000
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#define TCG_CT_CONST_XORI 0x4000
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@ -90,6 +88,7 @@ typedef enum S390Opcode {
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RIL_OIHF = 0xc00c,
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RIL_OILF = 0xc00d,
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RIL_SLFI = 0xc205,
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RIL_SLGFI = 0xc204,
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RIL_XIHF = 0xc006,
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RIL_XILF = 0xc007,
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@ -191,6 +190,7 @@ typedef enum S390Opcode {
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RXY_AY = 0xe35a,
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RXY_CG = 0xe320,
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RXY_CY = 0xe359,
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RXY_LAY = 0xe371,
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RXY_LB = 0xe376,
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RXY_LG = 0xe304,
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RXY_LGB = 0xe377,
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@ -217,6 +217,7 @@ typedef enum S390Opcode {
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RX_A = 0x5a,
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RX_C = 0x59,
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RX_L = 0x58,
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RX_LA = 0x41,
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RX_LH = 0x48,
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RX_ST = 0x50,
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RX_STC = 0x42,
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@ -405,15 +406,9 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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tcg_regset_clear(ct->u.regs);
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tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
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break;
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case 'N': /* force immediate negate */
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ct->ct |= TCG_CT_CONST_NEG;
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break;
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case 'W': /* force 32-bit ("word") immediate */
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ct->ct |= TCG_CT_CONST_32;
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break;
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case 'I':
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ct->ct |= TCG_CT_CONST_ADDI;
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break;
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case 'K':
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ct->ct |= TCG_CT_CONST_MULI;
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break;
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@ -529,25 +524,12 @@ static int tcg_target_const_match(tcg_target_long val,
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}
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/* Handle the modifiers. */
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if (ct & TCG_CT_CONST_NEG) {
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val = -val;
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}
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if (ct & TCG_CT_CONST_32) {
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val = (int32_t)val;
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}
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/* The following are mutually exclusive. */
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if (ct & TCG_CT_CONST_ADDI) {
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/* Immediates that may be used with add. If we have the
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extended-immediates facility then we have ADD IMMEDIATE
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with signed and unsigned 32-bit, otherwise we have only
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ADD HALFWORD IMMEDIATE with a signed 16-bit. */
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if (facilities & FACILITY_EXT_IMM) {
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return val == (int32_t)val || val == (uint32_t)val;
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} else {
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return val == (int16_t)val;
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}
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} else if (ct & TCG_CT_CONST_MULI) {
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if (ct & TCG_CT_CONST_MULI) {
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/* Immediates that may be used with multiply. If we have the
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general-instruction-extensions, then we have MULTIPLY SINGLE
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IMMEDIATE with a signed 32-bit, otherwise we have only
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@ -927,29 +909,6 @@ static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
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tcg_out_insn(s, RRE, LLGFR, dest, src);
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}
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static inline void tgen32_addi(TCGContext *s, TCGReg dest, int32_t val)
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{
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if (val == (int16_t)val) {
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tcg_out_insn(s, RI, AHI, dest, val);
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} else {
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tcg_out_insn(s, RIL, AFI, dest, val);
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}
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}
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static inline void tgen64_addi(TCGContext *s, TCGReg dest, int64_t val)
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{
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if (val == (int16_t)val) {
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tcg_out_insn(s, RI, AGHI, dest, val);
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} else if (val == (int32_t)val) {
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tcg_out_insn(s, RIL, AGFI, dest, val);
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} else if (val == (uint32_t)val) {
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tcg_out_insn(s, RIL, ALGFI, dest, val);
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} else {
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tcg_abort();
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}
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}
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/* Accept bit patterns like these:
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0....01....1
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1....10....0
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@ -1640,6 +1599,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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const TCGArg *args, const int *const_args)
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{
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S390Opcode op;
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TCGArg a0, a1, a2;
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switch (opc) {
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case INDEX_op_exit_tb:
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@ -1715,18 +1675,33 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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break;
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case INDEX_op_add_i32:
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a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
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if (const_args[2]) {
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tgen32_addi(s, args[0], args[2]);
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do_addi_32:
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if (a0 == a1) {
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if (a2 == (int16_t)a2) {
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tcg_out_insn(s, RI, AHI, a0, a2);
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break;
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}
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if (facilities & FACILITY_EXT_IMM) {
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tcg_out_insn(s, RIL, AFI, a0, a2);
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break;
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}
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}
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tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
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} else if (a0 == a1) {
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tcg_out_insn(s, RR, AR, a0, a2);
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} else {
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tcg_out_insn(s, RR, AR, args[0], args[2]);
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tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
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}
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break;
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case INDEX_op_sub_i32:
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a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
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if (const_args[2]) {
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tgen32_addi(s, args[0], -args[2]);
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} else {
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tcg_out_insn(s, RR, SR, args[0], args[2]);
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a2 = -a2;
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goto do_addi_32;
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}
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tcg_out_insn(s, RR, SR, args[0], args[2]);
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break;
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case INDEX_op_and_i32:
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@ -1920,15 +1895,39 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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break;
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case INDEX_op_add_i64:
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a0 = args[0], a1 = args[1], a2 = args[2];
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if (const_args[2]) {
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tgen64_addi(s, args[0], args[2]);
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do_addi_64:
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if (a0 == a1) {
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if (a2 == (int16_t)a2) {
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tcg_out_insn(s, RI, AGHI, a0, a2);
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break;
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}
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if (facilities & FACILITY_EXT_IMM) {
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if (a2 == (int32_t)a2) {
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tcg_out_insn(s, RIL, AGFI, a0, a2);
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break;
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} else if (a2 == (uint32_t)a2) {
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tcg_out_insn(s, RIL, ALGFI, a0, a2);
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break;
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} else if (-a2 == (uint32_t)-a2) {
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tcg_out_insn(s, RIL, SLGFI, a0, -a2);
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break;
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}
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}
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}
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tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
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} else if (a0 == a1) {
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tcg_out_insn(s, RRE, AGR, a0, a2);
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} else {
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tcg_out_insn(s, RRE, AGR, args[0], args[2]);
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tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
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}
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break;
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case INDEX_op_sub_i64:
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a0 = args[0], a1 = args[1], a2 = args[2];
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if (const_args[2]) {
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tgen64_addi(s, args[0], -args[2]);
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a2 = -a2;
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goto do_addi_64;
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} else {
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tcg_out_insn(s, RRE, SGR, args[0], args[2]);
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}
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@ -2103,8 +2102,8 @@ static const TCGTargetOpDef s390_op_defs[] = {
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{ INDEX_op_st16_i32, { "r", "r" } },
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{ INDEX_op_st_i32, { "r", "r" } },
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{ INDEX_op_add_i32, { "r", "0", "rWI" } },
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{ INDEX_op_sub_i32, { "r", "0", "rWNI" } },
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{ INDEX_op_add_i32, { "r", "r", "ri" } },
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{ INDEX_op_sub_i32, { "r", "0", "ri" } },
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{ INDEX_op_mul_i32, { "r", "0", "rK" } },
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{ INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } },
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@ -2167,8 +2166,8 @@ static const TCGTargetOpDef s390_op_defs[] = {
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{ INDEX_op_st32_i64, { "r", "r" } },
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{ INDEX_op_st_i64, { "r", "r" } },
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{ INDEX_op_add_i64, { "r", "0", "rI" } },
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{ INDEX_op_sub_i64, { "r", "0", "rNI" } },
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{ INDEX_op_add_i64, { "r", "r", "ri" } },
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{ INDEX_op_sub_i64, { "r", "0", "ri" } },
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{ INDEX_op_mul_i64, { "r", "0", "rK" } },
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{ INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } },
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