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target/openrisc: Put SR[OVE] in TB flags

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Removes a call at execution time for overflow exceptions.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2015-02-18 12:34:56 -08:00
parent 9ecaa27e71
commit 0c53d7342b
3 changed files with 18 additions and 12 deletions
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4
target/openrisc/cpu.h
View File

@ -400,8 +400,8 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
{
*pc = env->pc;
*cs_base = 0;
/* D_FLAG -- branch instruction exception */
*flags = (env->flags & D_FLAG);
/* D_FLAG -- branch instruction exception, OVE overflow trap enable. */
*flags = (env->flags & D_FLAG) | (env->sr & SR_OVE);
}
static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)

2
target/openrisc/exception_helper.c
View File

@ -32,7 +32,7 @@ void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp)
void HELPER(ove)(CPUOpenRISCState *env, target_ulong test)
{
if (unlikely(test) && (env->sr & SR_OVE)) {
if (unlikely(test)) {
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);

24
target/openrisc/translate.c
View File

@ -132,8 +132,8 @@ static inline void wb_SR_F(void)
static inline void gen_sync_flags(DisasContext *dc)
{
/* Sync the tb dependent flag between translate and runtime. */
if (dc->tb_flags != dc->synced_flags) {
tcg_gen_movi_tl(env_flags, dc->tb_flags);
if ((dc->tb_flags ^ dc->synced_flags) & D_FLAG) {
tcg_gen_movi_tl(env_flags, dc->tb_flags & D_FLAG);
dc->synced_flags = dc->tb_flags;
}
}
@ -249,20 +249,26 @@ static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0)
static void gen_ove_cy(DisasContext *dc, TCGv cy)
{
gen_helper_ove(cpu_env, cy);
if (dc->tb_flags & SR_OVE) {
gen_helper_ove(cpu_env, cy);
}
}
static void gen_ove_ov(DisasContext *dc, TCGv ov)
{
gen_helper_ove(cpu_env, ov);
if (dc->tb_flags & SR_OVE) {
gen_helper_ove(cpu_env, ov);
}
}
static void gen_ove_cyov(DisasContext *dc, TCGv cy, TCGv ov)
{
TCGv t0 = tcg_temp_new();
tcg_gen_or_tl(t0, cy, ov);
gen_helper_ove(cpu_env, t0);
tcg_temp_free(t0);
if (dc->tb_flags & SR_OVE) {
TCGv t0 = tcg_temp_new();
tcg_gen_or_tl(t0, cy, ov);
gen_helper_ove(cpu_env, t0);
tcg_temp_free(t0);
}
}
static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
@ -1606,7 +1612,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
dc->flags = cpu->env.cpucfgr;
dc->mem_idx = cpu_mmu_index(&cpu->env, false);
dc->synced_flags = dc->tb_flags = tb->flags;
dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
dc->delayed_branch = (dc->tb_flags & D_FLAG) != 0;
dc->singlestep_enabled = cs->singlestep_enabled;
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;