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Merge remote-tracking branch 'remotes/mcayland/qemu-sparc' into staging

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* remotes/mcayland/qemu-sparc:
  target-sparc64: implement Short Floating-Point Store Instructions
  apb: add IOMMU flush register implementation
  sun4u: switch second PCI-ebus bridge BAR over to PCI IO space

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2014-08-18 12:55:02 +01:00
commit 08ab59770d
3 changed files with 26 additions and 5 deletions
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12
hw/pci-host/apb.c
View File

@ -94,6 +94,7 @@ do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
#define IOMMU_CTRL_TSB_SHIFT 16
#define IOMMU_BASE 0x8
#define IOMMU_FLUSH 0x10
#define IOMMU_TTE_DATA_V (1ULL << 63)
#define IOMMU_TTE_DATA_SIZE (1ULL << 61)
@ -352,6 +353,9 @@ static void iommu_config_write(void *opaque, hwaddr addr,
is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;
break;
case IOMMU_FLUSH:
case IOMMU_FLUSH + 0x4:
break;
default:
qemu_log_mask(LOG_UNIMP,
"apb iommu: Unimplemented register write "
@ -387,6 +391,10 @@ static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size)
case IOMMU_BASE + 0x4:
val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
break;
case IOMMU_FLUSH:
case IOMMU_FLUSH + 0x4:
val = 0;
break;
default:
qemu_log_mask(LOG_UNIMP,
"apb iommu: Unimplemented register read "
@ -415,7 +423,7 @@ static void apb_config_writel (void *opaque, hwaddr addr,
/* XXX: not implemented yet */
break;
case 0x200 ... 0x217: /* IOMMU */
iommu_config_write(is, (addr & 0xf), val, size);
iommu_config_write(is, (addr & 0x1f), val, size);
break;
case 0xc00 ... 0xc3f: /* PCI interrupt control */
if (addr & 4) {
@ -497,7 +505,7 @@ static uint64_t apb_config_readl (void *opaque,
/* XXX: not implemented yet */
break;
case 0x200 ... 0x217: /* IOMMU */
val = iommu_config_read(is, (addr & 0xf), size);
val = iommu_config_read(is, (addr & 0x1f), size);
break;
case 0xc00 ... 0xc3f: /* PCI interrupt control */
if (addr & 4) {

4
hw/sparc64/sun4u.c
View File

@ -609,8 +609,8 @@ pci_ebus_init1(PCIDevice *pci_dev)
0, 0x1000000);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
0, 0x800000);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
0, 0x1000);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
return 0;
}

15
target-sparc/ldst_helper.c
View File

@ -2154,7 +2154,6 @@ void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
unsigned int i;
target_ulong val;
helper_check_align(env, addr, 3);
addr = asi_address_mask(env, asi, addr);
switch (asi) {
@ -2191,8 +2190,22 @@ void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
}
return;
case 0xd2: /* 16-bit floating point load primary */
case 0xd3: /* 16-bit floating point load secondary */
case 0xda: /* 16-bit floating point load primary, LE */
case 0xdb: /* 16-bit floating point load secondary, LE */
helper_check_align(env, addr, 1);
/* Fall through */
case 0xd0: /* 8-bit floating point load primary */
case 0xd1: /* 8-bit floating point load secondary */
case 0xd8: /* 8-bit floating point load primary, LE */
case 0xd9: /* 8-bit floating point load secondary, LE */
val = env->fpr[rd / 2].l.lower;
helper_st_asi(env, addr, val, asi & 0x8d, ((asi & 2) >> 1) + 1);
return;
default:
helper_check_align(env, addr, 3);
break;
}