mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-11-26 12:23:36 +08:00
Code Issues Packages Projects Releases Wiki Activity

target-alpha: Convert opcode 0x14 to source/sink

Browse Source 
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2014-03-18 23:50:56 -07:00
parent de4d3555fa
commit 075b8ddb9b
1 changed files with 18 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
target-alpha/translate.c
View File

@ -206,7 +206,7 @@ static TCGv __attribute__((unused)) load_fpr(DisasContext *ctx, unsigned reg)
} }
} }
static TCGv __attribute__((unused)) dest_fpr(DisasContext *ctx, unsigned reg) static TCGv dest_fpr(DisasContext *ctx, unsigned reg)
{ {
if (likely(reg < 31)) { if (likely(reg < 31)) {
return cpu_fir[reg]; return cpu_fir[reg];
@ -1861,6 +1861,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
uint8_t opc, ra, rb, rc, fpfn, fn7, lit; uint8_t opc, ra, rb, rc, fpfn, fn7, lit;
bool islit; bool islit;
TCGv va, vb, vc, tmp; TCGv va, vb, vc, tmp;
TCGv_i32 t32;
ExitStatus ret; ExitStatus ret;
/* Decode all instruction fields */ /* Decode all instruction fields */
@ -2373,21 +2374,19 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc; goto invalid_opc;
} }
break; break;
case 0x14: case 0x14:
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);
switch (fpfn) { /* fn11 & 0x3F */ switch (fpfn) { /* fn11 & 0x3F */
case 0x04: case 0x04:
/* ITOFS */ /* ITOFS */
REQUIRE_REG_31(rb); REQUIRE_REG_31(rb);
if (likely(rc != 31)) { t32 = tcg_temp_new_i32();
if (ra != 31) { va = load_gpr(ctx, ra);
TCGv_i32 tmp = tcg_temp_new_i32(); vc = dest_fpr(ctx, rc);
tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); tcg_gen_trunc_i64_i32(t32, va);
gen_helper_memory_to_s(cpu_fir[rc], tmp); gen_helper_memory_to_s(vc, t32);
tcg_temp_free_i32(tmp); tcg_temp_free_i32(t32);
} else
tcg_gen_movi_i64(cpu_fir[rc], 0);
}
break; break;
case 0x0A: case 0x0A:
/* SQRTF */ /* SQRTF */
@ -2402,26 +2401,19 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
case 0x14: case 0x14:
/* ITOFF */ /* ITOFF */
REQUIRE_REG_31(rb); REQUIRE_REG_31(rb);
if (likely(rc != 31)) { t32 = tcg_temp_new_i32();
if (ra != 31) { va = load_gpr(ctx, ra);
TCGv_i32 tmp = tcg_temp_new_i32(); vc = dest_fpr(ctx, rc);
tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); tcg_gen_trunc_i64_i32(t32, va);
gen_helper_memory_to_f(cpu_fir[rc], tmp); gen_helper_memory_to_f(vc, t32);
tcg_temp_free_i32(tmp); tcg_temp_free_i32(t32);
} else
tcg_gen_movi_i64(cpu_fir[rc], 0);
}
break; break;
case 0x24: case 0x24:
/* ITOFT */ /* ITOFT */
REQUIRE_REG_31(rb); REQUIRE_REG_31(rb);
if (likely(rc != 31)) { va = load_gpr(ctx, ra);
if (ra != 31) { vc = dest_fpr(ctx, rc);
tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]); tcg_gen_mov_i64(vc, va);
} else {
tcg_gen_movi_i64(cpu_fir[rc], 0);
}
}
break; break;
case 0x2A: case 0x2A:
/* SQRTG */ /* SQRTG */