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pxa2xx_dma: convert to memory API

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Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity 2011-11-14 11:55:27 +02:00
parent 838335ecf3
commit 00049a1221
1 changed files with 24 additions and 30 deletions
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54
hw/pxa2xx_dma.c
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@ -28,6 +28,7 @@ typedef struct {
typedef struct PXA2xxDMAState {
SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq irq;
uint32_t stopintr;
@ -250,11 +251,17 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s)
}
}
static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset)
static uint64_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
unsigned int channel;
if (size != 4) {
hw_error("%s: Bad access width\n", __FUNCTION__);
return 5;
}
switch (offset) {
case DRCMR64 ... DRCMR74:
offset -= DRCMR64 - DRCMR0 - (64 << 2);
@ -303,12 +310,17 @@ static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset)
return 7;
}
static void pxa2xx_dma_write(void *opaque,
target_phys_addr_t offset, uint32_t value)
static void pxa2xx_dma_write(void *opaque, target_phys_addr_t offset,
uint64_t value, unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
unsigned int channel;
if (size != 4) {
hw_error("%s: Bad access width\n", __FUNCTION__);
return;
}
switch (offset) {
case DRCMR64 ... DRCMR74:
offset -= DRCMR64 - DRCMR0 - (64 << 2);
@ -319,7 +331,7 @@ static void pxa2xx_dma_write(void *opaque,
if (value & DRCMR_MAPVLD)
if ((value & DRCMR_CHLNUM) > s->channels)
hw_error("%s: Bad DMA channel %i\n",
__FUNCTION__, value & DRCMR_CHLNUM);
__FUNCTION__, (unsigned)value & DRCMR_CHLNUM);
s->req[channel] = value;
break;
@ -402,28 +414,10 @@ static void pxa2xx_dma_write(void *opaque,
}
}
static uint32_t pxa2xx_dma_readbad(void *opaque, target_phys_addr_t offset)
{
hw_error("%s: Bad access width\n", __FUNCTION__);
return 5;
}
static void pxa2xx_dma_writebad(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
hw_error("%s: Bad access width\n", __FUNCTION__);
}
static CPUReadMemoryFunc * const pxa2xx_dma_readfn[] = {
pxa2xx_dma_readbad,
pxa2xx_dma_readbad,
pxa2xx_dma_read
};
static CPUWriteMemoryFunc * const pxa2xx_dma_writefn[] = {
pxa2xx_dma_writebad,
pxa2xx_dma_writebad,
pxa2xx_dma_write
static const MemoryRegionOps pxa2xx_dma_ops = {
.read = pxa2xx_dma_read,
.write = pxa2xx_dma_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void pxa2xx_dma_request(void *opaque, int req_num, int on)
@ -453,7 +447,7 @@ static void pxa2xx_dma_request(void *opaque, int req_num, int on)
static int pxa2xx_dma_init(SysBusDevice *dev)
{
int i, iomemtype;
int i;
PXA2xxDMAState *s;
s = FROM_SYSBUS(PXA2xxDMAState, dev);
@ -471,9 +465,9 @@ static int pxa2xx_dma_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
iomemtype = cpu_register_io_memory(pxa2xx_dma_readfn,
pxa2xx_dma_writefn, s, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x00010000, iomemtype);
memory_region_init_io(&s->iomem, &pxa2xx_dma_ops, s,
"pxa2xx.dma", 0x00010000);
sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
return 0;