2007-09-17 05:08:06 +08:00
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/*
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2007-06-03 19:13:39 +08:00
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* ColdFire UART emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This code is licenced under the GPL
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*/
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2007-11-18 01:14:51 +08:00
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#include "hw.h"
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#include "mcf.h"
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#include "qemu-char.h"
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2007-06-03 19:13:39 +08:00
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typedef struct {
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uint8_t mr[2];
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uint8_t sr;
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uint8_t isr;
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uint8_t imr;
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uint8_t bg1;
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uint8_t bg2;
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uint8_t fifo[4];
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uint8_t tb;
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int current_mr;
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int fifo_len;
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int tx_enabled;
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int rx_enabled;
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qemu_irq irq;
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CharDriverState *chr;
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} mcf_uart_state;
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/* UART Status Register bits. */
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#define MCF_UART_RxRDY 0x01
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#define MCF_UART_FFULL 0x02
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#define MCF_UART_TxRDY 0x04
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#define MCF_UART_TxEMP 0x08
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#define MCF_UART_OE 0x10
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#define MCF_UART_PE 0x20
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#define MCF_UART_FE 0x40
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#define MCF_UART_RB 0x80
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/* Interrupt flags. */
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#define MCF_UART_TxINT 0x01
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#define MCF_UART_RxINT 0x02
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#define MCF_UART_DBINT 0x04
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#define MCF_UART_COSINT 0x80
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/* UMR1 flags. */
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#define MCF_UART_BC0 0x01
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#define MCF_UART_BC1 0x02
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#define MCF_UART_PT 0x04
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#define MCF_UART_PM0 0x08
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#define MCF_UART_PM1 0x10
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#define MCF_UART_ERR 0x20
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#define MCF_UART_RxIRQ 0x40
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#define MCF_UART_RxRTS 0x80
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static void mcf_uart_update(mcf_uart_state *s)
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{
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s->isr &= ~(MCF_UART_TxINT | MCF_UART_RxINT);
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if (s->sr & MCF_UART_TxRDY)
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s->isr |= MCF_UART_TxINT;
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if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ)
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? MCF_UART_FFULL : MCF_UART_RxRDY)) != 0)
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s->isr |= MCF_UART_RxINT;
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qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
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}
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2009-10-02 05:12:16 +08:00
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uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
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2007-06-03 19:13:39 +08:00
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{
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mcf_uart_state *s = (mcf_uart_state *)opaque;
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switch (addr & 0x3f) {
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case 0x00:
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return s->mr[s->current_mr];
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case 0x04:
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return s->sr;
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case 0x0c:
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{
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uint8_t val;
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int i;
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if (s->fifo_len == 0)
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return 0;
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val = s->fifo[0];
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s->fifo_len--;
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for (i = 0; i < s->fifo_len; i++)
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s->fifo[i] = s->fifo[i + 1];
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s->sr &= ~MCF_UART_FFULL;
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if (s->fifo_len == 0)
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s->sr &= ~MCF_UART_RxRDY;
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mcf_uart_update(s);
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2007-11-25 08:55:06 +08:00
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qemu_chr_accept_input(s->chr);
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2007-06-03 19:13:39 +08:00
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return val;
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}
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case 0x10:
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/* TODO: Implement IPCR. */
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return 0;
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case 0x14:
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return s->isr;
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case 0x18:
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return s->bg1;
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case 0x1c:
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return s->bg2;
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default:
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return 0;
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}
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}
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/* Update TxRDY flag and set data if present and enabled. */
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static void mcf_uart_do_tx(mcf_uart_state *s)
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{
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if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
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if (s->chr)
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qemu_chr_write(s->chr, (unsigned char *)&s->tb, 1);
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s->sr |= MCF_UART_TxEMP;
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}
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if (s->tx_enabled) {
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s->sr |= MCF_UART_TxRDY;
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} else {
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s->sr &= ~MCF_UART_TxRDY;
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}
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}
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static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
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{
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/* Misc command. */
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switch ((cmd >> 4) & 3) {
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case 0: /* No-op. */
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break;
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case 1: /* Reset mode register pointer. */
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s->current_mr = 0;
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break;
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case 2: /* Reset receiver. */
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s->rx_enabled = 0;
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s->fifo_len = 0;
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s->sr &= ~(MCF_UART_RxRDY | MCF_UART_FFULL);
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break;
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case 3: /* Reset transmitter. */
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s->tx_enabled = 0;
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s->sr |= MCF_UART_TxEMP;
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s->sr &= ~MCF_UART_TxRDY;
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break;
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case 4: /* Reset error status. */
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break;
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case 5: /* Reset break-change interrupt. */
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s->isr &= ~MCF_UART_DBINT;
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break;
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case 6: /* Start break. */
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case 7: /* Stop break. */
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break;
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}
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/* Transmitter command. */
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switch ((cmd >> 2) & 3) {
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case 0: /* No-op. */
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break;
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case 1: /* Enable. */
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s->tx_enabled = 1;
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mcf_uart_do_tx(s);
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break;
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case 2: /* Disable. */
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s->tx_enabled = 0;
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mcf_uart_do_tx(s);
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break;
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case 3: /* Reserved. */
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fprintf(stderr, "mcf_uart: Bad TX command\n");
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break;
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}
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/* Receiver command. */
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switch (cmd & 3) {
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case 0: /* No-op. */
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break;
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case 1: /* Enable. */
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s->rx_enabled = 1;
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break;
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case 2:
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s->rx_enabled = 0;
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break;
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case 3: /* Reserved. */
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fprintf(stderr, "mcf_uart: Bad RX command\n");
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break;
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}
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}
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2009-10-02 05:12:16 +08:00
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void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val)
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2007-06-03 19:13:39 +08:00
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{
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mcf_uart_state *s = (mcf_uart_state *)opaque;
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switch (addr & 0x3f) {
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case 0x00:
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s->mr[s->current_mr] = val;
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s->current_mr = 1;
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break;
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case 0x04:
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/* CSR is ignored. */
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break;
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case 0x08: /* Command Register. */
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mcf_do_command(s, val);
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break;
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case 0x0c: /* Transmit Buffer. */
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s->sr &= ~MCF_UART_TxEMP;
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s->tb = val;
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mcf_uart_do_tx(s);
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break;
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case 0x10:
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/* ACR is ignored. */
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break;
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case 0x14:
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s->imr = val;
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break;
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default:
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break;
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}
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mcf_uart_update(s);
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}
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static void mcf_uart_reset(mcf_uart_state *s)
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{
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s->fifo_len = 0;
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s->mr[0] = 0;
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s->mr[1] = 0;
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s->sr = MCF_UART_TxEMP;
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s->tx_enabled = 0;
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s->rx_enabled = 0;
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s->isr = 0;
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s->imr = 0;
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}
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static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data)
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{
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/* Break events overwrite the last byte if the fifo is full. */
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if (s->fifo_len == 4)
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s->fifo_len--;
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s->fifo[s->fifo_len] = data;
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s->fifo_len++;
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s->sr |= MCF_UART_RxRDY;
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if (s->fifo_len == 4)
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s->sr |= MCF_UART_FFULL;
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mcf_uart_update(s);
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}
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static void mcf_uart_event(void *opaque, int event)
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{
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mcf_uart_state *s = (mcf_uart_state *)opaque;
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switch (event) {
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case CHR_EVENT_BREAK:
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s->isr |= MCF_UART_DBINT;
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mcf_uart_push_byte(s, 0);
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break;
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default:
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break;
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}
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}
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static int mcf_uart_can_receive(void *opaque)
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{
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mcf_uart_state *s = (mcf_uart_state *)opaque;
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return s->rx_enabled && (s->sr & MCF_UART_FFULL) == 0;
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}
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static void mcf_uart_receive(void *opaque, const uint8_t *buf, int size)
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{
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mcf_uart_state *s = (mcf_uart_state *)opaque;
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mcf_uart_push_byte(s, buf[0]);
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}
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void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
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{
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mcf_uart_state *s;
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s = qemu_mallocz(sizeof(mcf_uart_state));
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s->chr = chr;
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s->irq = irq;
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if (chr) {
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qemu_chr_add_handlers(chr, mcf_uart_can_receive, mcf_uart_receive,
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mcf_uart_event, s);
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}
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mcf_uart_reset(s);
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return s;
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}
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2009-08-26 02:29:31 +08:00
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static CPUReadMemoryFunc * const mcf_uart_readfn[] = {
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2007-06-03 19:13:39 +08:00
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mcf_uart_read,
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mcf_uart_read,
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mcf_uart_read
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};
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2009-08-26 02:29:31 +08:00
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static CPUWriteMemoryFunc * const mcf_uart_writefn[] = {
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2007-06-03 19:13:39 +08:00
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mcf_uart_write,
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mcf_uart_write,
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mcf_uart_write
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};
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2009-10-02 05:12:16 +08:00
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void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
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2007-06-03 19:13:39 +08:00
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CharDriverState *chr)
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{
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mcf_uart_state *s;
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int iomemtype;
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s = mcf_uart_init(irq, chr);
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2009-06-14 16:38:51 +08:00
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iomemtype = cpu_register_io_memory(mcf_uart_readfn,
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2010-12-08 19:05:37 +08:00
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mcf_uart_writefn, s,
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DEVICE_NATIVE_ENDIAN);
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2007-06-03 19:13:39 +08:00
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cpu_register_physical_memory(base, 0x40, iomemtype);
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}
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