2012-02-12 00:26:17 +08:00
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/*
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* QEMU SuperH CPU
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*
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2012-04-13 08:16:02 +08:00
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* Copyright (c) 2005 Samuel Tardieu
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2012-02-12 00:26:17 +08:00
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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2013-01-21 02:32:33 +08:00
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#include "migration/vmstate.h"
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2012-02-12 00:26:17 +08:00
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2013-06-22 01:09:18 +08:00
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static void superh_cpu_set_pc(CPUState *cs, vaddr value)
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{
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SuperHCPU *cpu = SUPERH_CPU(cs);
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cpu->env.pc = value;
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}
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2013-06-29 01:31:32 +08:00
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static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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SuperHCPU *cpu = SUPERH_CPU(cs);
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cpu->env.pc = tb->pc;
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cpu->env.flags = tb->flags;
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}
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2013-08-26 00:53:55 +08:00
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static bool superh_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & CPU_INTERRUPT_HARD;
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}
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2012-02-12 00:26:17 +08:00
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/* CPUClass::reset() */
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static void superh_cpu_reset(CPUState *s)
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{
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SuperHCPU *cpu = SUPERH_CPU(s);
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SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
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CPUSH4State *env = &cpu->env;
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scc->parent_reset(s);
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2013-08-27 03:22:53 +08:00
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memset(env, 0, offsetof(CPUSH4State, id));
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2013-09-04 08:19:44 +08:00
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tlb_flush(s, 1);
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2012-04-13 08:16:02 +08:00
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env->pc = 0xA0000000;
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#if defined(CONFIG_USER_ONLY)
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env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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#else
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2015-05-25 07:28:56 +08:00
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env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
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(1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
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2012-04-13 08:16:02 +08:00
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env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
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set_float_rounding_mode(float_round_to_zero, &env->fp_status);
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set_flush_to_zero(1, &env->fp_status);
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#endif
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set_default_nan_mode(1, &env->fp_status);
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2012-02-12 00:26:17 +08:00
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}
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2012-11-19 09:42:18 +08:00
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typedef struct SuperHCPUListState {
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fprintf_function cpu_fprintf;
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FILE *file;
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} SuperHCPUListState;
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/* Sort alphabetically by type name. */
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static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
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{
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ObjectClass *class_a = (ObjectClass *)a;
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ObjectClass *class_b = (ObjectClass *)b;
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const char *name_a, *name_b;
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name_a = object_class_get_name(class_a);
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name_b = object_class_get_name(class_b);
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return strcmp(name_a, name_b);
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}
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static void superh_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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SuperHCPUListState *s = user_data;
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(*s->cpu_fprintf)(s->file, "%s\n",
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scc->name);
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}
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void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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SuperHCPUListState s = {
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.cpu_fprintf = cpu_fprintf,
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.file = f,
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};
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GSList *list;
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list = object_class_get_list(TYPE_SUPERH_CPU, false);
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list = g_slist_sort(list, superh_cpu_list_compare);
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g_slist_foreach(list, superh_cpu_list_entry, &s);
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g_slist_free(list);
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}
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static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
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{
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const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
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const char *name = b;
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return strcasecmp(scc->name, name);
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}
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static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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GSList *list, *item;
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if (cpu_model == NULL) {
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return NULL;
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}
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if (strcasecmp(cpu_model, "any") == 0) {
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return object_class_by_name(TYPE_SH7750R_CPU);
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}
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oc = object_class_by_name(cpu_model);
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if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
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&& !object_class_is_abstract(oc)) {
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return oc;
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}
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oc = NULL;
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list = object_class_get_list(TYPE_SUPERH_CPU, false);
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item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
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if (item != NULL) {
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oc = item->data;
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}
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g_slist_free(list);
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return oc;
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}
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SuperHCPU *cpu_sh4_init(const char *cpu_model)
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{
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2014-03-04 10:17:10 +08:00
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return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
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2012-11-19 09:42:18 +08:00
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}
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static void sh7750r_cpu_initfn(Object *obj)
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{
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7750R;
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env->features = SH_FEATURE_BCR3_AND_BCR4;
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}
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static void sh7750r_class_init(ObjectClass *oc, void *data)
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{
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->name = "SH7750R";
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2012-11-20 23:15:47 +08:00
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scc->pvr = 0x00050000;
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scc->prr = 0x00000100;
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scc->cvr = 0x00110000;
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2012-11-19 09:42:18 +08:00
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}
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static const TypeInfo sh7750r_type_info = {
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.name = TYPE_SH7750R_CPU,
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.parent = TYPE_SUPERH_CPU,
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.class_init = sh7750r_class_init,
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.instance_init = sh7750r_cpu_initfn,
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};
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static void sh7751r_cpu_initfn(Object *obj)
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{
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7751R;
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env->features = SH_FEATURE_BCR3_AND_BCR4;
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}
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static void sh7751r_class_init(ObjectClass *oc, void *data)
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{
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->name = "SH7751R";
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2012-11-20 23:15:47 +08:00
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scc->pvr = 0x04050005;
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scc->prr = 0x00000113;
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scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
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2012-11-19 09:42:18 +08:00
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}
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static const TypeInfo sh7751r_type_info = {
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.name = TYPE_SH7751R_CPU,
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.parent = TYPE_SUPERH_CPU,
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.class_init = sh7751r_class_init,
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.instance_init = sh7751r_cpu_initfn,
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};
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static void sh7785_cpu_initfn(Object *obj)
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{
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7785;
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env->features = SH_FEATURE_SH4A;
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}
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static void sh7785_class_init(ObjectClass *oc, void *data)
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{
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->name = "SH7785";
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2012-11-20 23:15:47 +08:00
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scc->pvr = 0x10300700;
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scc->prr = 0x00000200;
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scc->cvr = 0x71440211;
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2012-11-19 09:42:18 +08:00
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}
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static const TypeInfo sh7785_type_info = {
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.name = TYPE_SH7785_CPU,
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.parent = TYPE_SUPERH_CPU,
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.class_init = sh7785_class_init,
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.instance_init = sh7785_cpu_initfn,
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};
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2012-04-24 00:16:02 +08:00
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static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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2013-07-27 08:53:25 +08:00
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CPUState *cs = CPU(dev);
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2012-04-24 00:16:02 +08:00
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SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
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2013-07-27 08:53:25 +08:00
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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2012-04-24 00:16:02 +08:00
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scc->parent_realize(dev, errp);
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}
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2012-04-13 08:32:12 +08:00
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static void superh_cpu_initfn(Object *obj)
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{
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2013-01-17 19:13:41 +08:00
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CPUState *cs = CPU(obj);
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2012-04-13 08:32:12 +08:00
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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2013-01-17 19:13:41 +08:00
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cs->env_ptr = env;
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2015-06-24 10:31:18 +08:00
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cpu_exec_init(cs, &error_abort);
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2012-04-13 08:32:12 +08:00
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env->movcal_backup_tail = &(env->movcal_backup);
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2013-01-20 08:30:32 +08:00
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if (tcg_enabled()) {
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sh4_translate_init();
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}
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2012-04-13 08:32:12 +08:00
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}
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2013-01-21 02:32:33 +08:00
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static const VMStateDescription vmstate_sh_cpu = {
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.name = "cpu",
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.unmigratable = 1,
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};
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2012-02-12 00:26:17 +08:00
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static void superh_cpu_class_init(ObjectClass *oc, void *data)
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{
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2013-01-21 02:32:33 +08:00
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DeviceClass *dc = DEVICE_CLASS(oc);
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2012-02-12 00:26:17 +08:00
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CPUClass *cc = CPU_CLASS(oc);
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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2012-04-24 00:16:02 +08:00
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scc->parent_realize = dc->realize;
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dc->realize = superh_cpu_realizefn;
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2012-02-12 00:26:17 +08:00
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scc->parent_reset = cc->reset;
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cc->reset = superh_cpu_reset;
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2013-01-21 02:32:33 +08:00
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2012-11-19 09:42:18 +08:00
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cc->class_by_name = superh_cpu_class_by_name;
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2013-08-26 00:53:55 +08:00
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cc->has_work = superh_cpu_has_work;
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2013-02-02 17:57:51 +08:00
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cc->do_interrupt = superh_cpu_do_interrupt;
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2014-09-14 00:45:23 +08:00
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cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
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2013-05-27 07:33:50 +08:00
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cc->dump_state = superh_cpu_dump_state;
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2013-06-22 01:09:18 +08:00
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cc->set_pc = superh_cpu_set_pc;
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2013-06-29 01:31:32 +08:00
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cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
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2013-06-29 10:18:45 +08:00
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cc->gdb_read_register = superh_cpu_gdb_read_register;
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cc->gdb_write_register = superh_cpu_gdb_write_register;
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2013-08-26 09:01:33 +08:00
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
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#else
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2013-06-30 00:55:54 +08:00
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cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
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#endif
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2013-01-21 02:32:33 +08:00
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dc->vmsd = &vmstate_sh_cpu;
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2013-06-29 05:18:47 +08:00
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cc->gdb_num_core_regs = 59;
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2012-02-12 00:26:17 +08:00
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}
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static const TypeInfo superh_cpu_type_info = {
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.name = TYPE_SUPERH_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(SuperHCPU),
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2012-04-13 08:32:12 +08:00
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.instance_init = superh_cpu_initfn,
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2012-11-19 09:42:18 +08:00
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.abstract = true,
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2012-02-12 00:26:17 +08:00
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.class_size = sizeof(SuperHCPUClass),
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.class_init = superh_cpu_class_init,
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};
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static void superh_cpu_register_types(void)
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{
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type_register_static(&superh_cpu_type_info);
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2012-11-19 09:42:18 +08:00
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type_register_static(&sh7750r_type_info);
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type_register_static(&sh7751r_type_info);
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type_register_static(&sh7785_type_info);
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2012-02-12 00:26:17 +08:00
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}
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type_init(superh_cpu_register_types)
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