2005-07-02 22:31:34 +08:00
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/*
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2008-07-22 15:07:34 +08:00
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* QEMU Sun4u/Sun4v System Emulator
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2007-09-17 05:08:06 +08:00
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*
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2005-07-02 22:31:34 +08:00
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* Copyright (c) 2005 Fabrice Bellard
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2007-09-17 05:08:06 +08:00
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*
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2005-07-02 22:31:34 +08:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-01-27 02:16:59 +08:00
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#include "qemu/osdep.h"
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2013-02-04 22:40:22 +08:00
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#include "hw/hw.h"
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#include "hw/pci/pci.h"
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2013-02-06 00:06:20 +08:00
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#include "hw/pci-host/apb.h"
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#include "hw/i386/pc.h"
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#include "hw/char/serial.h"
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#include "hw/timer/m48t59.h"
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#include "hw/block/fdc.h"
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2012-10-24 14:43:34 +08:00
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#include "net/net.h"
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2012-12-18 01:20:00 +08:00
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#include "qemu/timer.h"
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2012-12-18 01:20:04 +08:00
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#include "sysemu/sysemu.h"
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2013-02-04 22:40:22 +08:00
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#include "hw/boards.h"
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2013-05-30 17:13:06 +08:00
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#include "hw/nvram/openbios_firmware_abi.h"
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2013-02-06 00:06:20 +08:00
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#include "hw/nvram/fw_cfg.h"
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2013-02-04 22:40:22 +08:00
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#include "hw/sysbus.h"
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#include "hw/ide.h"
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#include "hw/loader.h"
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2009-09-20 22:58:02 +08:00
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#include "elf.h"
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2014-10-07 19:59:18 +08:00
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#include "sysemu/block-backend.h"
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2012-12-18 01:19:49 +08:00
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#include "exec/address-spaces.h"
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2005-07-02 22:31:34 +08:00
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2008-09-23 03:50:28 +08:00
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//#define DEBUG_IRQ
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2009-12-30 20:27:17 +08:00
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//#define DEBUG_EBUS
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2010-01-28 05:00:53 +08:00
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//#define DEBUG_TIMER
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2008-09-23 03:50:28 +08:00
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#ifdef DEBUG_IRQ
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2009-12-30 20:27:17 +08:00
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#define CPUIRQ_DPRINTF(fmt, ...) \
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2009-05-14 01:53:17 +08:00
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
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2008-09-23 03:50:28 +08:00
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#else
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2009-12-30 20:27:17 +08:00
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#define CPUIRQ_DPRINTF(fmt, ...)
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#endif
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#ifdef DEBUG_EBUS
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#define EBUS_DPRINTF(fmt, ...) \
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do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define EBUS_DPRINTF(fmt, ...)
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2008-09-23 03:50:28 +08:00
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#endif
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2010-01-28 05:00:53 +08:00
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#ifdef DEBUG_TIMER
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#define TIMER_DPRINTF(fmt, ...) \
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do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define TIMER_DPRINTF(fmt, ...)
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#endif
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2005-07-23 22:27:54 +08:00
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#define KERNEL_LOAD_ADDR 0x00404000
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#define CMDLINE_ADDR 0x003ff000
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2008-04-27 23:29:18 +08:00
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#define PROM_SIZE_MAX (4 * 1024 * 1024)
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2007-10-06 19:28:21 +08:00
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#define PROM_VADDR 0x000ffd00000ULL
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2005-07-23 22:27:54 +08:00
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#define APB_SPECIAL_BASE 0x1fe00000000ULL
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2007-10-06 19:28:21 +08:00
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#define APB_MEM_BASE 0x1ff00000000ULL
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2010-05-25 20:09:03 +08:00
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#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
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2007-10-06 19:28:21 +08:00
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#define PROM_FILENAME "openbios-sparc64"
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2005-07-23 22:27:54 +08:00
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#define NVRAM_SIZE 0x2000
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2007-12-02 12:51:10 +08:00
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#define MAX_IDE_BUS 2
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2008-09-19 02:27:29 +08:00
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#define BIOS_CFG_IOPORT 0x510
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2009-08-08 18:44:56 +08:00
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#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
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#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
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#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
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2005-07-02 22:31:34 +08:00
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2013-04-27 13:55:11 +08:00
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#define IVEC_MAX 0x40
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2008-09-23 03:50:28 +08:00
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2008-12-23 16:47:26 +08:00
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#define TICK_MAX 0x7fffffffffffffffULL
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2008-07-22 15:07:34 +08:00
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struct hwdef {
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const char * const default_cpu_model;
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2008-09-19 02:33:18 +08:00
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uint16_t machine_id;
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2008-09-27 03:48:58 +08:00
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uint64_t prom_addr;
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uint64_t console_serial_base;
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2008-07-22 15:07:34 +08:00
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};
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2011-08-08 21:09:22 +08:00
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typedef struct EbusState {
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PCIDevice pci_dev;
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MemoryRegion bar0;
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MemoryRegion bar1;
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} EbusState;
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2016-02-04 00:28:55 +08:00
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void DMA_init(ISABus *bus, int high_page_enable)
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2010-05-22 16:00:52 +08:00
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{
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}
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2014-12-04 03:04:02 +08:00
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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Error **errp)
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2008-06-21 00:25:56 +08:00
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{
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2015-06-09 02:10:45 +08:00
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fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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2008-06-21 00:25:56 +08:00
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}
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2015-03-03 06:23:27 +08:00
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static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
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2010-02-07 16:05:03 +08:00
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const char *arch, ram_addr_t RAM_size,
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const char *boot_devices,
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uint32_t kernel_image, uint32_t kernel_size,
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const char *cmdline,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image,
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int width, int height, int depth,
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const uint8_t *macaddr)
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2005-07-23 22:27:54 +08:00
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{
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2007-05-01 22:16:52 +08:00
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unsigned int i;
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uint32_t start, end;
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2007-11-15 03:35:16 +08:00
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uint8_t image[0x1ff0];
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struct OpenBIOS_nvpart_v1 *part_header;
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2015-03-03 06:23:27 +08:00
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NvramClass *k = NVRAM_GET_CLASS(nvram);
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2007-11-15 03:35:16 +08:00
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memset(image, '\0', sizeof(image));
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2009-03-08 17:51:29 +08:00
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start = 0;
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2005-07-23 22:27:54 +08:00
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2007-05-01 22:16:52 +08:00
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// OpenBIOS nvram variables
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// Variable partition
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2007-11-15 03:35:16 +08:00
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM;
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2008-08-22 01:58:08 +08:00
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pstrcpy(part_header->name, sizeof(part_header->name), "system");
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2007-05-01 22:16:52 +08:00
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2007-11-15 03:35:16 +08:00
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end = start + sizeof(struct OpenBIOS_nvpart_v1);
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2007-05-01 22:16:52 +08:00
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for (i = 0; i < nb_prom_envs; i++)
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2007-11-15 03:35:16 +08:00
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end = OpenBIOS_set_var(image, end, prom_envs[i]);
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// End marker
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image[end++] = '\0';
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2007-05-01 22:16:52 +08:00
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end = start + ((end - start + 15) & ~15);
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2007-11-15 03:35:16 +08:00
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OpenBIOS_finish_partition(part_header, end - start);
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2007-05-01 22:16:52 +08:00
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// free partition
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start = end;
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2007-11-15 03:35:16 +08:00
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE;
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2008-08-22 01:58:08 +08:00
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pstrcpy(part_header->name, sizeof(part_header->name), "free");
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2007-05-01 22:16:52 +08:00
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end = 0x1fd0;
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2007-11-15 03:35:16 +08:00
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OpenBIOS_finish_partition(part_header, end - start);
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2008-07-15 22:54:01 +08:00
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
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2015-03-03 06:23:27 +08:00
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for (i = 0; i < sizeof(image); i++) {
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(k->write)(nvram, i, image[i]);
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}
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2007-05-01 22:16:52 +08:00
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2005-07-23 22:27:54 +08:00
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return 0;
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2005-07-02 22:31:34 +08:00
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}
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2012-05-13 01:20:52 +08:00
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static uint64_t sun4u_load_kernel(const char *kernel_filename,
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const char *initrd_filename,
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ram_addr_t RAM_size, uint64_t *initrd_size,
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uint64_t *initrd_addr, uint64_t *kernel_addr,
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uint64_t *kernel_entry)
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2009-07-21 18:49:47 +08:00
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{
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int linux_boot;
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unsigned int i;
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long kernel_size;
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2010-01-25 05:18:00 +08:00
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uint8_t *ptr;
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2012-05-13 01:20:52 +08:00
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uint64_t kernel_top;
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2009-07-21 18:49:47 +08:00
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linux_boot = (kernel_filename != NULL);
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kernel_size = 0;
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if (linux_boot) {
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2009-09-20 22:58:02 +08:00
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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2012-05-13 01:20:52 +08:00
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kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
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2015-05-11 14:29:10 +08:00
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kernel_addr, &kernel_top, 1, EM_SPARCV9, 0);
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2012-05-13 01:20:52 +08:00
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if (kernel_size < 0) {
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*kernel_addr = KERNEL_LOAD_ADDR;
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*kernel_entry = KERNEL_LOAD_ADDR;
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2009-07-21 18:49:47 +08:00
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kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
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2009-09-20 22:58:02 +08:00
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RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
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TARGET_PAGE_SIZE);
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2012-05-13 01:20:52 +08:00
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}
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if (kernel_size < 0) {
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2009-07-21 18:49:47 +08:00
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kernel_size = load_image_targphys(kernel_filename,
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KERNEL_LOAD_ADDR,
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RAM_size - KERNEL_LOAD_ADDR);
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2012-05-13 01:20:52 +08:00
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}
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2009-07-21 18:49:47 +08:00
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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2012-05-13 01:20:52 +08:00
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/* load initrd above kernel */
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2009-07-21 18:49:47 +08:00
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*initrd_size = 0;
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if (initrd_filename) {
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2012-05-13 01:20:52 +08:00
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*initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
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2009-07-21 18:49:47 +08:00
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*initrd_size = load_image_targphys(initrd_filename,
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2012-05-13 01:20:52 +08:00
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*initrd_addr,
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RAM_size - *initrd_addr);
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if ((int)*initrd_size < 0) {
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2009-07-21 18:49:47 +08:00
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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}
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if (*initrd_size > 0) {
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
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2012-05-13 01:20:52 +08:00
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ptr = rom_ptr(*kernel_addr + i);
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2010-01-25 05:18:00 +08:00
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if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
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2012-05-13 01:20:52 +08:00
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stl_p(ptr + 24, *initrd_addr + *kernel_addr);
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2010-01-25 05:18:00 +08:00
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stl_p(ptr + 28, *initrd_size);
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2009-07-21 18:49:47 +08:00
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break;
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}
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}
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}
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}
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return kernel_size;
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}
|
2005-07-02 22:31:34 +08:00
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2012-03-14 08:38:24 +08:00
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|
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void cpu_check_irqs(CPUSPARCState *env)
|
2008-09-23 03:50:28 +08:00
|
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{
|
2013-01-18 01:51:17 +08:00
|
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CPUState *cs;
|
2010-01-08 04:28:31 +08:00
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uint32_t pil = env->pil_in |
|
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
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|
2012-04-03 23:49:05 +08:00
|
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/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
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if (env->ivec_status & 0x20) {
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return;
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}
|
2013-01-18 01:51:17 +08:00
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cs = CPU(sparc_env_get_cpu(env));
|
2010-01-08 04:28:31 +08:00
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/* check if TM or SM in SOFTINT are set
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setting these also causes interrupt 14 */
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14;
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}
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|
2011-07-26 01:22:38 +08:00
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|
|
/* The bit corresponding to psrpil is (1<< psrpil), the next bit
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is (2 << psrpil). */
|
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|
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if (pil < (2 << env->psrpil)){
|
2013-01-18 01:51:17 +08:00
|
|
|
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
|
2010-01-08 04:28:31 +08:00
|
|
|
CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
|
|
|
|
env->interrupt_index);
|
|
|
|
env->interrupt_index = 0;
|
2013-01-18 05:30:20 +08:00
|
|
|
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
2010-01-08 04:28:31 +08:00
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu_interrupts_enabled(env)) {
|
2008-09-23 03:50:28 +08:00
|
|
|
|
|
|
|
unsigned int i;
|
|
|
|
|
2010-01-08 04:28:31 +08:00
|
|
|
for (i = 15; i > env->psrpil; i--) {
|
2008-09-23 03:50:28 +08:00
|
|
|
if (pil & (1 << i)) {
|
|
|
|
int old_interrupt = env->interrupt_index;
|
2010-01-08 04:28:31 +08:00
|
|
|
int new_interrupt = TT_EXTINT | i;
|
|
|
|
|
2012-04-03 23:49:05 +08:00
|
|
|
if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
|
|
|
|
&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
|
2010-01-08 04:28:31 +08:00
|
|
|
CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
|
|
|
|
"current %x >= pending %x\n",
|
|
|
|
env->tl, cpu_tsptr(env)->tt, new_interrupt);
|
|
|
|
} else if (old_interrupt != new_interrupt) {
|
|
|
|
env->interrupt_index = new_interrupt;
|
|
|
|
CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
|
|
|
|
old_interrupt, new_interrupt);
|
2013-01-18 22:03:43 +08:00
|
|
|
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
2008-09-23 03:50:28 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2013-01-18 01:51:17 +08:00
|
|
|
} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
|
2010-01-08 04:28:31 +08:00
|
|
|
CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
|
|
|
|
"current interrupt %x\n",
|
|
|
|
pil, env->pil_in, env->softint, env->interrupt_index);
|
2011-07-26 01:22:38 +08:00
|
|
|
env->interrupt_index = 0;
|
2013-01-18 05:30:20 +08:00
|
|
|
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
2008-09-23 03:50:28 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-12 10:23:07 +08:00
|
|
|
static void cpu_kick_irq(SPARCCPU *cpu)
|
2010-01-28 05:00:53 +08:00
|
|
|
{
|
2013-01-18 01:51:17 +08:00
|
|
|
CPUState *cs = CPU(cpu);
|
2012-10-12 10:23:07 +08:00
|
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
|
2013-01-18 01:51:17 +08:00
|
|
|
cs->halted = 0;
|
2010-01-28 05:00:53 +08:00
|
|
|
cpu_check_irqs(env);
|
2013-01-18 01:51:17 +08:00
|
|
|
qemu_cpu_kick(cs);
|
2010-01-28 05:00:53 +08:00
|
|
|
}
|
|
|
|
|
2012-03-11 04:37:00 +08:00
|
|
|
static void cpu_set_ivec_irq(void *opaque, int irq, int level)
|
2008-09-23 03:50:28 +08:00
|
|
|
{
|
2012-10-12 10:23:08 +08:00
|
|
|
SPARCCPU *cpu = opaque;
|
|
|
|
CPUSPARCState *env = &cpu->env;
|
2013-01-18 01:51:17 +08:00
|
|
|
CPUState *cs;
|
2008-09-23 03:50:28 +08:00
|
|
|
|
|
|
|
if (level) {
|
2012-04-03 23:49:04 +08:00
|
|
|
if (!(env->ivec_status & 0x20)) {
|
|
|
|
CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
|
2013-01-18 01:51:17 +08:00
|
|
|
cs = CPU(cpu);
|
|
|
|
cs->halted = 0;
|
2012-04-03 23:49:04 +08:00
|
|
|
env->interrupt_index = TT_IVEC;
|
|
|
|
env->ivec_status |= 0x20;
|
|
|
|
env->ivec_data[0] = (0x1f << 6) | irq;
|
|
|
|
env->ivec_data[1] = 0;
|
|
|
|
env->ivec_data[2] = 0;
|
2013-01-18 22:03:43 +08:00
|
|
|
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
2012-04-03 23:49:04 +08:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (env->ivec_status & 0x20) {
|
|
|
|
CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
|
2013-01-18 05:30:20 +08:00
|
|
|
cs = CPU(cpu);
|
2012-04-03 23:49:04 +08:00
|
|
|
env->ivec_status &= ~0x20;
|
2013-01-18 05:30:20 +08:00
|
|
|
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
2012-04-03 23:49:04 +08:00
|
|
|
}
|
2008-09-23 03:50:28 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-09-27 03:48:58 +08:00
|
|
|
typedef struct ResetData {
|
2012-05-03 09:41:16 +08:00
|
|
|
SPARCCPU *cpu;
|
2009-11-07 18:05:03 +08:00
|
|
|
uint64_t prom_addr;
|
2008-09-27 03:48:58 +08:00
|
|
|
} ResetData;
|
|
|
|
|
2012-10-12 10:23:06 +08:00
|
|
|
static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
|
2010-01-28 05:00:53 +08:00
|
|
|
QEMUBHFunc *cb, uint32_t frequency,
|
2015-11-08 20:27:38 +08:00
|
|
|
uint64_t disabled_mask, uint64_t npt_mask)
|
2010-01-28 05:00:53 +08:00
|
|
|
{
|
2011-08-21 11:09:37 +08:00
|
|
|
CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
|
2010-01-28 05:00:53 +08:00
|
|
|
|
|
|
|
timer->name = name;
|
|
|
|
timer->frequency = frequency;
|
|
|
|
timer->disabled_mask = disabled_mask;
|
2015-11-08 20:27:38 +08:00
|
|
|
timer->npt_mask = npt_mask;
|
2010-01-28 05:00:53 +08:00
|
|
|
|
|
|
|
timer->disabled = 1;
|
2015-11-08 20:27:38 +08:00
|
|
|
timer->npt = 1;
|
2013-08-21 23:03:08 +08:00
|
|
|
timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
2010-01-28 05:00:53 +08:00
|
|
|
|
2013-08-21 23:03:08 +08:00
|
|
|
timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);
|
2010-01-28 05:00:53 +08:00
|
|
|
|
|
|
|
return timer;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cpu_timer_reset(CPUTimer *timer)
|
|
|
|
{
|
|
|
|
timer->disabled = 1;
|
2013-08-21 23:03:08 +08:00
|
|
|
timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
2010-01-28 05:00:53 +08:00
|
|
|
|
2013-08-21 23:03:08 +08:00
|
|
|
timer_del(timer->qtimer);
|
2010-01-28 05:00:53 +08:00
|
|
|
}
|
|
|
|
|
2005-11-22 07:33:12 +08:00
|
|
|
static void main_cpu_reset(void *opaque)
|
|
|
|
{
|
2008-09-27 03:48:58 +08:00
|
|
|
ResetData *s = (ResetData *)opaque;
|
2012-05-03 09:41:16 +08:00
|
|
|
CPUSPARCState *env = &s->cpu->env;
|
2009-11-07 18:05:03 +08:00
|
|
|
static unsigned int nr_resets;
|
2007-05-26 02:50:28 +08:00
|
|
|
|
2012-05-03 09:41:16 +08:00
|
|
|
cpu_reset(CPU(s->cpu));
|
2010-01-28 05:00:53 +08:00
|
|
|
|
|
|
|
cpu_timer_reset(env->tick);
|
|
|
|
cpu_timer_reset(env->stick);
|
|
|
|
cpu_timer_reset(env->hstick);
|
|
|
|
|
2008-09-27 03:48:58 +08:00
|
|
|
env->gregs[1] = 0; // Memory start
|
|
|
|
env->gregs[2] = ram_size; // Memory size
|
|
|
|
env->gregs[3] = 0; // Machine description XXX
|
2009-11-07 18:05:03 +08:00
|
|
|
if (nr_resets++ == 0) {
|
|
|
|
/* Power on reset */
|
|
|
|
env->pc = s->prom_addr + 0x20ULL;
|
|
|
|
} else {
|
|
|
|
env->pc = s->prom_addr + 0x40ULL;
|
|
|
|
}
|
2008-09-27 03:48:58 +08:00
|
|
|
env->npc = env->pc + 4;
|
2007-05-26 02:50:28 +08:00
|
|
|
}
|
|
|
|
|
2008-05-10 18:12:00 +08:00
|
|
|
static void tick_irq(void *opaque)
|
2007-05-26 02:50:28 +08:00
|
|
|
{
|
2012-10-12 10:23:06 +08:00
|
|
|
SPARCCPU *cpu = opaque;
|
|
|
|
CPUSPARCState *env = &cpu->env;
|
2007-05-26 02:50:28 +08:00
|
|
|
|
2010-01-28 05:00:53 +08:00
|
|
|
CPUTimer* timer = env->tick;
|
|
|
|
|
|
|
|
if (timer->disabled) {
|
|
|
|
CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
|
|
|
|
return;
|
|
|
|
} else {
|
|
|
|
CPUIRQ_DPRINTF("tick: fire\n");
|
2008-12-23 16:47:26 +08:00
|
|
|
}
|
2010-01-28 05:00:53 +08:00
|
|
|
|
|
|
|
env->softint |= SOFTINT_TIMER;
|
2012-10-12 10:23:07 +08:00
|
|
|
cpu_kick_irq(cpu);
|
2007-05-26 02:50:28 +08:00
|
|
|
}
|
|
|
|
|
2008-05-10 18:12:00 +08:00
|
|
|
static void stick_irq(void *opaque)
|
2007-05-26 02:50:28 +08:00
|
|
|
{
|
2012-10-12 10:23:06 +08:00
|
|
|
SPARCCPU *cpu = opaque;
|
|
|
|
CPUSPARCState *env = &cpu->env;
|
2007-05-26 02:50:28 +08:00
|
|
|
|
2010-01-28 05:00:53 +08:00
|
|
|
CPUTimer* timer = env->stick;
|
|
|
|
|
|
|
|
if (timer->disabled) {
|
|
|
|
CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
|
|
|
|
return;
|
|
|
|
} else {
|
|
|
|
CPUIRQ_DPRINTF("stick: fire\n");
|
2008-12-23 16:47:26 +08:00
|
|
|
}
|
2010-01-28 05:00:53 +08:00
|
|
|
|
|
|
|
env->softint |= SOFTINT_STIMER;
|
2012-10-12 10:23:07 +08:00
|
|
|
cpu_kick_irq(cpu);
|
2007-05-26 02:50:28 +08:00
|
|
|
}
|
|
|
|
|
2008-05-10 18:12:00 +08:00
|
|
|
static void hstick_irq(void *opaque)
|
2007-05-26 02:50:28 +08:00
|
|
|
{
|
2012-10-12 10:23:06 +08:00
|
|
|
SPARCCPU *cpu = opaque;
|
|
|
|
CPUSPARCState *env = &cpu->env;
|
2007-05-26 02:50:28 +08:00
|
|
|
|
2010-01-28 05:00:53 +08:00
|
|
|
CPUTimer* timer = env->hstick;
|
|
|
|
|
|
|
|
if (timer->disabled) {
|
|
|
|
CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
|
|
|
|
return;
|
|
|
|
} else {
|
|
|
|
CPUIRQ_DPRINTF("hstick: fire\n");
|
2008-12-23 16:47:26 +08:00
|
|
|
}
|
2010-01-28 05:00:53 +08:00
|
|
|
|
|
|
|
env->softint |= SOFTINT_STIMER;
|
2012-10-12 10:23:07 +08:00
|
|
|
cpu_kick_irq(cpu);
|
2010-01-28 05:00:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
|
|
|
|
{
|
|
|
|
return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
|
|
|
|
{
|
|
|
|
return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
|
2005-11-22 07:33:12 +08:00
|
|
|
}
|
|
|
|
|
2010-01-28 05:00:53 +08:00
|
|
|
void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
|
2008-10-04 03:04:42 +08:00
|
|
|
{
|
2015-11-08 20:45:35 +08:00
|
|
|
uint64_t real_count = count & ~timer->npt_mask;
|
|
|
|
uint64_t npt_bit = count & timer->npt_mask;
|
2010-01-28 05:00:53 +08:00
|
|
|
|
2013-08-21 23:03:08 +08:00
|
|
|
int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
|
2010-01-28 05:00:53 +08:00
|
|
|
cpu_to_timer_ticks(real_count, timer->frequency);
|
|
|
|
|
2015-11-08 20:45:35 +08:00
|
|
|
TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
|
2010-01-28 05:00:53 +08:00
|
|
|
timer->name, real_count,
|
2015-11-08 20:45:35 +08:00
|
|
|
timer->npt ? "disabled" : "enabled", timer);
|
2010-01-28 05:00:53 +08:00
|
|
|
|
2015-11-08 20:45:35 +08:00
|
|
|
timer->npt = npt_bit ? 1 : 0;
|
2010-01-28 05:00:53 +08:00
|
|
|
timer->clock_offset = vm_clock_offset;
|
2008-10-04 03:04:42 +08:00
|
|
|
}
|
|
|
|
|
2010-01-28 05:00:53 +08:00
|
|
|
uint64_t cpu_tick_get_count(CPUTimer *timer)
|
2008-10-04 03:04:42 +08:00
|
|
|
{
|
2010-01-28 05:00:53 +08:00
|
|
|
uint64_t real_count = timer_to_cpu_ticks(
|
2013-08-21 23:03:08 +08:00
|
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
|
2010-01-28 05:00:53 +08:00
|
|
|
timer->frequency);
|
|
|
|
|
2015-11-08 20:45:35 +08:00
|
|
|
TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
|
2010-01-28 05:00:53 +08:00
|
|
|
timer->name, real_count,
|
2015-11-08 20:45:35 +08:00
|
|
|
timer->npt ? "disabled" : "enabled", timer);
|
2010-01-28 05:00:53 +08:00
|
|
|
|
2015-11-08 20:45:35 +08:00
|
|
|
if (timer->npt) {
|
|
|
|
real_count |= timer->npt_mask;
|
|
|
|
}
|
2010-01-28 05:00:53 +08:00
|
|
|
|
|
|
|
return real_count;
|
2008-10-04 03:04:42 +08:00
|
|
|
}
|
|
|
|
|
2010-01-28 05:00:53 +08:00
|
|
|
void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
|
2008-10-04 03:04:42 +08:00
|
|
|
{
|
2013-08-21 23:03:08 +08:00
|
|
|
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
2010-01-28 05:00:53 +08:00
|
|
|
|
|
|
|
uint64_t real_limit = limit & ~timer->disabled_mask;
|
|
|
|
timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
|
|
|
|
|
|
|
|
int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
|
|
|
|
timer->clock_offset;
|
|
|
|
|
|
|
|
if (expires < now) {
|
|
|
|
expires = now + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
|
|
|
|
"called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
|
|
|
|
timer->name, real_limit,
|
|
|
|
timer->disabled?"disabled":"enabled",
|
|
|
|
timer, limit,
|
|
|
|
timer_to_cpu_ticks(now - timer->clock_offset,
|
|
|
|
timer->frequency),
|
|
|
|
timer_to_cpu_ticks(expires - now, timer->frequency));
|
|
|
|
|
|
|
|
if (!real_limit) {
|
|
|
|
TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
|
|
|
|
timer->name);
|
2013-08-21 23:03:08 +08:00
|
|
|
timer_del(timer->qtimer);
|
2010-01-28 05:00:53 +08:00
|
|
|
} else if (timer->disabled) {
|
2013-08-21 23:03:08 +08:00
|
|
|
timer_del(timer->qtimer);
|
2010-01-28 05:00:53 +08:00
|
|
|
} else {
|
2013-08-21 23:03:08 +08:00
|
|
|
timer_mod(timer->qtimer, expires);
|
2010-01-28 05:00:53 +08:00
|
|
|
}
|
2008-10-04 03:04:42 +08:00
|
|
|
}
|
|
|
|
|
2012-03-11 04:37:00 +08:00
|
|
|
static void isa_irq_handler(void *opaque, int n, int level)
|
2009-08-29 03:04:13 +08:00
|
|
|
{
|
2012-03-11 04:37:00 +08:00
|
|
|
static const int isa_irq_to_ivec[16] = {
|
|
|
|
[1] = 0x29, /* keyboard */
|
|
|
|
[4] = 0x2b, /* serial */
|
|
|
|
[6] = 0x27, /* floppy */
|
|
|
|
[7] = 0x22, /* parallel */
|
|
|
|
[12] = 0x2a, /* mouse */
|
|
|
|
};
|
|
|
|
qemu_irq *irqs = opaque;
|
|
|
|
int ivec;
|
|
|
|
|
|
|
|
assert(n < 16);
|
|
|
|
ivec = isa_irq_to_ivec[n];
|
|
|
|
EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
|
|
|
|
if (ivec) {
|
|
|
|
qemu_set_irq(irqs[ivec], level);
|
|
|
|
}
|
2009-08-29 03:04:13 +08:00
|
|
|
}
|
|
|
|
|
2009-01-10 19:33:32 +08:00
|
|
|
/* EBUS (Eight bit bus) bridge */
|
2011-12-16 05:09:51 +08:00
|
|
|
static ISABus *
|
2012-03-11 04:37:00 +08:00
|
|
|
pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
|
2009-01-10 19:33:32 +08:00
|
|
|
{
|
2009-08-29 03:04:13 +08:00
|
|
|
qemu_irq *isa_irq;
|
2011-12-16 05:09:56 +08:00
|
|
|
PCIDevice *pci_dev;
|
2011-12-16 05:09:51 +08:00
|
|
|
ISABus *isa_bus;
|
2009-08-29 03:04:13 +08:00
|
|
|
|
2011-12-16 05:09:56 +08:00
|
|
|
pci_dev = pci_create_simple(bus, devfn, "ebus");
|
2013-06-07 20:11:07 +08:00
|
|
|
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
|
2012-03-11 04:37:00 +08:00
|
|
|
isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
|
2011-12-16 05:09:51 +08:00
|
|
|
isa_bus_irqs(isa_bus, isa_irq);
|
|
|
|
return isa_bus;
|
2009-07-12 16:54:49 +08:00
|
|
|
}
|
2009-01-10 19:33:32 +08:00
|
|
|
|
2015-12-18 00:35:17 +08:00
|
|
|
static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp)
|
2009-07-12 16:54:49 +08:00
|
|
|
{
|
2011-08-08 21:09:22 +08:00
|
|
|
EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
|
|
|
|
|
isa: Clean up error handling around isa_bus_new()
We can have at most one ISA bus. If you try to create another one,
isa_bus_new() complains to stderr and returns null.
isa_bus_new() is called in two contexts, machine's init() and device's
realize() methods. Since complaining to stderr is not proper in the
latter context, convert isa_bus_new() to Error.
Machine's init():
* mips_jazz_init(), called from the init() methods of machines
"magnum" and "pica"
* mips_r4k_init(), the init() method of machine "mips"
* pc_init1() called from the init() methods of non-q35 PC machines
* typhoon_init(), called from clipper_init(), the init() method of
machine "clipper"
These callers always create the first ISA bus, hence isa_bus_new()
can't fail. Simply pass &error_abort.
Device's realize():
* i82378_realize(), of PCI device "i82378"
* ich9_lpc_realize(), of PCI device "ICH9-LPC"
* pci_ebus_realize(), of PCI device "ebus"
* piix3_realize(), of PCI device "pci-piix3", abstract parent of
"PIIX3" and "PIIX3-xen"
* piix4_realize(), of PCI device "PIIX4"
* vt82c686b_realize(), of PCI device "VT82C686B"
Propagate the error. Note that these devices are typically created
only by machine init() methods with qdev_init_nofail() or similar. If
we screwed up and created an ISA bus before that call, we now give up
right away. Before, we'd hobble on, and typically die in
isa_bus_irqs(). Similar if someone finds a way to hot-plug one of
these critters.
Cc: Richard Henderson <rth@twiddle.net>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: "Hervé Poussineau" <hpoussin@reactos.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Markus Armbruster <armbru@pond.sub.org>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <1450370121-5768-11-git-send-email-armbru@redhat.com>
2015-12-18 00:35:18 +08:00
|
|
|
if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(),
|
|
|
|
pci_address_space_io(pci_dev), errp)) {
|
|
|
|
return;
|
|
|
|
}
|
2011-08-08 21:09:22 +08:00
|
|
|
|
|
|
|
pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
|
|
|
|
pci_dev->config[0x05] = 0x00;
|
|
|
|
pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
|
|
|
|
pci_dev->config[0x07] = 0x03; // status = medium devsel
|
|
|
|
pci_dev->config[0x09] = 0x00; // programming i/f
|
|
|
|
pci_dev->config[0x0D] = 0x0a; // latency_timer
|
|
|
|
|
2013-07-22 21:54:23 +08:00
|
|
|
memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
|
|
|
|
0, 0x1000000);
|
2011-08-08 21:09:31 +08:00
|
|
|
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
|
2013-07-22 21:54:23 +08:00
|
|
|
memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
|
2015-03-03 06:23:27 +08:00
|
|
|
0, 0x4000);
|
2014-08-05 01:13:11 +08:00
|
|
|
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
|
2009-01-10 19:33:32 +08:00
|
|
|
}
|
|
|
|
|
2011-12-05 02:22:06 +08:00
|
|
|
static void ebus_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
2015-12-18 00:35:17 +08:00
|
|
|
k->realize = pci_ebus_realize;
|
2011-12-05 02:22:06 +08:00
|
|
|
k->vendor_id = PCI_VENDOR_ID_SUN;
|
|
|
|
k->device_id = PCI_DEVICE_ID_SUN_EBUS;
|
|
|
|
k->revision = 0x01;
|
|
|
|
k->class_id = PCI_CLASS_BRIDGE_OTHER;
|
|
|
|
}
|
|
|
|
|
2013-01-10 23:19:07 +08:00
|
|
|
static const TypeInfo ebus_info = {
|
2011-12-08 11:34:16 +08:00
|
|
|
.name = "ebus",
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(EbusState),
|
|
|
|
.class_init = ebus_class_init,
|
2009-07-12 16:54:49 +08:00
|
|
|
};
|
|
|
|
|
2013-07-27 19:48:18 +08:00
|
|
|
#define TYPE_OPENPROM "openprom"
|
|
|
|
#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
|
|
|
|
|
2011-10-03 20:31:12 +08:00
|
|
|
typedef struct PROMState {
|
2013-07-27 19:48:18 +08:00
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
2011-10-03 20:31:12 +08:00
|
|
|
MemoryRegion prom;
|
|
|
|
} PROMState;
|
|
|
|
|
2010-03-15 04:20:59 +08:00
|
|
|
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
|
|
|
|
{
|
2012-10-23 18:30:10 +08:00
|
|
|
hwaddr *base_addr = (hwaddr *)opaque;
|
2010-03-15 04:20:59 +08:00
|
|
|
return addr + *base_addr - PROM_VADDR;
|
|
|
|
}
|
|
|
|
|
2009-07-21 17:58:02 +08:00
|
|
|
/* Boot PROM (OpenBIOS) */
|
2012-10-23 18:30:10 +08:00
|
|
|
static void prom_init(hwaddr addr, const char *bios_name)
|
2009-07-21 17:58:02 +08:00
|
|
|
{
|
|
|
|
DeviceState *dev;
|
|
|
|
SysBusDevice *s;
|
|
|
|
char *filename;
|
|
|
|
int ret;
|
|
|
|
|
2013-07-27 19:48:18 +08:00
|
|
|
dev = qdev_create(NULL, TYPE_OPENPROM);
|
2009-10-07 07:15:58 +08:00
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 09:47:33 +08:00
|
|
|
s = SYS_BUS_DEVICE(dev);
|
2009-07-21 17:58:02 +08:00
|
|
|
|
|
|
|
sysbus_mmio_map(s, 0, addr);
|
|
|
|
|
|
|
|
/* load boot prom */
|
|
|
|
if (bios_name == NULL) {
|
|
|
|
bios_name = PROM_FILENAME;
|
|
|
|
}
|
|
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
|
|
|
|
if (filename) {
|
2010-03-15 04:20:59 +08:00
|
|
|
ret = load_elf(filename, translate_prom_address, &addr,
|
2015-05-11 14:29:10 +08:00
|
|
|
NULL, NULL, NULL, 1, EM_SPARCV9, 0);
|
2009-07-21 17:58:02 +08:00
|
|
|
if (ret < 0 || ret > PROM_SIZE_MAX) {
|
|
|
|
ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
|
|
|
|
}
|
2011-08-21 11:09:37 +08:00
|
|
|
g_free(filename);
|
2009-07-21 17:58:02 +08:00
|
|
|
} else {
|
|
|
|
ret = -1;
|
|
|
|
}
|
|
|
|
if (ret < 0 || ret > PROM_SIZE_MAX) {
|
|
|
|
fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-08-14 16:36:05 +08:00
|
|
|
static int prom_init1(SysBusDevice *dev)
|
2009-07-21 17:58:02 +08:00
|
|
|
{
|
2013-07-27 19:48:18 +08:00
|
|
|
PROMState *s = OPENPROM(dev);
|
2009-07-21 17:58:02 +08:00
|
|
|
|
2014-09-09 13:27:55 +08:00
|
|
|
memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 22:51:43 +08:00
|
|
|
&error_fatal);
|
2011-12-20 21:59:12 +08:00
|
|
|
vmstate_register_ram_global(&s->prom);
|
2011-10-03 20:31:12 +08:00
|
|
|
memory_region_set_readonly(&s->prom, true);
|
2011-11-27 17:38:10 +08:00
|
|
|
sysbus_init_mmio(dev, &s->prom);
|
2009-08-14 16:36:05 +08:00
|
|
|
return 0;
|
2009-07-21 17:58:02 +08:00
|
|
|
}
|
|
|
|
|
2012-01-25 03:12:29 +08:00
|
|
|
static Property prom_properties[] = {
|
|
|
|
{/* end of property list */},
|
|
|
|
};
|
|
|
|
|
|
|
|
static void prom_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 11:34:16 +08:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-25 03:12:29 +08:00
|
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->init = prom_init1;
|
2011-12-08 11:34:16 +08:00
|
|
|
dc->props = prom_properties;
|
2012-01-25 03:12:29 +08:00
|
|
|
}
|
|
|
|
|
2013-01-10 23:19:07 +08:00
|
|
|
static const TypeInfo prom_info = {
|
2013-07-27 19:48:18 +08:00
|
|
|
.name = TYPE_OPENPROM,
|
2011-12-08 11:34:16 +08:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(PROMState),
|
|
|
|
.class_init = prom_class_init,
|
2009-07-21 17:58:02 +08:00
|
|
|
};
|
|
|
|
|
2009-07-21 18:04:47 +08:00
|
|
|
|
2013-07-27 19:50:51 +08:00
|
|
|
#define TYPE_SUN4U_MEMORY "memory"
|
|
|
|
#define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
|
|
|
|
|
|
|
|
typedef struct RamDevice {
|
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
2011-10-03 20:31:12 +08:00
|
|
|
MemoryRegion ram;
|
2009-07-21 19:20:11 +08:00
|
|
|
uint64_t size;
|
2009-07-21 18:04:47 +08:00
|
|
|
} RamDevice;
|
|
|
|
|
|
|
|
/* System RAM */
|
2009-08-14 16:36:05 +08:00
|
|
|
static int ram_init1(SysBusDevice *dev)
|
2009-07-21 18:04:47 +08:00
|
|
|
{
|
2013-07-27 19:50:51 +08:00
|
|
|
RamDevice *d = SUN4U_RAM(dev);
|
2009-07-21 18:04:47 +08:00
|
|
|
|
2014-09-09 13:27:55 +08:00
|
|
|
memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 22:51:43 +08:00
|
|
|
&error_fatal);
|
2011-12-20 21:59:12 +08:00
|
|
|
vmstate_register_ram_global(&d->ram);
|
2011-11-27 17:38:10 +08:00
|
|
|
sysbus_init_mmio(dev, &d->ram);
|
2009-08-14 16:36:05 +08:00
|
|
|
return 0;
|
2009-07-21 18:04:47 +08:00
|
|
|
}
|
|
|
|
|
2012-10-23 18:30:10 +08:00
|
|
|
static void ram_init(hwaddr addr, ram_addr_t RAM_size)
|
2009-07-21 18:04:47 +08:00
|
|
|
{
|
|
|
|
DeviceState *dev;
|
|
|
|
SysBusDevice *s;
|
|
|
|
RamDevice *d;
|
|
|
|
|
|
|
|
/* allocate RAM */
|
2013-07-27 19:50:51 +08:00
|
|
|
dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
|
2013-01-20 09:47:33 +08:00
|
|
|
s = SYS_BUS_DEVICE(dev);
|
2009-07-21 18:04:47 +08:00
|
|
|
|
2013-07-27 19:50:51 +08:00
|
|
|
d = SUN4U_RAM(dev);
|
2009-07-21 18:04:47 +08:00
|
|
|
d->size = RAM_size;
|
2009-10-07 07:15:58 +08:00
|
|
|
qdev_init_nofail(dev);
|
2009-07-21 18:04:47 +08:00
|
|
|
|
|
|
|
sysbus_mmio_map(s, 0, addr);
|
|
|
|
}
|
|
|
|
|
2012-01-25 03:12:29 +08:00
|
|
|
static Property ram_properties[] = {
|
|
|
|
DEFINE_PROP_UINT64("size", RamDevice, size, 0),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void ram_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 11:34:16 +08:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-25 03:12:29 +08:00
|
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->init = ram_init1;
|
2011-12-08 11:34:16 +08:00
|
|
|
dc->props = ram_properties;
|
2012-01-25 03:12:29 +08:00
|
|
|
}
|
|
|
|
|
2013-01-10 23:19:07 +08:00
|
|
|
static const TypeInfo ram_info = {
|
2013-07-27 19:50:51 +08:00
|
|
|
.name = TYPE_SUN4U_MEMORY,
|
2011-12-08 11:34:16 +08:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(RamDevice),
|
|
|
|
.class_init = ram_class_init,
|
2009-07-21 18:04:47 +08:00
|
|
|
};
|
|
|
|
|
2012-05-03 09:33:52 +08:00
|
|
|
static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
|
2005-07-02 22:31:34 +08:00
|
|
|
{
|
2012-05-03 09:29:49 +08:00
|
|
|
SPARCCPU *cpu;
|
2012-03-14 08:38:24 +08:00
|
|
|
CPUSPARCState *env;
|
2008-09-27 03:48:58 +08:00
|
|
|
ResetData *reset_info;
|
2005-07-02 22:31:34 +08:00
|
|
|
|
2010-01-28 05:00:53 +08:00
|
|
|
uint32_t tick_frequency = 100*1000000;
|
|
|
|
uint32_t stick_frequency = 100*1000000;
|
|
|
|
uint32_t hstick_frequency = 100*1000000;
|
|
|
|
|
2012-05-03 09:29:49 +08:00
|
|
|
if (cpu_model == NULL) {
|
2008-07-22 15:07:34 +08:00
|
|
|
cpu_model = hwdef->default_cpu_model;
|
2012-05-03 09:29:49 +08:00
|
|
|
}
|
|
|
|
cpu = cpu_sparc_init(cpu_model);
|
|
|
|
if (cpu == NULL) {
|
2007-03-25 15:55:52 +08:00
|
|
|
fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
2012-05-03 09:29:49 +08:00
|
|
|
env = &cpu->env;
|
2007-05-26 02:50:28 +08:00
|
|
|
|
2012-10-12 10:23:06 +08:00
|
|
|
env->tick = cpu_timer_create("tick", cpu, tick_irq,
|
2015-11-08 20:27:38 +08:00
|
|
|
tick_frequency, TICK_INT_DIS,
|
|
|
|
TICK_NPT_MASK);
|
2010-01-28 05:00:53 +08:00
|
|
|
|
2012-10-12 10:23:06 +08:00
|
|
|
env->stick = cpu_timer_create("stick", cpu, stick_irq,
|
2015-11-08 20:27:38 +08:00
|
|
|
stick_frequency, TICK_INT_DIS,
|
|
|
|
TICK_NPT_MASK);
|
2007-05-26 02:50:28 +08:00
|
|
|
|
2012-10-12 10:23:06 +08:00
|
|
|
env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
|
2015-11-08 20:27:38 +08:00
|
|
|
hstick_frequency, TICK_INT_DIS,
|
|
|
|
TICK_NPT_MASK);
|
2008-09-27 03:48:58 +08:00
|
|
|
|
2011-08-21 11:09:37 +08:00
|
|
|
reset_info = g_malloc0(sizeof(ResetData));
|
2012-05-03 09:41:16 +08:00
|
|
|
reset_info->cpu = cpu;
|
2009-11-07 18:05:03 +08:00
|
|
|
reset_info->prom_addr = hwdef->prom_addr;
|
2009-06-27 15:25:07 +08:00
|
|
|
qemu_register_reset(main_cpu_reset, reset_info);
|
2005-11-22 07:33:12 +08:00
|
|
|
|
2012-05-03 09:33:52 +08:00
|
|
|
return cpu;
|
2009-07-21 18:46:23 +08:00
|
|
|
}
|
|
|
|
|
2011-08-12 07:07:21 +08:00
|
|
|
static void sun4uv_init(MemoryRegion *address_space_mem,
|
2014-05-07 22:42:57 +08:00
|
|
|
MachineState *machine,
|
2009-07-21 18:46:23 +08:00
|
|
|
const struct hwdef *hwdef)
|
|
|
|
{
|
2012-05-03 09:33:52 +08:00
|
|
|
SPARCCPU *cpu;
|
2015-03-03 06:23:27 +08:00
|
|
|
Nvram *nvram;
|
2009-07-21 18:46:23 +08:00
|
|
|
unsigned int i;
|
2012-05-13 01:20:52 +08:00
|
|
|
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
|
2009-07-21 18:46:23 +08:00
|
|
|
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
|
2011-12-16 05:09:51 +08:00
|
|
|
ISABus *isa_bus;
|
2015-03-03 06:23:27 +08:00
|
|
|
SysBusDevice *s;
|
2012-03-11 04:37:00 +08:00
|
|
|
qemu_irq *ivec_irqs, *pbm_irqs;
|
2009-08-28 21:47:03 +08:00
|
|
|
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
|
2009-09-22 19:53:18 +08:00
|
|
|
DriveInfo *fd[MAX_FD];
|
2016-02-04 00:28:57 +08:00
|
|
|
DeviceState *dev;
|
2013-04-16 08:24:08 +08:00
|
|
|
FWCfgState *fw_cfg;
|
2009-07-21 18:46:23 +08:00
|
|
|
|
|
|
|
/* init CPUs */
|
2014-05-07 22:42:57 +08:00
|
|
|
cpu = cpu_devinit(machine->cpu_model, hwdef);
|
2009-07-21 18:46:23 +08:00
|
|
|
|
2009-07-21 18:04:47 +08:00
|
|
|
/* set up devices */
|
2014-05-07 22:42:57 +08:00
|
|
|
ram_init(0, machine->ram_size);
|
2005-07-02 22:31:34 +08:00
|
|
|
|
2009-07-21 17:58:02 +08:00
|
|
|
prom_init(hwdef->prom_addr, bios_name);
|
2005-07-02 22:31:34 +08:00
|
|
|
|
2012-10-12 10:23:08 +08:00
|
|
|
ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX);
|
2012-03-11 04:37:00 +08:00
|
|
|
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
|
|
|
|
&pci_bus3, &pbm_irqs);
|
2012-09-08 18:23:54 +08:00
|
|
|
pci_vga_init(pci_bus);
|
2005-07-23 22:27:54 +08:00
|
|
|
|
2009-01-10 19:33:32 +08:00
|
|
|
// XXX Should be pci_bus3
|
2012-03-11 04:37:00 +08:00
|
|
|
isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
|
2009-01-10 19:33:32 +08:00
|
|
|
|
2008-09-27 03:48:58 +08:00
|
|
|
i = 0;
|
|
|
|
if (hwdef->console_serial_base) {
|
2011-08-12 07:07:21 +08:00
|
|
|
serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
|
2011-08-12 07:07:16 +08:00
|
|
|
NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
|
2008-09-27 03:48:58 +08:00
|
|
|
i++;
|
|
|
|
}
|
2005-07-23 22:27:54 +08:00
|
|
|
|
2015-02-05 01:33:05 +08:00
|
|
|
serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS);
|
2015-02-05 01:33:07 +08:00
|
|
|
parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
|
2005-07-23 22:27:54 +08:00
|
|
|
|
2009-01-14 03:47:10 +08:00
|
|
|
for(i = 0; i < nb_nics; i++)
|
2013-06-06 16:48:51 +08:00
|
|
|
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
|
2005-07-23 22:27:54 +08:00
|
|
|
|
2014-10-02 02:19:27 +08:00
|
|
|
ide_drive_get(hd, ARRAY_SIZE(hd));
|
2007-12-02 12:51:10 +08:00
|
|
|
|
2009-01-18 02:41:53 +08:00
|
|
|
pci_cmd646_ide_init(pci_bus, hd, 1);
|
|
|
|
|
2011-12-16 05:09:51 +08:00
|
|
|
isa_create_simple(isa_bus, "i8042");
|
2016-02-04 00:28:57 +08:00
|
|
|
|
|
|
|
/* Floppy */
|
2007-12-02 12:51:10 +08:00
|
|
|
for(i = 0; i < MAX_FD; i++) {
|
2009-09-22 19:53:18 +08:00
|
|
|
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
2007-12-02 12:51:10 +08:00
|
|
|
}
|
2016-02-04 00:28:57 +08:00
|
|
|
dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC));
|
|
|
|
if (fd[0]) {
|
|
|
|
qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
|
|
|
|
&error_abort);
|
|
|
|
}
|
|
|
|
if (fd[1]) {
|
|
|
|
qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
|
|
|
|
&error_abort);
|
|
|
|
}
|
|
|
|
qdev_prop_set_uint32(dev, "dma", -1);
|
|
|
|
qdev_init_nofail(dev);
|
2009-07-21 18:49:47 +08:00
|
|
|
|
2015-03-03 06:23:27 +08:00
|
|
|
/* Map NVRAM into I/O (ebus) space */
|
|
|
|
nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
|
|
|
|
s = SYS_BUS_DEVICE(nvram);
|
|
|
|
memory_region_add_subregion(get_system_io(), 0x2000,
|
|
|
|
sysbus_mmio_get_region(s, 0));
|
|
|
|
|
2009-07-21 18:49:47 +08:00
|
|
|
initrd_size = 0;
|
2012-05-13 01:20:52 +08:00
|
|
|
initrd_addr = 0;
|
2014-05-07 22:42:57 +08:00
|
|
|
kernel_size = sun4u_load_kernel(machine->kernel_filename,
|
|
|
|
machine->initrd_filename,
|
2012-05-13 01:20:52 +08:00
|
|
|
ram_size, &initrd_size, &initrd_addr,
|
|
|
|
&kernel_addr, &kernel_entry);
|
2009-07-21 18:49:47 +08:00
|
|
|
|
2014-05-07 22:42:57 +08:00
|
|
|
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
|
|
|
|
machine->boot_order,
|
2012-05-13 01:20:52 +08:00
|
|
|
kernel_addr, kernel_size,
|
2014-05-07 22:42:57 +08:00
|
|
|
machine->kernel_cmdline,
|
2012-05-13 01:20:52 +08:00
|
|
|
initrd_addr, initrd_size,
|
2008-07-15 22:54:01 +08:00
|
|
|
/* XXX: need an option to load a NVRAM image */
|
|
|
|
0,
|
|
|
|
graphic_width, graphic_height, graphic_depth,
|
|
|
|
(uint8_t *)&nd_table[0].macaddr);
|
2005-07-23 22:27:54 +08:00
|
|
|
|
2014-12-22 20:11:36 +08:00
|
|
|
fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
|
2013-01-23 04:25:03 +08:00
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
|
2008-09-19 02:33:18 +08:00
|
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
|
2012-05-13 01:20:52 +08:00
|
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
|
|
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
|
2014-05-07 22:42:57 +08:00
|
|
|
if (machine->kernel_cmdline) {
|
2010-01-10 05:27:04 +08:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
|
2014-05-07 22:42:57 +08:00
|
|
|
strlen(machine->kernel_cmdline) + 1);
|
|
|
|
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
|
2009-03-08 17:51:29 +08:00
|
|
|
} else {
|
2010-01-10 05:27:04 +08:00
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
2009-03-08 17:51:29 +08:00
|
|
|
}
|
2012-05-13 01:20:52 +08:00
|
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
|
|
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
|
2014-05-07 22:42:57 +08:00
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
|
2009-08-08 18:44:56 +08:00
|
|
|
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
|
|
|
|
|
2009-03-08 17:51:29 +08:00
|
|
|
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
|
2005-07-02 22:31:34 +08:00
|
|
|
}
|
|
|
|
|
2008-09-19 02:33:18 +08:00
|
|
|
enum {
|
|
|
|
sun4u_id = 0,
|
|
|
|
sun4v_id = 64,
|
2008-09-27 03:48:58 +08:00
|
|
|
niagara_id,
|
2008-09-19 02:33:18 +08:00
|
|
|
};
|
|
|
|
|
2008-07-22 15:07:34 +08:00
|
|
|
static const struct hwdef hwdefs[] = {
|
|
|
|
/* Sun4u generic PC-like machine */
|
|
|
|
{
|
2010-05-25 20:08:57 +08:00
|
|
|
.default_cpu_model = "TI UltraSparc IIi",
|
2008-09-19 02:33:18 +08:00
|
|
|
.machine_id = sun4u_id,
|
2008-09-27 03:48:58 +08:00
|
|
|
.prom_addr = 0x1fff0000000ULL,
|
|
|
|
.console_serial_base = 0,
|
2008-07-22 15:07:34 +08:00
|
|
|
},
|
|
|
|
/* Sun4v generic PC-like machine */
|
|
|
|
{
|
|
|
|
.default_cpu_model = "Sun UltraSparc T1",
|
2008-09-19 02:33:18 +08:00
|
|
|
.machine_id = sun4v_id,
|
2008-09-27 03:48:58 +08:00
|
|
|
.prom_addr = 0x1fff0000000ULL,
|
|
|
|
.console_serial_base = 0,
|
|
|
|
},
|
|
|
|
/* Sun4v generic Niagara machine */
|
|
|
|
{
|
|
|
|
.default_cpu_model = "Sun UltraSparc T1",
|
|
|
|
.machine_id = niagara_id,
|
|
|
|
.prom_addr = 0xfff0000000ULL,
|
|
|
|
.console_serial_base = 0xfff0c2c000ULL,
|
2008-07-22 15:07:34 +08:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Sun4u hardware initialisation */
|
2014-05-07 22:42:57 +08:00
|
|
|
static void sun4u_init(MachineState *machine)
|
2012-10-16 04:22:02 +08:00
|
|
|
{
|
2014-05-07 22:42:57 +08:00
|
|
|
sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
|
2008-07-22 15:07:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Sun4v hardware initialisation */
|
2014-05-07 22:42:57 +08:00
|
|
|
static void sun4v_init(MachineState *machine)
|
2012-10-16 04:22:02 +08:00
|
|
|
{
|
2014-05-07 22:42:57 +08:00
|
|
|
sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
|
2008-07-22 15:07:34 +08:00
|
|
|
}
|
|
|
|
|
2008-09-27 03:48:58 +08:00
|
|
|
/* Niagara hardware initialisation */
|
2014-05-07 22:42:57 +08:00
|
|
|
static void niagara_init(MachineState *machine)
|
2012-10-16 04:22:02 +08:00
|
|
|
{
|
2014-05-07 22:42:57 +08:00
|
|
|
sun4uv_init(get_system_memory(), machine, &hwdefs[2]);
|
2008-09-27 03:48:58 +08:00
|
|
|
}
|
|
|
|
|
2015-09-19 16:49:44 +08:00
|
|
|
static void sun4u_class_init(ObjectClass *oc, void *data)
|
2015-09-05 02:37:08 +08:00
|
|
|
{
|
2015-09-19 16:49:44 +08:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2015-09-05 02:37:08 +08:00
|
|
|
mc->desc = "Sun4u platform";
|
|
|
|
mc->init = sun4u_init;
|
|
|
|
mc->max_cpus = 1; /* XXX for now */
|
|
|
|
mc->is_default = 1;
|
|
|
|
mc->default_boot_order = "c";
|
|
|
|
}
|
2008-07-22 15:07:34 +08:00
|
|
|
|
2015-09-19 16:49:44 +08:00
|
|
|
static const TypeInfo sun4u_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("sun4u"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = sun4u_class_init,
|
|
|
|
};
|
2008-09-27 03:48:58 +08:00
|
|
|
|
2015-09-19 16:49:44 +08:00
|
|
|
static void sun4v_class_init(ObjectClass *oc, void *data)
|
2015-09-05 02:37:08 +08:00
|
|
|
{
|
2015-09-19 16:49:44 +08:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2015-09-05 02:37:08 +08:00
|
|
|
mc->desc = "Sun4v platform";
|
|
|
|
mc->init = sun4v_init;
|
|
|
|
mc->max_cpus = 1; /* XXX for now */
|
|
|
|
mc->default_boot_order = "c";
|
|
|
|
}
|
|
|
|
|
2015-09-19 16:49:44 +08:00
|
|
|
static const TypeInfo sun4v_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("sun4v"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = sun4v_class_init,
|
|
|
|
};
|
2015-09-05 02:37:08 +08:00
|
|
|
|
2015-09-19 16:49:44 +08:00
|
|
|
static void niagara_class_init(ObjectClass *oc, void *data)
|
2015-09-05 02:37:08 +08:00
|
|
|
{
|
2015-09-19 16:49:44 +08:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2015-09-05 02:37:08 +08:00
|
|
|
mc->desc = "Sun4v platform, Niagara";
|
|
|
|
mc->init = niagara_init;
|
|
|
|
mc->max_cpus = 1; /* XXX for now */
|
|
|
|
mc->default_boot_order = "c";
|
|
|
|
}
|
|
|
|
|
2015-09-19 16:49:44 +08:00
|
|
|
static const TypeInfo niagara_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("Niagara"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = niagara_class_init,
|
|
|
|
};
|
2009-05-21 07:38:09 +08:00
|
|
|
|
2012-02-09 22:20:55 +08:00
|
|
|
static void sun4u_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&ebus_info);
|
|
|
|
type_register_static(&prom_info);
|
|
|
|
type_register_static(&ram_info);
|
|
|
|
}
|
|
|
|
|
2015-09-19 16:49:44 +08:00
|
|
|
static void sun4u_machine_init(void)
|
|
|
|
{
|
|
|
|
type_register_static(&sun4u_type);
|
|
|
|
type_register_static(&sun4v_type);
|
|
|
|
type_register_static(&niagara_type);
|
|
|
|
}
|
|
|
|
|
2012-02-09 22:20:55 +08:00
|
|
|
type_init(sun4u_register_types)
|
2015-09-19 16:49:44 +08:00
|
|
|
machine_init(sun4u_machine_init)
|