2008-12-08 03:08:45 +08:00
|
|
|
/*
|
|
|
|
* SuperH on-chip PCIC emulation.
|
|
|
|
*
|
|
|
|
* Copyright (c) 2008 Takashi YOSHII
|
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
|
|
* in the Software without restriction, including without limitation the rights
|
|
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
|
|
* furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice shall be included in
|
|
|
|
* all copies or substantial portions of the Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
|
|
* THE SOFTWARE.
|
|
|
|
*/
|
2019-05-23 22:35:07 +08:00
|
|
|
|
2016-01-27 02:17:20 +08:00
|
|
|
#include "qemu/osdep.h"
|
2013-02-04 22:40:22 +08:00
|
|
|
#include "hw/sysbus.h"
|
2013-02-06 00:06:20 +08:00
|
|
|
#include "hw/sh4/sh.h"
|
2019-08-12 13:23:42 +08:00
|
|
|
#include "hw/irq.h"
|
2013-02-04 22:40:22 +08:00
|
|
|
#include "hw/pci/pci.h"
|
|
|
|
#include "hw/pci/pci_host.h"
|
2012-12-18 01:20:00 +08:00
|
|
|
#include "qemu/bswap.h"
|
2019-05-23 22:35:07 +08:00
|
|
|
#include "qemu/module.h"
|
2020-09-04 04:43:22 +08:00
|
|
|
#include "qom/object.h"
|
2008-12-08 03:08:45 +08:00
|
|
|
|
2013-07-22 21:54:29 +08:00
|
|
|
#define TYPE_SH_PCI_HOST_BRIDGE "sh_pci"
|
|
|
|
|
2020-09-17 02:25:19 +08:00
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(SHPCIState, SH_PCI_HOST_BRIDGE)
|
2013-07-22 21:54:29 +08:00
|
|
|
|
2020-09-04 04:43:22 +08:00
|
|
|
struct SHPCIState {
|
2013-07-22 21:54:29 +08:00
|
|
|
PCIHostState parent_obj;
|
|
|
|
|
2008-12-08 03:08:45 +08:00
|
|
|
PCIDevice *dev;
|
2011-01-20 01:23:59 +08:00
|
|
|
qemu_irq irq[4];
|
2011-08-15 22:17:30 +08:00
|
|
|
MemoryRegion memconfig_p4;
|
|
|
|
MemoryRegion memconfig_a7;
|
|
|
|
MemoryRegion isa;
|
2008-12-08 03:08:45 +08:00
|
|
|
uint32_t par;
|
|
|
|
uint32_t mbr;
|
|
|
|
uint32_t iobr;
|
2020-09-04 04:43:22 +08:00
|
|
|
};
|
2008-12-08 03:08:45 +08:00
|
|
|
|
2021-10-30 05:02:09 +08:00
|
|
|
static void sh_pci_reg_write(void *p, hwaddr addr, uint64_t val, unsigned size)
|
2008-12-08 03:08:45 +08:00
|
|
|
{
|
2011-01-20 01:23:59 +08:00
|
|
|
SHPCIState *pcic = p;
|
2013-07-22 21:54:29 +08:00
|
|
|
PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
|
|
|
|
|
2021-10-30 05:02:09 +08:00
|
|
|
switch (addr) {
|
2008-12-08 03:08:45 +08:00
|
|
|
case 0 ... 0xfc:
|
2016-06-11 00:10:21 +08:00
|
|
|
stl_le_p(pcic->dev->config + addr, val);
|
2008-12-08 03:08:45 +08:00
|
|
|
break;
|
|
|
|
case 0x1c0:
|
|
|
|
pcic->par = val;
|
|
|
|
break;
|
|
|
|
case 0x1c4:
|
2010-04-12 05:59:39 +08:00
|
|
|
pcic->mbr = val & 0xff000001;
|
2008-12-08 03:08:45 +08:00
|
|
|
break;
|
|
|
|
case 0x1c8:
|
sh4: Fix PCI ISA IO memory subregion
Booting the r2d machine from flash fails because flash is not discovered.
Looking at the flattened memory tree, we see the following.
FlatView #1
AS "memory", root: system
AS "cpu-memory-0", root: system
AS "sh_pci_host", root: bus master container
Root memory region: system
0000000000000000-000000000000ffff (prio 0, i/o): io
0000000000010000-0000000000ffffff (prio 0, i/o): r2d.flash @0000000000010000
The overlapping memory region is sh_pci.isa, ie the ISA I/O region bridge.
This region is initially assigned to address 0xfe240000, but overwritten
with a write into the PCIIOBR register. This write is expected to adjust
the PCI memory window, but not to change the region's base adddress.
Peter Maydell provided the following detailed explanation.
"Section 22.3.7 and in particular figure 22.3 (of "SSH7751R user's manual:
hardware") are clear about how this is supposed to work: there is a window
at 0xfe240000 in the system register space for PCI I/O space. When the CPU
makes an access into that area, the PCI controller calculates the PCI
address to use by combining bits 0..17 of the system address with the
bits 31..18 value that the guest has put into the PCIIOBR. That is, writing
to the PCIIOBR changes which section of the IO address space is visible in
the 0xfe240000 window. Instead what QEMU's implementation does is move the
window to whatever value the guest writes to the PCIIOBR register -- so if
the guest writes 0 we put the window at 0 in system address space."
Fix the problem by calling memory_region_set_alias_offset() instead of
removing and re-adding the PCI ISA subregion on writes into PCIIOBR.
At the same time, in sh_pci_device_realize(), don't set iobr since
it is overwritten later anyway. Instead, pass the base address to
memory_region_add_subregion() directly.
Many thanks to Peter Maydell for the detailed problem analysis, and for
providing suggestions on how to fix the problem.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200218201050.15273-1-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-19 04:10:50 +08:00
|
|
|
pcic->iobr = val & 0xfffc0001;
|
|
|
|
memory_region_set_alias_offset(&pcic->isa, val & 0xfffc0000);
|
2008-12-08 03:08:45 +08:00
|
|
|
break;
|
|
|
|
case 0x220:
|
2013-07-22 21:54:29 +08:00
|
|
|
pci_data_write(phb->bus, pcic->par, val, 4);
|
2008-12-08 03:08:45 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-10-30 05:02:09 +08:00
|
|
|
static uint64_t sh_pci_reg_read(void *p, hwaddr addr, unsigned size)
|
2008-12-08 03:08:45 +08:00
|
|
|
{
|
2011-01-20 01:23:59 +08:00
|
|
|
SHPCIState *pcic = p;
|
2013-07-22 21:54:29 +08:00
|
|
|
PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
|
|
|
|
|
2021-10-30 05:02:09 +08:00
|
|
|
switch (addr) {
|
2008-12-08 03:08:45 +08:00
|
|
|
case 0 ... 0xfc:
|
2016-06-11 00:10:21 +08:00
|
|
|
return ldl_le_p(pcic->dev->config + addr);
|
2008-12-08 03:08:45 +08:00
|
|
|
case 0x1c0:
|
|
|
|
return pcic->par;
|
2010-04-12 05:59:39 +08:00
|
|
|
case 0x1c4:
|
|
|
|
return pcic->mbr;
|
|
|
|
case 0x1c8:
|
|
|
|
return pcic->iobr;
|
2008-12-08 03:08:45 +08:00
|
|
|
case 0x220:
|
2013-07-22 21:54:29 +08:00
|
|
|
return pci_data_read(phb->bus, pcic->par, 4);
|
2008-12-08 03:08:45 +08:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-08-15 22:17:30 +08:00
|
|
|
static const MemoryRegionOps sh_pci_reg_ops = {
|
|
|
|
.read = sh_pci_reg_read,
|
|
|
|
.write = sh_pci_reg_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
2008-12-08 03:08:45 +08:00
|
|
|
};
|
|
|
|
|
2011-01-20 01:23:59 +08:00
|
|
|
static int sh_pci_map_irq(PCIDevice *d, int irq_num)
|
|
|
|
{
|
2020-10-11 23:04:23 +08:00
|
|
|
return PCI_SLOT(d->devfn);
|
2011-01-20 01:23:59 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_pci_set_irq(void *opaque, int irq_num, int level)
|
|
|
|
{
|
|
|
|
qemu_irq *pic = opaque;
|
|
|
|
|
|
|
|
qemu_set_irq(pic[irq_num], level);
|
|
|
|
}
|
|
|
|
|
2018-10-03 05:25:14 +08:00
|
|
|
static void sh_pci_device_realize(DeviceState *dev, Error **errp)
|
2011-01-20 01:23:59 +08:00
|
|
|
{
|
2018-10-03 05:25:14 +08:00
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
SHPCIState *s = SH_PCI_HOST_BRIDGE(dev);
|
|
|
|
PCIHostState *phb = PCI_HOST_BRIDGE(s);
|
2011-01-20 01:23:59 +08:00
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
2018-10-03 05:25:14 +08:00
|
|
|
sysbus_init_irq(sbd, &s->irq[i]);
|
2011-01-20 01:23:59 +08:00
|
|
|
}
|
2020-05-12 15:00:20 +08:00
|
|
|
phb->bus = pci_register_root_bus(dev, "pci",
|
2017-11-29 16:46:22 +08:00
|
|
|
sh_pci_set_irq, sh_pci_map_irq,
|
|
|
|
s->irq,
|
|
|
|
get_system_memory(),
|
|
|
|
get_system_io(),
|
|
|
|
PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
|
2013-06-07 09:25:08 +08:00
|
|
|
memory_region_init_io(&s->memconfig_p4, OBJECT(s), &sh_pci_reg_ops, s,
|
2011-08-15 22:17:30 +08:00
|
|
|
"sh_pci", 0x224);
|
2013-06-07 09:25:08 +08:00
|
|
|
memory_region_init_alias(&s->memconfig_a7, OBJECT(s), "sh_pci.2",
|
|
|
|
&s->memconfig_p4, 0, 0x224);
|
2013-07-22 21:54:11 +08:00
|
|
|
memory_region_init_alias(&s->isa, OBJECT(s), "sh_pci.isa",
|
|
|
|
get_system_io(), 0, 0x40000);
|
2018-10-03 05:25:14 +08:00
|
|
|
sysbus_init_mmio(sbd, &s->memconfig_p4);
|
|
|
|
sysbus_init_mmio(sbd, &s->memconfig_a7);
|
sh4: Fix PCI ISA IO memory subregion
Booting the r2d machine from flash fails because flash is not discovered.
Looking at the flattened memory tree, we see the following.
FlatView #1
AS "memory", root: system
AS "cpu-memory-0", root: system
AS "sh_pci_host", root: bus master container
Root memory region: system
0000000000000000-000000000000ffff (prio 0, i/o): io
0000000000010000-0000000000ffffff (prio 0, i/o): r2d.flash @0000000000010000
The overlapping memory region is sh_pci.isa, ie the ISA I/O region bridge.
This region is initially assigned to address 0xfe240000, but overwritten
with a write into the PCIIOBR register. This write is expected to adjust
the PCI memory window, but not to change the region's base adddress.
Peter Maydell provided the following detailed explanation.
"Section 22.3.7 and in particular figure 22.3 (of "SSH7751R user's manual:
hardware") are clear about how this is supposed to work: there is a window
at 0xfe240000 in the system register space for PCI I/O space. When the CPU
makes an access into that area, the PCI controller calculates the PCI
address to use by combining bits 0..17 of the system address with the
bits 31..18 value that the guest has put into the PCIIOBR. That is, writing
to the PCIIOBR changes which section of the IO address space is visible in
the 0xfe240000 window. Instead what QEMU's implementation does is move the
window to whatever value the guest writes to the PCIIOBR register -- so if
the guest writes 0 we put the window at 0 in system address space."
Fix the problem by calling memory_region_set_alias_offset() instead of
removing and re-adding the PCI ISA subregion on writes into PCIIOBR.
At the same time, in sh_pci_device_realize(), don't set iobr since
it is overwritten later anyway. Instead, pass the base address to
memory_region_add_subregion() directly.
Many thanks to Peter Maydell for the detailed problem analysis, and for
providing suggestions on how to fix the problem.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200218201050.15273-1-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-19 04:10:50 +08:00
|
|
|
memory_region_add_subregion(get_system_memory(), 0xfe240000, &s->isa);
|
2011-12-17 06:37:46 +08:00
|
|
|
|
2013-07-22 21:54:29 +08:00
|
|
|
s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host");
|
2011-01-20 01:23:59 +08:00
|
|
|
}
|
|
|
|
|
2015-12-18 19:03:48 +08:00
|
|
|
static void sh_pci_host_realize(PCIDevice *d, Error **errp)
|
2011-01-20 01:23:59 +08:00
|
|
|
{
|
|
|
|
pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT);
|
|
|
|
pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST |
|
|
|
|
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
|
|
|
|
}
|
|
|
|
|
2011-12-05 02:22:06 +08:00
|
|
|
static void sh_pci_host_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-29 00:26:58 +08:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-05 02:22:06 +08:00
|
|
|
|
2015-12-18 19:03:48 +08:00
|
|
|
k->realize = sh_pci_host_realize;
|
2011-12-05 02:22:06 +08:00
|
|
|
k->vendor_id = PCI_VENDOR_ID_HITACHI;
|
|
|
|
k->device_id = PCI_DEVICE_ID_HITACHI_SH7751R;
|
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-29 00:26:58 +08:00
|
|
|
/*
|
|
|
|
* PCI-facing part of the host bridge, not usable without the
|
|
|
|
* host-facing part, which can't be device_add'ed, yet.
|
|
|
|
*/
|
2017-05-04 04:35:44 +08:00
|
|
|
dc->user_creatable = false;
|
2011-12-05 02:22:06 +08:00
|
|
|
}
|
|
|
|
|
2013-01-10 23:19:07 +08:00
|
|
|
static const TypeInfo sh_pci_host_info = {
|
2011-12-08 11:34:16 +08:00
|
|
|
.name = "sh_pci_host",
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(PCIDevice),
|
|
|
|
.class_init = sh_pci_host_class_init,
|
2017-09-28 03:56:34 +08:00
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
|
|
{ },
|
|
|
|
},
|
2011-01-20 01:23:59 +08:00
|
|
|
};
|
|
|
|
|
2012-01-25 03:12:29 +08:00
|
|
|
static void sh_pci_device_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2018-10-03 05:25:14 +08:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-25 03:12:29 +08:00
|
|
|
|
2018-10-03 05:25:14 +08:00
|
|
|
dc->realize = sh_pci_device_realize;
|
2012-01-25 03:12:29 +08:00
|
|
|
}
|
|
|
|
|
2013-01-10 23:19:07 +08:00
|
|
|
static const TypeInfo sh_pci_device_info = {
|
2013-07-22 21:54:29 +08:00
|
|
|
.name = TYPE_SH_PCI_HOST_BRIDGE,
|
|
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
2011-12-08 11:34:16 +08:00
|
|
|
.instance_size = sizeof(SHPCIState),
|
|
|
|
.class_init = sh_pci_device_class_init,
|
2012-01-25 03:12:29 +08:00
|
|
|
};
|
|
|
|
|
2012-02-09 22:20:55 +08:00
|
|
|
static void sh_pci_register_types(void)
|
2008-12-08 03:08:45 +08:00
|
|
|
{
|
2011-12-08 11:34:16 +08:00
|
|
|
type_register_static(&sh_pci_device_info);
|
|
|
|
type_register_static(&sh_pci_host_info);
|
2008-12-08 03:08:45 +08:00
|
|
|
}
|
2011-01-20 01:23:59 +08:00
|
|
|
|
2012-02-09 22:20:55 +08:00
|
|
|
type_init(sh_pci_register_types)
|