2011-09-27 12:30:58 +08:00
|
|
|
/*
|
|
|
|
|
* Tiny Code Interpreter for QEMU
|
|
|
|
|
*
|
2016-04-06 04:24:51 +08:00
|
|
|
* Copyright (c) 2009, 2011, 2016 Stefan Weil
|
2011-09-27 12:30:58 +08:00
|
|
|
*
|
|
|
|
|
* This program is free software: you can redistribute it and/or modify
|
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
|
* the Free Software Foundation, either version 2 of the License, or
|
|
|
|
|
* (at your option) any later version.
|
|
|
|
|
*
|
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
|
*
|
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
|
*/
|
|
|
|
|
|
2016-01-30 01:50:05 +08:00
|
|
|
#include "qemu/osdep.h"
|
2011-09-27 12:30:58 +08:00
|
|
|
|
2016-04-06 04:24:51 +08:00
|
|
|
/* Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
|
|
|
|
|
* Without assertions, the interpreter runs much faster. */
|
|
|
|
|
#if defined(CONFIG_DEBUG_TCG)
|
|
|
|
|
# define tci_assert(cond) assert(cond)
|
|
|
|
|
#else
|
|
|
|
|
# define tci_assert(cond) ((void)0)
|
2011-09-27 12:30:58 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#include "qemu-common.h"
|
2016-05-20 19:57:31 +08:00
|
|
|
#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
|
2014-03-29 02:42:10 +08:00
|
|
|
#include "exec/cpu_ldst.h"
|
2020-01-01 19:23:00 +08:00
|
|
|
#include "tcg/tcg-op.h"
|
cfi: Initial support for cfi-icall in QEMU
LLVM/Clang, supports runtime checks for forward-edge Control-Flow
Integrity (CFI).
CFI on indirect function calls (cfi-icall) ensures that, in indirect
function calls, the function called is of the right signature for the
pointer type defined at compile time.
For this check to work, the code must always respect the function
signature when using function pointer, the function must be defined
at compile time, and be compiled with link-time optimization.
This rules out, for example, shared libraries that are dynamically loaded
(given that functions are not known at compile time), and code that is
dynamically generated at run-time.
This patch:
1) Introduces the CONFIG_CFI flag to support cfi in QEMU
2) Introduces a decorator to allow the definition of "sensitive"
functions, where a non-instrumented function may be called at runtime
through a pointer. The decorator will take care of disabling cfi-icall
checks on such functions, when cfi is enabled.
3) Marks functions currently in QEMU that exhibit such behavior,
in particular:
- The function in TCG that calls pre-compiled TBs
- The function in TCI that interprets instructions
- Functions in the plugin infrastructures that jump to callbacks
- Functions in util that directly call a signal handler
Signed-off-by: Daniele Buono <dbuono@linux.vnet.ibm.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org
Message-Id: <20201204230615.2392-3-dbuono@linux.vnet.ibm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-12-05 07:06:12 +08:00
|
|
|
#include "qemu/compiler.h"
|
2011-09-27 12:30:58 +08:00
|
|
|
|
2017-12-14 06:52:57 +08:00
|
|
|
#if MAX_OPC_PARAM_IARGS != 6
|
2011-09-27 12:30:58 +08:00
|
|
|
# error Fix needed, number of supported input arguments changed!
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
|
|
|
typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
|
2012-09-19 04:43:38 +08:00
|
|
|
tcg_target_ulong, tcg_target_ulong,
|
2011-09-27 12:30:58 +08:00
|
|
|
tcg_target_ulong, tcg_target_ulong,
|
|
|
|
|
tcg_target_ulong, tcg_target_ulong,
|
2017-12-14 06:52:57 +08:00
|
|
|
tcg_target_ulong, tcg_target_ulong,
|
2011-09-27 12:30:58 +08:00
|
|
|
tcg_target_ulong, tcg_target_ulong);
|
|
|
|
|
#else
|
|
|
|
|
typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
|
2012-09-19 04:43:38 +08:00
|
|
|
tcg_target_ulong, tcg_target_ulong,
|
2017-12-14 06:52:57 +08:00
|
|
|
tcg_target_ulong, tcg_target_ulong);
|
2011-09-27 12:30:58 +08:00
|
|
|
#endif
|
|
|
|
|
|
2021-01-25 04:57:01 +08:00
|
|
|
__thread uintptr_t tci_tb_ptr;
|
|
|
|
|
|
2017-07-14 05:10:31 +08:00
|
|
|
static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
tci_assert(index < TCG_TARGET_NB_REGS);
|
|
|
|
|
return regs[index];
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
|
2017-07-14 05:10:31 +08:00
|
|
|
static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
return (int8_t)tci_read_reg(regs, index);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
|
2017-07-14 05:10:31 +08:00
|
|
|
static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
return (int16_t)tci_read_reg(regs, index);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if TCG_TARGET_REG_BITS == 64
|
2017-07-14 05:10:31 +08:00
|
|
|
static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
return (int32_t)tci_read_reg(regs, index);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2017-07-14 05:10:31 +08:00
|
|
|
static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
return (uint8_t)tci_read_reg(regs, index);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
|
2017-07-14 05:10:31 +08:00
|
|
|
static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
return (uint16_t)tci_read_reg(regs, index);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
|
2017-07-14 05:10:31 +08:00
|
|
|
static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
return (uint32_t)tci_read_reg(regs, index);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if TCG_TARGET_REG_BITS == 64
|
2017-07-14 05:10:31 +08:00
|
|
|
static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
return tci_read_reg(regs, index);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2017-07-14 05:10:31 +08:00
|
|
|
static void
|
|
|
|
|
tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
tci_assert(index < TCG_TARGET_NB_REGS);
|
2016-04-06 04:24:51 +08:00
|
|
|
tci_assert(index != TCG_AREG0);
|
|
|
|
|
tci_assert(index != TCG_REG_CALL_STACK);
|
2017-07-14 05:10:31 +08:00
|
|
|
regs[index] = value;
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if TCG_TARGET_REG_BITS == 32
|
2017-07-14 05:10:31 +08:00
|
|
|
static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
|
|
|
|
|
uint32_t low_index, uint64_t value)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
tci_write_reg(regs, low_index, value);
|
|
|
|
|
tci_write_reg(regs, high_index, value >> 32);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
|
|
|
/* Create a 64 bit value from two 32 bit values. */
|
|
|
|
|
static uint64_t tci_uint64(uint32_t high, uint32_t low)
|
|
|
|
|
{
|
|
|
|
|
return ((uint64_t)high << 32) + low;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Read constant (native size) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2020-11-01 06:18:58 +08:00
|
|
|
tcg_target_ulong value = *(const tcg_target_ulong *)(*tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += sizeof(value);
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
2013-03-28 13:37:51 +08:00
|
|
|
/* Read unsigned constant (32 bit) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static uint32_t tci_read_i32(const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2020-11-01 06:18:58 +08:00
|
|
|
uint32_t value = *(const uint32_t *)(*tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += sizeof(value);
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
2013-03-28 13:37:51 +08:00
|
|
|
/* Read signed constant (32 bit) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static int32_t tci_read_s32(const uint8_t **tb_ptr)
|
2013-03-28 13:37:51 +08:00
|
|
|
{
|
2020-11-01 06:18:58 +08:00
|
|
|
int32_t value = *(const int32_t *)(*tb_ptr);
|
2013-03-28 13:37:51 +08:00
|
|
|
*tb_ptr += sizeof(value);
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
2011-09-27 12:30:58 +08:00
|
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
|
|
|
/* Read constant (64 bit) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static uint64_t tci_read_i64(const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2020-11-01 06:18:58 +08:00
|
|
|
uint64_t value = *(const uint64_t *)(*tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += sizeof(value);
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Read indexed register (native size) from bytecode. */
|
2017-07-14 05:10:31 +08:00
|
|
|
static tcg_target_ulong
|
2020-11-01 06:18:58 +08:00
|
|
|
tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
tcg_target_ulong value = tci_read_reg(regs, **tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += 1;
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Read indexed register (8 bit) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
uint8_t value = tci_read_reg8(regs, **tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += 1;
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
|
|
|
|
|
/* Read indexed register (8 bit signed) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
int8_t value = tci_read_reg8s(regs, **tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += 1;
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Read indexed register (16 bit) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static uint16_t tci_read_r16(const tcg_target_ulong *regs,
|
|
|
|
|
const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
uint16_t value = tci_read_reg16(regs, **tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += 1;
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
|
|
|
|
|
/* Read indexed register (16 bit signed) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static int16_t tci_read_r16s(const tcg_target_ulong *regs,
|
|
|
|
|
const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
int16_t value = tci_read_reg16s(regs, **tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += 1;
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Read indexed register (32 bit) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static uint32_t tci_read_r32(const tcg_target_ulong *regs,
|
|
|
|
|
const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
uint32_t value = tci_read_reg32(regs, **tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += 1;
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
|
|
|
/* Read two indexed registers (2 * 32 bit) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
|
|
|
|
|
const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
uint32_t low = tci_read_r32(regs, tb_ptr);
|
|
|
|
|
return tci_uint64(tci_read_r32(regs, tb_ptr), low);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
#elif TCG_TARGET_REG_BITS == 64
|
|
|
|
|
/* Read indexed register (32 bit signed) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static int32_t tci_read_r32s(const tcg_target_ulong *regs,
|
|
|
|
|
const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
int32_t value = tci_read_reg32s(regs, **tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += 1;
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Read indexed register (64 bit) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
|
|
|
|
|
const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
uint64_t value = tci_read_reg64(regs, **tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += 1;
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Read indexed register(s) with target address from bytecode. */
|
2017-07-14 05:10:31 +08:00
|
|
|
static target_ulong
|
2020-11-01 06:18:58 +08:00
|
|
|
tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
target_ulong taddr = tci_read_r(regs, tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
2017-07-14 05:10:31 +08:00
|
|
|
taddr += (uint64_t)tci_read_r(regs, tb_ptr) << 32;
|
2011-09-27 12:30:58 +08:00
|
|
|
#endif
|
|
|
|
|
return taddr;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Read indexed register or constant (native size) from bytecode. */
|
2017-07-14 05:10:31 +08:00
|
|
|
static tcg_target_ulong
|
2020-11-01 06:18:58 +08:00
|
|
|
tci_read_ri(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
|
|
|
|
tcg_target_ulong value;
|
2011-11-09 16:03:33 +08:00
|
|
|
TCGReg r = **tb_ptr;
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += 1;
|
|
|
|
|
if (r == TCG_CONST) {
|
|
|
|
|
value = tci_read_i(tb_ptr);
|
|
|
|
|
} else {
|
2017-07-14 05:10:31 +08:00
|
|
|
value = tci_read_reg(regs, r);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Read indexed register or constant (32 bit) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static uint32_t tci_read_ri32(const tcg_target_ulong *regs,
|
|
|
|
|
const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
|
|
|
|
uint32_t value;
|
2011-11-09 16:03:33 +08:00
|
|
|
TCGReg r = **tb_ptr;
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += 1;
|
|
|
|
|
if (r == TCG_CONST) {
|
|
|
|
|
value = tci_read_i32(tb_ptr);
|
|
|
|
|
} else {
|
2017-07-14 05:10:31 +08:00
|
|
|
value = tci_read_reg32(regs, r);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
|
|
|
/* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static uint64_t tci_read_ri64(const tcg_target_ulong *regs,
|
|
|
|
|
const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2017-07-14 05:10:31 +08:00
|
|
|
uint32_t low = tci_read_ri32(regs, tb_ptr);
|
|
|
|
|
return tci_uint64(tci_read_ri32(regs, tb_ptr), low);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
#elif TCG_TARGET_REG_BITS == 64
|
|
|
|
|
/* Read indexed register or constant (64 bit) from bytecode. */
|
2020-11-01 06:18:58 +08:00
|
|
|
static uint64_t tci_read_ri64(const tcg_target_ulong *regs,
|
|
|
|
|
const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
|
|
|
|
uint64_t value;
|
2011-11-09 16:03:33 +08:00
|
|
|
TCGReg r = **tb_ptr;
|
2011-09-27 12:30:58 +08:00
|
|
|
*tb_ptr += 1;
|
|
|
|
|
if (r == TCG_CONST) {
|
|
|
|
|
value = tci_read_i64(tb_ptr);
|
|
|
|
|
} else {
|
2017-07-14 05:10:31 +08:00
|
|
|
value = tci_read_reg64(regs, r);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2020-11-01 06:18:58 +08:00
|
|
|
static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2012-11-20 04:43:14 +08:00
|
|
|
tcg_target_ulong label = tci_read_i(tb_ptr);
|
2016-04-06 04:24:51 +08:00
|
|
|
tci_assert(label != 0);
|
2011-09-27 12:30:58 +08:00
|
|
|
return label;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
|
|
|
|
|
{
|
|
|
|
|
bool result = false;
|
|
|
|
|
int32_t i0 = u0;
|
|
|
|
|
int32_t i1 = u1;
|
|
|
|
|
switch (condition) {
|
|
|
|
|
case TCG_COND_EQ:
|
|
|
|
|
result = (u0 == u1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_NE:
|
|
|
|
|
result = (u0 != u1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_LT:
|
|
|
|
|
result = (i0 < i1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_GE:
|
|
|
|
|
result = (i0 >= i1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_LE:
|
|
|
|
|
result = (i0 <= i1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_GT:
|
|
|
|
|
result = (i0 > i1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_LTU:
|
|
|
|
|
result = (u0 < u1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_GEU:
|
|
|
|
|
result = (u0 >= u1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_LEU:
|
|
|
|
|
result = (u0 <= u1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_GTU:
|
|
|
|
|
result = (u0 > u1);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2021-01-28 14:11:11 +08:00
|
|
|
g_assert_not_reached();
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
|
|
|
|
|
{
|
|
|
|
|
bool result = false;
|
|
|
|
|
int64_t i0 = u0;
|
|
|
|
|
int64_t i1 = u1;
|
|
|
|
|
switch (condition) {
|
|
|
|
|
case TCG_COND_EQ:
|
|
|
|
|
result = (u0 == u1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_NE:
|
|
|
|
|
result = (u0 != u1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_LT:
|
|
|
|
|
result = (i0 < i1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_GE:
|
|
|
|
|
result = (i0 >= i1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_LE:
|
|
|
|
|
result = (i0 <= i1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_GT:
|
|
|
|
|
result = (i0 > i1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_LTU:
|
|
|
|
|
result = (u0 < u1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_GEU:
|
|
|
|
|
result = (u0 >= u1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_LEU:
|
|
|
|
|
result = (u0 <= u1);
|
|
|
|
|
break;
|
|
|
|
|
case TCG_COND_GTU:
|
|
|
|
|
result = (u0 > u1);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2021-01-28 14:11:11 +08:00
|
|
|
g_assert_not_reached();
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
2014-05-27 11:59:16 +08:00
|
|
|
#ifdef CONFIG_SOFTMMU
|
|
|
|
|
# define qemu_ld_ub \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_ld_leuw \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_ld_leul \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_ld_leq \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_ld_beuw \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_ld_beul \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_ld_beq \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_st_b(X) \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_st_lew(X) \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_st_lel(X) \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_st_leq(X) \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_st_bew(X) \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_st_bel(X) \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
# define qemu_st_beq(X) \
|
2015-05-14 00:10:33 +08:00
|
|
|
helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
|
2014-05-27 11:59:16 +08:00
|
|
|
#else
|
|
|
|
|
# define qemu_ld_ub ldub_p(g2h(taddr))
|
|
|
|
|
# define qemu_ld_leuw lduw_le_p(g2h(taddr))
|
|
|
|
|
# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr))
|
|
|
|
|
# define qemu_ld_leq ldq_le_p(g2h(taddr))
|
|
|
|
|
# define qemu_ld_beuw lduw_be_p(g2h(taddr))
|
|
|
|
|
# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr))
|
|
|
|
|
# define qemu_ld_beq ldq_be_p(g2h(taddr))
|
|
|
|
|
# define qemu_st_b(X) stb_p(g2h(taddr), X)
|
|
|
|
|
# define qemu_st_lew(X) stw_le_p(g2h(taddr), X)
|
|
|
|
|
# define qemu_st_lel(X) stl_le_p(g2h(taddr), X)
|
|
|
|
|
# define qemu_st_leq(X) stq_le_p(g2h(taddr), X)
|
|
|
|
|
# define qemu_st_bew(X) stw_be_p(g2h(taddr), X)
|
|
|
|
|
# define qemu_st_bel(X) stl_be_p(g2h(taddr), X)
|
|
|
|
|
# define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
|
|
|
|
|
#endif
|
|
|
|
|
|
2021-01-28 13:37:55 +08:00
|
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
|
|
|
# define CASE_32_64(x) \
|
|
|
|
|
case glue(glue(INDEX_op_, x), _i64): \
|
|
|
|
|
case glue(glue(INDEX_op_, x), _i32):
|
|
|
|
|
# define CASE_64(x) \
|
|
|
|
|
case glue(glue(INDEX_op_, x), _i64):
|
|
|
|
|
#else
|
|
|
|
|
# define CASE_32_64(x) \
|
|
|
|
|
case glue(glue(INDEX_op_, x), _i32):
|
|
|
|
|
# define CASE_64(x)
|
|
|
|
|
#endif
|
|
|
|
|
|
2011-09-27 12:30:58 +08:00
|
|
|
/* Interpret pseudo code in tb. */
|
cfi: Initial support for cfi-icall in QEMU
LLVM/Clang, supports runtime checks for forward-edge Control-Flow
Integrity (CFI).
CFI on indirect function calls (cfi-icall) ensures that, in indirect
function calls, the function called is of the right signature for the
pointer type defined at compile time.
For this check to work, the code must always respect the function
signature when using function pointer, the function must be defined
at compile time, and be compiled with link-time optimization.
This rules out, for example, shared libraries that are dynamically loaded
(given that functions are not known at compile time), and code that is
dynamically generated at run-time.
This patch:
1) Introduces the CONFIG_CFI flag to support cfi in QEMU
2) Introduces a decorator to allow the definition of "sensitive"
functions, where a non-instrumented function may be called at runtime
through a pointer. The decorator will take care of disabling cfi-icall
checks on such functions, when cfi is enabled.
3) Marks functions currently in QEMU that exhibit such behavior,
in particular:
- The function in TCG that calls pre-compiled TBs
- The function in TCI that interprets instructions
- Functions in the plugin infrastructures that jump to callbacks
- Functions in util that directly call a signal handler
Signed-off-by: Daniele Buono <dbuono@linux.vnet.ibm.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org
Message-Id: <20201204230615.2392-3-dbuono@linux.vnet.ibm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-12-05 07:06:12 +08:00
|
|
|
/*
|
|
|
|
|
* Disable CFI checks.
|
|
|
|
|
* One possible operation in the pseudo code is a call to binary code.
|
|
|
|
|
* Therefore, disable CFI checks in the interpreter function
|
|
|
|
|
*/
|
2020-10-29 03:05:44 +08:00
|
|
|
uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
|
|
|
|
|
const void *v_tb_ptr)
|
2011-09-27 12:30:58 +08:00
|
|
|
{
|
2020-11-01 06:18:58 +08:00
|
|
|
const uint8_t *tb_ptr = v_tb_ptr;
|
2017-07-14 05:10:31 +08:00
|
|
|
tcg_target_ulong regs[TCG_TARGET_NB_REGS];
|
2013-03-28 13:37:55 +08:00
|
|
|
long tcg_temps[CPU_TEMP_BUF_NLONGS];
|
|
|
|
|
uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
|
2016-04-21 20:58:23 +08:00
|
|
|
uintptr_t ret = 0;
|
2011-09-27 12:30:58 +08:00
|
|
|
|
2017-07-14 05:10:31 +08:00
|
|
|
regs[TCG_AREG0] = (tcg_target_ulong)env;
|
|
|
|
|
regs[TCG_REG_CALL_STACK] = sp_value;
|
2016-04-06 04:24:51 +08:00
|
|
|
tci_assert(tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
|
|
|
|
|
for (;;) {
|
|
|
|
|
TCGOpcode opc = tb_ptr[0];
|
2016-04-06 04:24:51 +08:00
|
|
|
#if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
|
2011-09-27 12:30:58 +08:00
|
|
|
uint8_t op_size = tb_ptr[1];
|
2020-11-01 06:18:58 +08:00
|
|
|
const uint8_t *old_code_ptr = tb_ptr;
|
2011-09-27 12:30:58 +08:00
|
|
|
#endif
|
|
|
|
|
tcg_target_ulong t0;
|
|
|
|
|
tcg_target_ulong t1;
|
|
|
|
|
tcg_target_ulong t2;
|
|
|
|
|
tcg_target_ulong label;
|
|
|
|
|
TCGCond condition;
|
|
|
|
|
target_ulong taddr;
|
|
|
|
|
uint8_t tmp8;
|
|
|
|
|
uint16_t tmp16;
|
|
|
|
|
uint32_t tmp32;
|
|
|
|
|
uint64_t tmp64;
|
|
|
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
|
|
|
uint64_t v64;
|
|
|
|
|
#endif
|
2015-05-13 02:51:44 +08:00
|
|
|
TCGMemOpIdx oi;
|
2011-09-27 12:30:58 +08:00
|
|
|
|
|
|
|
|
/* Skip opcode and size entry. */
|
|
|
|
|
tb_ptr += 2;
|
|
|
|
|
|
|
|
|
|
switch (opc) {
|
|
|
|
|
case INDEX_op_call:
|
2017-07-14 05:10:31 +08:00
|
|
|
t0 = tci_read_ri(regs, &tb_ptr);
|
2021-01-25 04:57:01 +08:00
|
|
|
tci_tb_ptr = (uintptr_t)tb_ptr;
|
2011-09-27 12:30:58 +08:00
|
|
|
#if TCG_TARGET_REG_BITS == 32
|
2017-07-14 05:10:31 +08:00
|
|
|
tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0),
|
|
|
|
|
tci_read_reg(regs, TCG_REG_R1),
|
|
|
|
|
tci_read_reg(regs, TCG_REG_R2),
|
|
|
|
|
tci_read_reg(regs, TCG_REG_R3),
|
2021-01-29 08:55:57 +08:00
|
|
|
tci_read_reg(regs, TCG_REG_R4),
|
2017-07-14 05:10:31 +08:00
|
|
|
tci_read_reg(regs, TCG_REG_R5),
|
|
|
|
|
tci_read_reg(regs, TCG_REG_R6),
|
|
|
|
|
tci_read_reg(regs, TCG_REG_R7),
|
|
|
|
|
tci_read_reg(regs, TCG_REG_R8),
|
|
|
|
|
tci_read_reg(regs, TCG_REG_R9),
|
2017-12-14 06:52:57 +08:00
|
|
|
tci_read_reg(regs, TCG_REG_R10),
|
2021-01-29 08:55:57 +08:00
|
|
|
tci_read_reg(regs, TCG_REG_R11));
|
2017-07-14 05:10:31 +08:00
|
|
|
tci_write_reg(regs, TCG_REG_R0, tmp64);
|
|
|
|
|
tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32);
|
2011-09-27 12:30:58 +08:00
|
|
|
#else
|
2017-07-14 05:10:31 +08:00
|
|
|
tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0),
|
|
|
|
|
tci_read_reg(regs, TCG_REG_R1),
|
|
|
|
|
tci_read_reg(regs, TCG_REG_R2),
|
|
|
|
|
tci_read_reg(regs, TCG_REG_R3),
|
2021-01-29 08:55:57 +08:00
|
|
|
tci_read_reg(regs, TCG_REG_R4),
|
|
|
|
|
tci_read_reg(regs, TCG_REG_R5));
|
2017-07-14 05:10:31 +08:00
|
|
|
tci_write_reg(regs, TCG_REG_R0, tmp64);
|
2011-09-27 12:30:58 +08:00
|
|
|
#endif
|
|
|
|
|
break;
|
|
|
|
|
case INDEX_op_br:
|
|
|
|
|
label = tci_read_label(&tb_ptr);
|
2016-04-06 04:24:51 +08:00
|
|
|
tci_assert(tb_ptr == old_code_ptr + op_size);
|
2011-09-27 12:30:58 +08:00
|
|
|
tb_ptr = (uint8_t *)label;
|
|
|
|
|
continue;
|
|
|
|
|
case INDEX_op_setcond_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
condition = *tb_ptr++;
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
|
|
|
case INDEX_op_setcond2_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
tmp64 = tci_read_r64(regs, &tb_ptr);
|
|
|
|
|
v64 = tci_read_ri64(regs, &tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
condition = *tb_ptr++;
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#elif TCG_TARGET_REG_BITS == 64
|
|
|
|
|
case INDEX_op_setcond_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
condition = *tb_ptr++;
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
case INDEX_op_mov_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
2020-04-18 04:19:47 +08:00
|
|
|
case INDEX_op_tci_movi_i32:
|
2011-09-27 12:30:58 +08:00
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = tci_read_i32(&tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Load/store operations (32 bit). */
|
|
|
|
|
|
2021-01-28 13:37:55 +08:00
|
|
|
CASE_32_64(ld8u)
|
2011-09-27 12:30:58 +08:00
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r(regs, &tb_ptr);
|
2013-03-28 13:37:51 +08:00
|
|
|
t2 = tci_read_s32(&tb_ptr);
|
2021-01-28 13:23:55 +08:00
|
|
|
tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
2021-01-28 13:39:39 +08:00
|
|
|
CASE_32_64(ld8s)
|
|
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = tci_read_r(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_s32(&tb_ptr);
|
|
|
|
|
tci_write_reg(regs, t0, *(int8_t *)(t1 + t2));
|
2019-04-11 03:48:38 +08:00
|
|
|
break;
|
2021-01-28 13:41:17 +08:00
|
|
|
CASE_32_64(ld16u)
|
|
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = tci_read_r(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_s32(&tb_ptr);
|
|
|
|
|
tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
2021-01-28 13:42:42 +08:00
|
|
|
CASE_32_64(ld16s)
|
2021-01-28 10:48:14 +08:00
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = tci_read_r(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_s32(&tb_ptr);
|
|
|
|
|
tci_write_reg(regs, t0, *(int16_t *)(t1 + t2));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_ld_i32:
|
2021-01-28 13:44:01 +08:00
|
|
|
CASE_64(ld32u)
|
2011-09-27 12:30:58 +08:00
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r(regs, &tb_ptr);
|
2013-03-28 13:37:51 +08:00
|
|
|
t2 = tci_read_s32(&tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
2021-01-28 13:47:02 +08:00
|
|
|
CASE_32_64(st8)
|
2017-07-14 05:10:31 +08:00
|
|
|
t0 = tci_read_r8(regs, &tb_ptr);
|
|
|
|
|
t1 = tci_read_r(regs, &tb_ptr);
|
2013-03-28 13:37:51 +08:00
|
|
|
t2 = tci_read_s32(&tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*(uint8_t *)(t1 + t2) = t0;
|
|
|
|
|
break;
|
2021-01-28 13:49:37 +08:00
|
|
|
CASE_32_64(st16)
|
2017-07-14 05:10:31 +08:00
|
|
|
t0 = tci_read_r16(regs, &tb_ptr);
|
|
|
|
|
t1 = tci_read_r(regs, &tb_ptr);
|
2013-03-28 13:37:51 +08:00
|
|
|
t2 = tci_read_s32(&tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*(uint16_t *)(t1 + t2) = t0;
|
|
|
|
|
break;
|
|
|
|
|
case INDEX_op_st_i32:
|
2021-01-28 13:53:59 +08:00
|
|
|
CASE_64(st32)
|
2017-07-14 05:10:31 +08:00
|
|
|
t0 = tci_read_r32(regs, &tb_ptr);
|
|
|
|
|
t1 = tci_read_r(regs, &tb_ptr);
|
2013-03-28 13:37:51 +08:00
|
|
|
t2 = tci_read_s32(&tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*(uint32_t *)(t1 + t2) = t0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Arithmetic operations (32 bit). */
|
|
|
|
|
|
|
|
|
|
case INDEX_op_add_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1 + t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_sub_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1 - t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_mul_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1 * t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_div_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_divu_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1 / t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_rem_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_remu_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1 % t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_and_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1 & t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_or_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1 | t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_xor_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1 ^ t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Shift/rotate operations (32 bit). */
|
|
|
|
|
|
|
|
|
|
case INDEX_op_shl_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1 << (t2 & 31));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_shr_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1 >> (t2 & 31));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_sar_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31)));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#if TCG_TARGET_HAS_rot_i32
|
|
|
|
|
case INDEX_op_rotl_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, rol32(t1, t2 & 31));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_rotr_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, ror32(t1, t2 & 31));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
2012-09-19 04:52:14 +08:00
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_deposit_i32
|
|
|
|
|
case INDEX_op_deposit_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r32(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_r32(regs, &tb_ptr);
|
2012-09-19 04:52:14 +08:00
|
|
|
tmp16 = *tb_ptr++;
|
|
|
|
|
tmp8 = *tb_ptr++;
|
|
|
|
|
tmp32 = (((1 << tmp8) - 1) << tmp16);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
|
2012-09-19 04:52:14 +08:00
|
|
|
break;
|
2011-09-27 12:30:58 +08:00
|
|
|
#endif
|
|
|
|
|
case INDEX_op_brcond_i32:
|
2017-07-14 05:10:31 +08:00
|
|
|
t0 = tci_read_r32(regs, &tb_ptr);
|
|
|
|
|
t1 = tci_read_ri32(regs, &tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
condition = *tb_ptr++;
|
|
|
|
|
label = tci_read_label(&tb_ptr);
|
|
|
|
|
if (tci_compare32(t0, t1, condition)) {
|
2016-04-06 04:24:51 +08:00
|
|
|
tci_assert(tb_ptr == old_code_ptr + op_size);
|
2011-09-27 12:30:58 +08:00
|
|
|
tb_ptr = (uint8_t *)label;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
|
|
|
case INDEX_op_add2_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
tmp64 = tci_read_r64(regs, &tb_ptr);
|
|
|
|
|
tmp64 += tci_read_r64(regs, &tb_ptr);
|
|
|
|
|
tci_write_reg64(regs, t1, t0, tmp64);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_sub2_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
tmp64 = tci_read_r64(regs, &tb_ptr);
|
|
|
|
|
tmp64 -= tci_read_r64(regs, &tb_ptr);
|
|
|
|
|
tci_write_reg64(regs, t1, t0, tmp64);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_brcond2_i32:
|
2017-07-14 05:10:31 +08:00
|
|
|
tmp64 = tci_read_r64(regs, &tb_ptr);
|
|
|
|
|
v64 = tci_read_ri64(regs, &tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
condition = *tb_ptr++;
|
|
|
|
|
label = tci_read_label(&tb_ptr);
|
|
|
|
|
if (tci_compare64(tmp64, v64, condition)) {
|
2016-04-06 04:24:51 +08:00
|
|
|
tci_assert(tb_ptr == old_code_ptr + op_size);
|
2011-09-27 12:30:58 +08:00
|
|
|
tb_ptr = (uint8_t *)label;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case INDEX_op_mulu2_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t2 = tci_read_r32(regs, &tb_ptr);
|
|
|
|
|
tmp64 = tci_read_r32(regs, &tb_ptr);
|
|
|
|
|
tci_write_reg64(regs, t1, t0, t2 * tmp64);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif /* TCG_TARGET_REG_BITS == 32 */
|
|
|
|
|
#if TCG_TARGET_HAS_ext8s_i32
|
|
|
|
|
case INDEX_op_ext8s_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r8s(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_ext16s_i32
|
|
|
|
|
case INDEX_op_ext16s_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r16s(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_ext8u_i32
|
|
|
|
|
case INDEX_op_ext8u_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r8(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_ext16u_i32
|
|
|
|
|
case INDEX_op_ext16u_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r16(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_bswap16_i32
|
|
|
|
|
case INDEX_op_bswap16_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r16(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, bswap16(t1));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_bswap32_i32
|
|
|
|
|
case INDEX_op_bswap32_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, bswap32(t1));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_not_i32
|
|
|
|
|
case INDEX_op_not_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, ~t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_neg_i32
|
|
|
|
|
case INDEX_op_neg_i32:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r32(regs, &tb_ptr);
|
2021-01-28 13:31:49 +08:00
|
|
|
tci_write_reg(regs, t0, -t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
|
|
|
case INDEX_op_mov_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
2020-04-18 04:19:47 +08:00
|
|
|
case INDEX_op_tci_movi_i64:
|
2011-09-27 12:30:58 +08:00
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = tci_read_i64(&tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Load/store operations (64 bit). */
|
|
|
|
|
|
|
|
|
|
case INDEX_op_ld32s_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r(regs, &tb_ptr);
|
2013-03-28 13:37:51 +08:00
|
|
|
t2 = tci_read_s32(&tb_ptr);
|
2021-01-28 13:21:10 +08:00
|
|
|
tci_write_reg(regs, t0, *(int32_t *)(t1 + t2));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_ld_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r(regs, &tb_ptr);
|
2013-03-28 13:37:51 +08:00
|
|
|
t2 = tci_read_s32(&tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_st_i64:
|
2017-07-14 05:10:31 +08:00
|
|
|
t0 = tci_read_r64(regs, &tb_ptr);
|
|
|
|
|
t1 = tci_read_r(regs, &tb_ptr);
|
2013-03-28 13:37:51 +08:00
|
|
|
t2 = tci_read_s32(&tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
*(uint64_t *)(t1 + t2) = t0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Arithmetic operations (64 bit). */
|
|
|
|
|
|
|
|
|
|
case INDEX_op_add_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1 + t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_sub_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1 - t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_mul_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1 * t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_div_i64:
|
2021-01-28 14:30:00 +08:00
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
|
|
|
|
|
break;
|
2011-09-27 12:30:58 +08:00
|
|
|
case INDEX_op_divu_i64:
|
2021-01-28 14:30:00 +08:00
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
|
|
|
|
|
break;
|
2011-09-27 12:30:58 +08:00
|
|
|
case INDEX_op_rem_i64:
|
2021-01-28 14:30:00 +08:00
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
|
|
|
|
|
break;
|
2011-09-27 12:30:58 +08:00
|
|
|
case INDEX_op_remu_i64:
|
2021-01-28 14:30:00 +08:00
|
|
|
t0 = *tb_ptr++;
|
|
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_and_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1 & t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_or_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1 | t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_xor_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1 ^ t2);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Shift/rotate operations (64 bit). */
|
|
|
|
|
|
|
|
|
|
case INDEX_op_shl_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1 << (t2 & 63));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_shr_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1 >> (t2 & 63));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
case INDEX_op_sar_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#if TCG_TARGET_HAS_rot_i64
|
|
|
|
|
case INDEX_op_rotl_i64:
|
2013-09-13 03:13:11 +08:00
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, rol64(t1, t2 & 63));
|
2013-09-13 03:13:11 +08:00
|
|
|
break;
|
2011-09-27 12:30:58 +08:00
|
|
|
case INDEX_op_rotr_i64:
|
2013-09-13 03:13:11 +08:00
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_ri64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, ror64(t1, t2 & 63));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
2012-09-19 04:52:14 +08:00
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_deposit_i64
|
|
|
|
|
case INDEX_op_deposit_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r64(regs, &tb_ptr);
|
|
|
|
|
t2 = tci_read_r64(regs, &tb_ptr);
|
2012-09-19 04:52:14 +08:00
|
|
|
tmp16 = *tb_ptr++;
|
|
|
|
|
tmp8 = *tb_ptr++;
|
|
|
|
|
tmp64 = (((1ULL << tmp8) - 1) << tmp16);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
|
2012-09-19 04:52:14 +08:00
|
|
|
break;
|
2011-09-27 12:30:58 +08:00
|
|
|
#endif
|
|
|
|
|
case INDEX_op_brcond_i64:
|
2017-07-14 05:10:31 +08:00
|
|
|
t0 = tci_read_r64(regs, &tb_ptr);
|
|
|
|
|
t1 = tci_read_ri64(regs, &tb_ptr);
|
2011-09-27 12:30:58 +08:00
|
|
|
condition = *tb_ptr++;
|
|
|
|
|
label = tci_read_label(&tb_ptr);
|
|
|
|
|
if (tci_compare64(t0, t1, condition)) {
|
2016-04-06 04:24:51 +08:00
|
|
|
tci_assert(tb_ptr == old_code_ptr + op_size);
|
2011-09-27 12:30:58 +08:00
|
|
|
tb_ptr = (uint8_t *)label;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
#if TCG_TARGET_HAS_ext8u_i64
|
|
|
|
|
case INDEX_op_ext8u_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r8(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_ext8s_i64
|
|
|
|
|
case INDEX_op_ext8s_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r8s(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_ext16s_i64
|
|
|
|
|
case INDEX_op_ext16s_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r16s(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_ext16u_i64
|
|
|
|
|
case INDEX_op_ext16u_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r16(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_ext32s_i64
|
|
|
|
|
case INDEX_op_ext32s_i64:
|
2015-07-27 18:41:45 +08:00
|
|
|
#endif
|
|
|
|
|
case INDEX_op_ext_i32_i64:
|
2011-09-27 12:30:58 +08:00
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r32s(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#if TCG_TARGET_HAS_ext32u_i64
|
|
|
|
|
case INDEX_op_ext32u_i64:
|
2015-07-27 18:41:45 +08:00
|
|
|
#endif
|
|
|
|
|
case INDEX_op_extu_i32_i64:
|
2011-09-27 12:30:58 +08:00
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r32(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#if TCG_TARGET_HAS_bswap16_i64
|
|
|
|
|
case INDEX_op_bswap16_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r16(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, bswap16(t1));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_bswap32_i64
|
|
|
|
|
case INDEX_op_bswap32_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r32(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, bswap32(t1));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_bswap64_i64
|
|
|
|
|
case INDEX_op_bswap64_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, bswap64(t1));
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_not_i64
|
|
|
|
|
case INDEX_op_not_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, ~t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#if TCG_TARGET_HAS_neg_i64
|
|
|
|
|
case INDEX_op_neg_i64:
|
|
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
t1 = tci_read_r64(regs, &tb_ptr);
|
2021-01-28 13:35:07 +08:00
|
|
|
tci_write_reg(regs, t0, -t1);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* TCG_TARGET_REG_BITS == 64 */
|
|
|
|
|
|
|
|
|
|
/* QEMU specific operations. */
|
|
|
|
|
|
|
|
|
|
case INDEX_op_exit_tb:
|
2016-04-21 20:58:23 +08:00
|
|
|
ret = *(uint64_t *)tb_ptr;
|
2011-09-27 12:30:58 +08:00
|
|
|
goto exit;
|
|
|
|
|
break;
|
|
|
|
|
case INDEX_op_goto_tb:
|
2016-04-23 00:08:45 +08:00
|
|
|
/* Jump address is aligned */
|
|
|
|
|
tb_ptr = QEMU_ALIGN_PTR_UP(tb_ptr, 4);
|
2020-09-23 18:56:46 +08:00
|
|
|
t0 = qatomic_read((int32_t *)tb_ptr);
|
2016-04-23 00:08:45 +08:00
|
|
|
tb_ptr += sizeof(int32_t);
|
2016-04-06 04:24:51 +08:00
|
|
|
tci_assert(tb_ptr == old_code_ptr + op_size);
|
2011-09-27 12:30:58 +08:00
|
|
|
tb_ptr += (int32_t)t0;
|
|
|
|
|
continue;
|
2014-05-27 11:59:16 +08:00
|
|
|
case INDEX_op_qemu_ld_i32:
|
2011-09-27 12:30:58 +08:00
|
|
|
t0 = *tb_ptr++;
|
2017-07-14 05:10:31 +08:00
|
|
|
taddr = tci_read_ulong(regs, &tb_ptr);
|
2015-05-13 02:51:44 +08:00
|
|
|
oi = tci_read_i(&tb_ptr);
|
2015-05-30 00:16:51 +08:00
|
|
|
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
|
2014-05-27 11:59:16 +08:00
|
|
|
case MO_UB:
|
|
|
|
|
tmp32 = qemu_ld_ub;
|
|
|
|
|
break;
|
|
|
|
|
case MO_SB:
|
|
|
|
|
tmp32 = (int8_t)qemu_ld_ub;
|
|
|
|
|
break;
|
|
|
|
|
case MO_LEUW:
|
|
|
|
|
tmp32 = qemu_ld_leuw;
|
|
|
|
|
break;
|
|
|
|
|
case MO_LESW:
|
|
|
|
|
tmp32 = (int16_t)qemu_ld_leuw;
|
|
|
|
|
break;
|
|
|
|
|
case MO_LEUL:
|
|
|
|
|
tmp32 = qemu_ld_leul;
|
|
|
|
|
break;
|
|
|
|
|
case MO_BEUW:
|
|
|
|
|
tmp32 = qemu_ld_beuw;
|
|
|
|
|
break;
|
|
|
|
|
case MO_BESW:
|
|
|
|
|
tmp32 = (int16_t)qemu_ld_beuw;
|
|
|
|
|
break;
|
|
|
|
|
case MO_BEUL:
|
|
|
|
|
tmp32 = qemu_ld_beul;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2021-01-28 14:11:11 +08:00
|
|
|
g_assert_not_reached();
|
2014-05-27 11:59:16 +08:00
|
|
|
}
|
2017-07-14 05:10:31 +08:00
|
|
|
tci_write_reg(regs, t0, tmp32);
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
2014-05-27 11:59:16 +08:00
|
|
|
case INDEX_op_qemu_ld_i64:
|
2011-09-27 12:30:58 +08:00
|
|
|
t0 = *tb_ptr++;
|
2014-05-27 11:59:16 +08:00
|
|
|
if (TCG_TARGET_REG_BITS == 32) {
|
|
|
|
|
t1 = *tb_ptr++;
|
|
|
|
|
}
|
2017-07-14 05:10:31 +08:00
|
|
|
taddr = tci_read_ulong(regs, &tb_ptr);
|
2015-05-13 02:51:44 +08:00
|
|
|
oi = tci_read_i(&tb_ptr);
|
2015-05-30 00:16:51 +08:00
|
|
|
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
|
2014-05-27 11:59:16 +08:00
|
|
|
case MO_UB:
|
|
|
|
|
tmp64 = qemu_ld_ub;
|
|
|
|
|
break;
|
|
|
|
|
case MO_SB:
|
|
|
|
|
tmp64 = (int8_t)qemu_ld_ub;
|
|
|
|
|
break;
|
|
|
|
|
case MO_LEUW:
|
|
|
|
|
tmp64 = qemu_ld_leuw;
|
|
|
|
|
break;
|
|
|
|
|
case MO_LESW:
|
|
|
|
|
tmp64 = (int16_t)qemu_ld_leuw;
|
|
|
|
|
break;
|
|
|
|
|
case MO_LEUL:
|
|
|
|
|
tmp64 = qemu_ld_leul;
|
|
|
|
|
break;
|
|
|
|
|
case MO_LESL:
|
|
|
|
|
tmp64 = (int32_t)qemu_ld_leul;
|
|
|
|
|
break;
|
|
|
|
|
case MO_LEQ:
|
|
|
|
|
tmp64 = qemu_ld_leq;
|
|
|
|
|
break;
|
|
|
|
|
case MO_BEUW:
|
|
|
|
|
tmp64 = qemu_ld_beuw;
|
|
|
|
|
break;
|
|
|
|
|
case MO_BESW:
|
|
|
|
|
tmp64 = (int16_t)qemu_ld_beuw;
|
|
|
|
|
break;
|
|
|
|
|
case MO_BEUL:
|
|
|
|
|
tmp64 = qemu_ld_beul;
|
|
|
|
|
break;
|
|
|
|
|
case MO_BESL:
|
|
|
|
|
tmp64 = (int32_t)qemu_ld_beul;
|
|
|
|
|
break;
|
|
|
|
|
case MO_BEQ:
|
|
|
|
|
tmp64 = qemu_ld_beq;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2021-01-28 14:11:11 +08:00
|
|
|
g_assert_not_reached();
|
2014-05-27 11:59:16 +08:00
|
|
|
}
|
2017-07-14 05:10:31 +08:00
|
|
|
tci_write_reg(regs, t0, tmp64);
|
2014-05-27 11:59:16 +08:00
|
|
|
if (TCG_TARGET_REG_BITS == 32) {
|
2017-07-14 05:10:31 +08:00
|
|
|
tci_write_reg(regs, t1, tmp64 >> 32);
|
2014-05-27 11:59:16 +08:00
|
|
|
}
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
2014-05-27 11:59:16 +08:00
|
|
|
case INDEX_op_qemu_st_i32:
|
2017-07-14 05:10:31 +08:00
|
|
|
t0 = tci_read_r(regs, &tb_ptr);
|
|
|
|
|
taddr = tci_read_ulong(regs, &tb_ptr);
|
2015-05-13 02:51:44 +08:00
|
|
|
oi = tci_read_i(&tb_ptr);
|
2015-05-30 00:16:51 +08:00
|
|
|
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
|
2014-05-27 11:59:16 +08:00
|
|
|
case MO_UB:
|
|
|
|
|
qemu_st_b(t0);
|
|
|
|
|
break;
|
|
|
|
|
case MO_LEUW:
|
|
|
|
|
qemu_st_lew(t0);
|
|
|
|
|
break;
|
|
|
|
|
case MO_LEUL:
|
|
|
|
|
qemu_st_lel(t0);
|
|
|
|
|
break;
|
|
|
|
|
case MO_BEUW:
|
|
|
|
|
qemu_st_bew(t0);
|
|
|
|
|
break;
|
|
|
|
|
case MO_BEUL:
|
|
|
|
|
qemu_st_bel(t0);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2021-01-28 14:11:11 +08:00
|
|
|
g_assert_not_reached();
|
2014-05-27 11:59:16 +08:00
|
|
|
}
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
2014-05-27 11:59:16 +08:00
|
|
|
case INDEX_op_qemu_st_i64:
|
2017-07-14 05:10:31 +08:00
|
|
|
tmp64 = tci_read_r64(regs, &tb_ptr);
|
|
|
|
|
taddr = tci_read_ulong(regs, &tb_ptr);
|
2015-05-13 02:51:44 +08:00
|
|
|
oi = tci_read_i(&tb_ptr);
|
2015-05-30 00:16:51 +08:00
|
|
|
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
|
2014-05-27 11:59:16 +08:00
|
|
|
case MO_UB:
|
|
|
|
|
qemu_st_b(tmp64);
|
|
|
|
|
break;
|
|
|
|
|
case MO_LEUW:
|
|
|
|
|
qemu_st_lew(tmp64);
|
|
|
|
|
break;
|
|
|
|
|
case MO_LEUL:
|
|
|
|
|
qemu_st_lel(tmp64);
|
|
|
|
|
break;
|
|
|
|
|
case MO_LEQ:
|
|
|
|
|
qemu_st_leq(tmp64);
|
|
|
|
|
break;
|
|
|
|
|
case MO_BEUW:
|
|
|
|
|
qemu_st_bew(tmp64);
|
|
|
|
|
break;
|
|
|
|
|
case MO_BEUL:
|
|
|
|
|
qemu_st_bel(tmp64);
|
|
|
|
|
break;
|
|
|
|
|
case MO_BEQ:
|
|
|
|
|
qemu_st_beq(tmp64);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2021-01-28 14:11:11 +08:00
|
|
|
g_assert_not_reached();
|
2014-05-27 11:59:16 +08:00
|
|
|
}
|
2011-09-27 12:30:58 +08:00
|
|
|
break;
|
2016-07-15 04:20:22 +08:00
|
|
|
case INDEX_op_mb:
|
|
|
|
|
/* Ensure ordering for all kinds */
|
|
|
|
|
smp_mb();
|
|
|
|
|
break;
|
2011-09-27 12:30:58 +08:00
|
|
|
default:
|
2021-01-28 14:11:11 +08:00
|
|
|
g_assert_not_reached();
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
2016-04-06 04:24:51 +08:00
|
|
|
tci_assert(tb_ptr == old_code_ptr + op_size);
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
|
|
|
|
exit:
|
2016-04-21 20:58:23 +08:00
|
|
|
return ret;
|
2011-09-27 12:30:58 +08:00
|
|
|
}
|
