2015-01-09 16:04:39 +08:00
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/*
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* s390 PCI instructions
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*
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* Copyright 2014 IBM Corp.
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* Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
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* Hong Bo Li <lihbbj@cn.ibm.com>
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* Yi Min Zhao <zyimin@cn.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at
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* your option) any later version. See the COPYING file in the top-level
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* directory.
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*/
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2016-01-27 02:17:00 +08:00
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#include "qemu/osdep.h"
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2016-01-20 04:51:44 +08:00
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#include "cpu.h"
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2015-01-09 16:04:39 +08:00
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#include "s390-pci-inst.h"
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#include "s390-pci-bus.h"
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2016-06-23 01:11:19 +08:00
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#include "exec/memory-internal.h"
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#include "qemu/error-report.h"
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2017-01-10 18:59:55 +08:00
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#include "sysemu/hw_accel.h"
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2019-01-09 01:37:30 +08:00
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#include "hw/s390x/tod.h"
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2015-01-09 16:04:39 +08:00
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2017-04-01 21:56:30 +08:00
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#ifndef DEBUG_S390PCI_INST
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#define DEBUG_S390PCI_INST 0
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2015-01-09 16:04:39 +08:00
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#endif
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2017-04-01 21:56:30 +08:00
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#define DPRINTF(fmt, ...) \
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do { \
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if (DEBUG_S390PCI_INST) { \
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fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
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} \
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} while (0)
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2015-01-09 16:04:39 +08:00
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static void s390_set_status_code(CPUS390XState *env,
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uint8_t r, uint64_t status_code)
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{
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env->regs[r] &= ~0xff000000ULL;
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env->regs[r] |= (status_code & 0xff) << 24;
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}
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static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)
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{
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2016-06-03 15:16:01 +08:00
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S390PCIBusDevice *pbdev = NULL;
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2016-11-23 11:08:29 +08:00
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S390pciState *s = s390_get_phb();
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2016-06-03 15:16:01 +08:00
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uint32_t res_code, initial_l2, g_l2;
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int rc, i;
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2015-01-09 16:04:39 +08:00
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uint64_t resume_token;
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rc = 0;
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if (lduw_p(&rrb->request.hdr.len) != 32) {
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res_code = CLP_RC_LEN;
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rc = -EINVAL;
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goto out;
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}
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if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {
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res_code = CLP_RC_FMT;
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rc = -EINVAL;
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goto out;
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}
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if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||
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2016-05-11 15:22:42 +08:00
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ldq_p(&rrb->request.reserved1) != 0) {
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2015-01-09 16:04:39 +08:00
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res_code = CLP_RC_RESNOT0;
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rc = -EINVAL;
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goto out;
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}
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resume_token = ldq_p(&rrb->request.resume_token);
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if (resume_token) {
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2016-11-23 11:08:29 +08:00
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pbdev = s390_pci_find_dev_by_idx(s, resume_token);
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2015-01-09 16:04:39 +08:00
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if (!pbdev) {
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res_code = CLP_RC_LISTPCI_BADRT;
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rc = -EINVAL;
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goto out;
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}
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2016-06-03 15:16:01 +08:00
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} else {
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2016-11-23 11:08:29 +08:00
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pbdev = s390_pci_find_next_avail_dev(s, NULL);
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2015-01-09 16:04:39 +08:00
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}
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if (lduw_p(&rrb->response.hdr.len) < 48) {
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res_code = CLP_RC_8K;
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rc = -EINVAL;
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goto out;
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}
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initial_l2 = lduw_p(&rrb->response.hdr.len);
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if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)
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!= 0) {
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res_code = CLP_RC_LEN;
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rc = -EINVAL;
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*cc = 3;
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goto out;
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}
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stl_p(&rrb->response.fmt, 0);
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stq_p(&rrb->response.reserved1, 0);
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2016-05-13 16:16:30 +08:00
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stl_p(&rrb->response.mdd, FH_MASK_SHM);
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2015-01-09 16:04:39 +08:00
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stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);
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2016-05-11 15:22:42 +08:00
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rrb->response.flags = UID_CHECKING_ENABLED;
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2015-01-09 16:04:39 +08:00
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rrb->response.entry_size = sizeof(ClpFhListEntry);
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2016-06-03 15:16:01 +08:00
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i = 0;
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2015-01-09 16:04:39 +08:00
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g_l2 = LIST_PCI_HDR_LEN;
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2016-06-03 15:16:01 +08:00
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while (g_l2 < initial_l2 && pbdev) {
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stw_p(&rrb->response.fh_list[i].device_id,
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2015-01-09 16:04:39 +08:00
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pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));
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2016-06-03 15:16:01 +08:00
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stw_p(&rrb->response.fh_list[i].vendor_id,
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2015-01-09 16:04:39 +08:00
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pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));
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2016-04-19 15:03:13 +08:00
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/* Ignore RESERVED devices. */
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2016-06-03 15:16:01 +08:00
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stl_p(&rrb->response.fh_list[i].config,
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2016-04-19 15:03:13 +08:00
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pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31);
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2016-06-03 15:16:01 +08:00
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stl_p(&rrb->response.fh_list[i].fid, pbdev->fid);
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stl_p(&rrb->response.fh_list[i].fh, pbdev->fh);
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2015-01-09 16:04:39 +08:00
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g_l2 += sizeof(ClpFhListEntry);
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/* Add endian check for DPRINTF? */
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DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
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2016-06-03 15:16:01 +08:00
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g_l2,
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lduw_p(&rrb->response.fh_list[i].vendor_id),
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lduw_p(&rrb->response.fh_list[i].device_id),
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ldl_p(&rrb->response.fh_list[i].fid),
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ldl_p(&rrb->response.fh_list[i].fh));
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2016-11-23 11:08:29 +08:00
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pbdev = s390_pci_find_next_avail_dev(s, pbdev);
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2016-06-03 15:16:01 +08:00
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i++;
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}
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if (!pbdev) {
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2015-01-09 16:04:39 +08:00
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resume_token = 0;
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} else {
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2016-06-03 15:16:01 +08:00
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resume_token = pbdev->fh & FH_MASK_INDEX;
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2015-01-09 16:04:39 +08:00
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}
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stq_p(&rrb->response.resume_token, resume_token);
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stw_p(&rrb->response.hdr.len, g_l2);
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stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);
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out:
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if (rc) {
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DPRINTF("list pci failed rc 0x%x\n", rc);
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stw_p(&rrb->response.hdr.rsp, res_code);
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}
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return rc;
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}
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2017-12-01 00:27:33 +08:00
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int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)
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2015-01-09 16:04:39 +08:00
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{
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ClpReqHdr *reqh;
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ClpRspHdr *resh;
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S390PCIBusDevice *pbdev;
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uint32_t req_len;
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uint32_t res_len;
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uint8_t buffer[4096 * 2];
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uint8_t cc = 0;
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CPUS390XState *env = &cpu->env;
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2016-11-23 11:08:29 +08:00
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S390pciState *s = s390_get_phb();
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2015-01-09 16:04:39 +08:00
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int i;
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if (env->psw.mask & PSW_MASK_PSTATE) {
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2017-12-01 00:27:33 +08:00
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s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
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2015-01-09 16:04:39 +08:00
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return 0;
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}
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2015-03-05 17:36:48 +08:00
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if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) {
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2017-12-01 00:27:35 +08:00
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s390_cpu_virt_mem_handle_exc(cpu, ra);
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2015-02-13 01:09:41 +08:00
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return 0;
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}
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2015-01-09 16:04:39 +08:00
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reqh = (ClpReqHdr *)buffer;
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req_len = lduw_p(&reqh->len);
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if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {
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2017-12-01 00:27:33 +08:00
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s390_program_interrupt(env, PGM_OPERAND, 4, ra);
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2015-01-09 16:04:39 +08:00
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return 0;
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}
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2015-03-05 17:36:48 +08:00
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if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
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2015-02-13 01:09:41 +08:00
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req_len + sizeof(*resh))) {
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2017-12-01 00:27:35 +08:00
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s390_cpu_virt_mem_handle_exc(cpu, ra);
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2015-02-13 01:09:41 +08:00
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return 0;
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}
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2015-01-09 16:04:39 +08:00
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resh = (ClpRspHdr *)(buffer + req_len);
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res_len = lduw_p(&resh->len);
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if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {
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2017-12-01 00:27:33 +08:00
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s390_program_interrupt(env, PGM_OPERAND, 4, ra);
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2015-01-09 16:04:39 +08:00
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return 0;
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}
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if ((req_len + res_len) > 8192) {
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2017-12-01 00:27:33 +08:00
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s390_program_interrupt(env, PGM_OPERAND, 4, ra);
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2015-01-09 16:04:39 +08:00
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return 0;
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}
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2015-03-05 17:36:48 +08:00
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if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
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2015-02-13 01:09:41 +08:00
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req_len + res_len)) {
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2017-12-01 00:27:35 +08:00
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s390_cpu_virt_mem_handle_exc(cpu, ra);
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2015-02-13 01:09:41 +08:00
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return 0;
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}
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2015-01-09 16:04:39 +08:00
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if (req_len != 32) {
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stw_p(&resh->rsp, CLP_RC_LEN);
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goto out;
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}
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switch (lduw_p(&reqh->cmd)) {
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case CLP_LIST_PCI: {
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ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;
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list_pci(rrb, &cc);
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break;
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}
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case CLP_SET_PCI_FN: {
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ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;
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ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;
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|
2016-11-23 11:08:29 +08:00
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pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh));
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2015-01-09 16:04:39 +08:00
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if (!pbdev) {
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stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);
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goto out;
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}
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switch (reqsetpci->oc) {
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case CLP_SET_ENABLE_PCI_FN:
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2016-06-15 17:02:36 +08:00
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switch (reqsetpci->ndas) {
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case 0:
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stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS);
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goto out;
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case 1:
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break;
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default:
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stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES);
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goto out;
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}
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if (pbdev->fh & FH_MASK_ENABLE) {
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stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
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goto out;
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}
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2016-05-13 16:16:30 +08:00
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pbdev->fh |= FH_MASK_ENABLE;
|
2016-04-19 15:03:13 +08:00
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pbdev->state = ZPCI_FS_ENABLED;
|
2015-01-09 16:04:39 +08:00
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stl_p(&ressetpci->fh, pbdev->fh);
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stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
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break;
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case CLP_SET_DISABLE_PCI_FN:
|
2016-06-15 17:02:36 +08:00
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if (!(pbdev->fh & FH_MASK_ENABLE)) {
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stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
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goto out;
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}
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device_reset(DEVICE(pbdev));
|
2016-05-13 16:16:30 +08:00
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pbdev->fh &= ~FH_MASK_ENABLE;
|
2016-04-19 15:03:13 +08:00
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pbdev->state = ZPCI_FS_DISABLED;
|
2015-01-09 16:04:39 +08:00
|
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stl_p(&ressetpci->fh, pbdev->fh);
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stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
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break;
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default:
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DPRINTF("unknown set pci command\n");
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|
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stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
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|
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break;
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}
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break;
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}
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|
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case CLP_QUERY_PCI_FN: {
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ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;
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ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;
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|
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|
2016-11-23 11:08:29 +08:00
|
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pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh));
|
2015-01-09 16:04:39 +08:00
|
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if (!pbdev) {
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DPRINTF("query pci no pci dev\n");
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stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);
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goto out;
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}
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for (i = 0; i < PCI_BAR_COUNT; i++) {
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|
|
uint32_t data = pci_get_long(pbdev->pdev->config +
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|
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PCI_BASE_ADDRESS_0 + (i * 4));
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|
|
|
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stl_p(&resquery->bar[i], data);
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|
|
resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?
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|
|
|
ctz64(pbdev->pdev->io_regions[i].size) : 0;
|
|
|
|
DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i,
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|
|
|
ldl_p(&resquery->bar[i]),
|
|
|
|
pbdev->pdev->io_regions[i].size,
|
|
|
|
resquery->bar_size[i]);
|
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|
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}
|
|
|
|
|
|
|
|
stq_p(&resquery->sdma, ZPCI_SDMA_ADDR);
|
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|
|
stq_p(&resquery->edma, ZPCI_EDMA_ADDR);
|
2016-06-13 19:28:38 +08:00
|
|
|
stl_p(&resquery->fid, pbdev->fid);
|
2015-01-09 16:04:39 +08:00
|
|
|
stw_p(&resquery->pchid, 0);
|
|
|
|
stw_p(&resquery->ug, 1);
|
2016-05-11 15:22:42 +08:00
|
|
|
stl_p(&resquery->uid, pbdev->uid);
|
2015-01-09 16:04:39 +08:00
|
|
|
stw_p(&resquery->hdr.rsp, CLP_RC_OK);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case CLP_QUERY_PCI_FNGRP: {
|
|
|
|
ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh;
|
|
|
|
resgrp->fr = 1;
|
|
|
|
stq_p(&resgrp->dasm, 0);
|
|
|
|
stq_p(&resgrp->msia, ZPCI_MSI_ADDR);
|
2019-01-09 01:37:30 +08:00
|
|
|
stw_p(&resgrp->mui, DEFAULT_MUI);
|
2015-01-09 16:04:39 +08:00
|
|
|
stw_p(&resgrp->i, 128);
|
2017-11-30 20:55:27 +08:00
|
|
|
stw_p(&resgrp->maxstbl, 128);
|
2015-01-09 16:04:39 +08:00
|
|
|
resgrp->version = 0;
|
|
|
|
|
|
|
|
stw_p(&resgrp->hdr.rsp, CLP_RC_OK);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
DPRINTF("unknown clp command\n");
|
|
|
|
stw_p(&resh->rsp, CLP_RC_CMD);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
2015-03-05 17:36:48 +08:00
|
|
|
if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer,
|
2015-02-13 01:09:41 +08:00
|
|
|
req_len + res_len)) {
|
2017-12-01 00:27:35 +08:00
|
|
|
s390_cpu_virt_mem_handle_exc(cpu, ra);
|
2015-02-13 01:09:41 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
setcc(cpu, cc);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-11-30 20:55:24 +08:00
|
|
|
/**
|
|
|
|
* Swap data contained in s390x big endian registers to little endian
|
|
|
|
* PCI bars.
|
|
|
|
*
|
|
|
|
* @ptr: a pointer to a uint64_t data field
|
|
|
|
* @len: the length of the valid data, must be 1,2,4 or 8
|
|
|
|
*/
|
|
|
|
static int zpci_endian_swap(uint64_t *ptr, uint8_t len)
|
|
|
|
{
|
|
|
|
uint64_t data = *ptr;
|
|
|
|
|
|
|
|
switch (len) {
|
|
|
|
case 1:
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
data = bswap16(data);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
data = bswap32(data);
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
data = bswap64(data);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
*ptr = data;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-11-30 20:55:30 +08:00
|
|
|
static MemoryRegion *s390_get_subregion(MemoryRegion *mr, uint64_t offset,
|
|
|
|
uint8_t len)
|
|
|
|
{
|
|
|
|
MemoryRegion *subregion;
|
|
|
|
uint64_t subregion_size;
|
|
|
|
|
|
|
|
QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
|
|
|
|
subregion_size = int128_get64(subregion->size);
|
|
|
|
if ((offset >= subregion->addr) &&
|
|
|
|
(offset + len) <= (subregion->addr + subregion_size)) {
|
|
|
|
mr = subregion;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return mr;
|
|
|
|
}
|
|
|
|
|
2017-11-30 20:55:28 +08:00
|
|
|
static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
|
|
|
|
uint64_t offset, uint64_t *data, uint8_t len)
|
|
|
|
{
|
|
|
|
MemoryRegion *mr;
|
|
|
|
|
|
|
|
mr = pbdev->pdev->io_regions[pcias].memory;
|
2017-11-30 20:55:30 +08:00
|
|
|
mr = s390_get_subregion(mr, offset, len);
|
|
|
|
offset -= mr->addr;
|
2017-11-30 20:55:28 +08:00
|
|
|
return memory_region_dispatch_read(mr, offset, data, len,
|
|
|
|
MEMTXATTRS_UNSPECIFIED);
|
|
|
|
}
|
|
|
|
|
2017-12-01 00:27:33 +08:00
|
|
|
int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
|
2015-01-09 16:04:39 +08:00
|
|
|
{
|
|
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
S390PCIBusDevice *pbdev;
|
|
|
|
uint64_t offset;
|
|
|
|
uint64_t data;
|
2016-08-24 18:53:31 +08:00
|
|
|
MemTxResult result;
|
2015-01-09 16:04:39 +08:00
|
|
|
uint8_t len;
|
|
|
|
uint32_t fh;
|
|
|
|
uint8_t pcias;
|
|
|
|
|
|
|
|
if (env->psw.mask & PSW_MASK_PSTATE) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (r2 & 0x1) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
fh = env->regs[r2] >> 32;
|
|
|
|
pcias = (env->regs[r2] >> 16) & 0xf;
|
|
|
|
len = env->regs[r2] & 0xf;
|
|
|
|
offset = env->regs[r2 + 1];
|
|
|
|
|
2017-11-30 20:55:26 +08:00
|
|
|
if (!(fh & FH_MASK_ENABLE)) {
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-23 11:08:29 +08:00
|
|
|
pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
|
2016-04-19 15:03:13 +08:00
|
|
|
if (!pbdev) {
|
2015-01-09 16:04:39 +08:00
|
|
|
DPRINTF("pcilg no pci dev\n");
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-04-19 15:03:13 +08:00
|
|
|
switch (pbdev->state) {
|
|
|
|
case ZPCI_FS_PERMANENT_ERROR:
|
|
|
|
case ZPCI_FS_ERROR:
|
2015-01-09 16:04:39 +08:00
|
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
|
|
s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
|
|
|
|
return 0;
|
2016-04-19 15:03:13 +08:00
|
|
|
default:
|
|
|
|
break;
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
|
2017-11-30 20:55:26 +08:00
|
|
|
switch (pcias) {
|
|
|
|
case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
|
|
|
|
if (!len || (len > (8 - (offset & 0x7)))) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 4, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2017-11-30 20:55:28 +08:00
|
|
|
result = zpci_read_bar(pbdev, pcias, offset, &data, len);
|
2016-08-24 18:53:31 +08:00
|
|
|
if (result != MEMTX_OK) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 4, ra);
|
2016-08-24 18:53:31 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2017-11-30 20:55:26 +08:00
|
|
|
break;
|
|
|
|
case ZPCI_CONFIG_BAR:
|
|
|
|
if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 4, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
data = pci_host_config_read_common(
|
|
|
|
pbdev->pdev, offset, pci_config_size(pbdev->pdev), len);
|
|
|
|
|
2017-11-30 20:55:24 +08:00
|
|
|
if (zpci_endian_swap(&data, len)) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 4, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2017-11-30 20:55:26 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
DPRINTF("pcilg invalid space\n");
|
2015-01-09 16:04:39 +08:00
|
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
|
|
s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-01-09 01:37:30 +08:00
|
|
|
pbdev->fmb.counter[ZPCI_FMB_CNT_LD]++;
|
|
|
|
|
2015-01-09 16:04:39 +08:00
|
|
|
env->regs[r1] = data;
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_OK);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-11-30 20:55:29 +08:00
|
|
|
static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
|
|
|
|
uint64_t offset, uint64_t data, uint8_t len)
|
|
|
|
{
|
|
|
|
MemoryRegion *mr;
|
|
|
|
|
2017-11-30 20:55:30 +08:00
|
|
|
mr = pbdev->pdev->io_regions[pcias].memory;
|
|
|
|
mr = s390_get_subregion(mr, offset, len);
|
|
|
|
offset -= mr->addr;
|
2017-11-30 20:55:29 +08:00
|
|
|
return memory_region_dispatch_write(mr, offset, data, len,
|
|
|
|
MEMTXATTRS_UNSPECIFIED);
|
|
|
|
}
|
|
|
|
|
2017-12-01 00:27:33 +08:00
|
|
|
int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
|
2015-01-09 16:04:39 +08:00
|
|
|
{
|
|
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
uint64_t offset, data;
|
|
|
|
S390PCIBusDevice *pbdev;
|
2016-08-24 18:53:31 +08:00
|
|
|
MemTxResult result;
|
2015-01-09 16:04:39 +08:00
|
|
|
uint8_t len;
|
|
|
|
uint32_t fh;
|
|
|
|
uint8_t pcias;
|
|
|
|
|
|
|
|
if (env->psw.mask & PSW_MASK_PSTATE) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (r2 & 0x1) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
fh = env->regs[r2] >> 32;
|
|
|
|
pcias = (env->regs[r2] >> 16) & 0xf;
|
|
|
|
len = env->regs[r2] & 0xf;
|
|
|
|
offset = env->regs[r2 + 1];
|
2017-11-30 20:55:25 +08:00
|
|
|
data = env->regs[r1];
|
|
|
|
|
|
|
|
if (!(fh & FH_MASK_ENABLE)) {
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
|
|
return 0;
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
|
2016-11-23 11:08:29 +08:00
|
|
|
pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
|
2016-04-19 15:03:13 +08:00
|
|
|
if (!pbdev) {
|
2015-01-09 16:04:39 +08:00
|
|
|
DPRINTF("pcistg no pci dev\n");
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-04-19 15:03:13 +08:00
|
|
|
switch (pbdev->state) {
|
2017-11-30 20:55:25 +08:00
|
|
|
/* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED
|
|
|
|
* are already covered by the FH_MASK_ENABLE check above
|
|
|
|
*/
|
2016-04-19 15:03:13 +08:00
|
|
|
case ZPCI_FS_PERMANENT_ERROR:
|
|
|
|
case ZPCI_FS_ERROR:
|
2015-01-09 16:04:39 +08:00
|
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
|
|
s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
|
|
|
|
return 0;
|
2016-04-19 15:03:13 +08:00
|
|
|
default:
|
|
|
|
break;
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
|
2017-11-30 20:55:25 +08:00
|
|
|
switch (pcias) {
|
|
|
|
/* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */
|
|
|
|
case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
|
|
|
|
/* Check length:
|
|
|
|
* A length of 0 is invalid and length should not cross a double word
|
|
|
|
*/
|
|
|
|
if (!len || (len > (8 - (offset & 0x7)))) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 4, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2016-08-24 18:46:34 +08:00
|
|
|
|
2017-11-30 20:55:29 +08:00
|
|
|
result = zpci_write_bar(pbdev, pcias, offset, data, len);
|
2016-08-24 18:53:31 +08:00
|
|
|
if (result != MEMTX_OK) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 4, ra);
|
2016-08-24 18:53:31 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2017-11-30 20:55:25 +08:00
|
|
|
break;
|
|
|
|
case ZPCI_CONFIG_BAR:
|
|
|
|
/* ZPCI uses the pseudo BAR number 15 as configuration space */
|
|
|
|
/* possible access lengths are 1,2,4 and must not cross a word */
|
|
|
|
if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 4, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2017-11-30 20:55:25 +08:00
|
|
|
/* len = 1,2,4 so we do not need to test */
|
|
|
|
zpci_endian_swap(&data, len);
|
2015-01-09 16:04:39 +08:00
|
|
|
pci_host_config_write_common(pbdev->pdev, offset,
|
|
|
|
pci_config_size(pbdev->pdev),
|
|
|
|
data, len);
|
2017-11-30 20:55:25 +08:00
|
|
|
break;
|
|
|
|
default:
|
2015-01-09 16:04:39 +08:00
|
|
|
DPRINTF("pcistg invalid space\n");
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
|
|
s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-01-09 01:37:30 +08:00
|
|
|
pbdev->fmb.counter[ZPCI_FMB_CNT_ST]++;
|
|
|
|
|
2015-01-09 16:04:39 +08:00
|
|
|
setcc(cpu, ZPCI_PCI_LS_OK);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-02-05 15:22:57 +08:00
|
|
|
static void s390_pci_update_iotlb(S390PCIIOMMU *iommu, S390IOTLBEntry *entry)
|
|
|
|
{
|
|
|
|
S390IOTLBEntry *cache = g_hash_table_lookup(iommu->iotlb, &entry->iova);
|
|
|
|
IOMMUTLBEntry notify = {
|
|
|
|
.target_as = &address_space_memory,
|
|
|
|
.iova = entry->iova,
|
|
|
|
.translated_addr = entry->translated_addr,
|
|
|
|
.perm = entry->perm,
|
|
|
|
.addr_mask = ~PAGE_MASK,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (entry->perm == IOMMU_NONE) {
|
|
|
|
if (!cache) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
g_hash_table_remove(iommu->iotlb, &entry->iova);
|
|
|
|
} else {
|
|
|
|
if (cache) {
|
|
|
|
if (cache->perm == entry->perm &&
|
|
|
|
cache->translated_addr == entry->translated_addr) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
notify.perm = IOMMU_NONE;
|
2018-06-15 21:57:16 +08:00
|
|
|
memory_region_notify_iommu(&iommu->iommu_mr, 0, notify);
|
2018-02-05 15:22:57 +08:00
|
|
|
notify.perm = entry->perm;
|
|
|
|
}
|
|
|
|
|
|
|
|
cache = g_new(S390IOTLBEntry, 1);
|
|
|
|
cache->iova = entry->iova;
|
|
|
|
cache->translated_addr = entry->translated_addr;
|
|
|
|
cache->len = PAGE_SIZE;
|
|
|
|
cache->perm = entry->perm;
|
|
|
|
g_hash_table_replace(iommu->iotlb, &cache->iova, cache);
|
|
|
|
}
|
|
|
|
|
2018-06-15 21:57:16 +08:00
|
|
|
memory_region_notify_iommu(&iommu->iommu_mr, 0, notify);
|
2018-02-05 15:22:57 +08:00
|
|
|
}
|
|
|
|
|
2017-12-01 00:27:33 +08:00
|
|
|
int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
|
2015-01-09 16:04:39 +08:00
|
|
|
{
|
|
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
uint32_t fh;
|
2018-02-05 15:22:56 +08:00
|
|
|
uint16_t error = 0;
|
2015-01-09 16:04:39 +08:00
|
|
|
S390PCIBusDevice *pbdev;
|
2016-12-08 13:02:24 +08:00
|
|
|
S390PCIIOMMU *iommu;
|
2018-02-05 15:22:56 +08:00
|
|
|
S390IOTLBEntry entry;
|
2015-01-19 15:15:56 +08:00
|
|
|
hwaddr start, end;
|
2015-01-09 16:04:39 +08:00
|
|
|
|
|
|
|
if (env->psw.mask & PSW_MASK_PSTATE) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
|
2018-02-05 15:22:56 +08:00
|
|
|
return 0;
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (r2 & 0x1) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
|
2018-02-05 15:22:56 +08:00
|
|
|
return 0;
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
fh = env->regs[r1] >> 32;
|
2015-01-19 15:15:56 +08:00
|
|
|
start = env->regs[r2];
|
|
|
|
end = start + env->regs[r2 + 1];
|
2015-01-09 16:04:39 +08:00
|
|
|
|
2016-11-23 11:08:29 +08:00
|
|
|
pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
|
2016-04-19 15:03:13 +08:00
|
|
|
if (!pbdev) {
|
2015-01-09 16:04:39 +08:00
|
|
|
DPRINTF("rpcit no pci dev\n");
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
2018-02-05 15:22:56 +08:00
|
|
|
return 0;
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
|
2016-04-19 15:03:13 +08:00
|
|
|
switch (pbdev->state) {
|
|
|
|
case ZPCI_FS_RESERVED:
|
|
|
|
case ZPCI_FS_STANDBY:
|
|
|
|
case ZPCI_FS_DISABLED:
|
|
|
|
case ZPCI_FS_PERMANENT_ERROR:
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
|
|
return 0;
|
|
|
|
case ZPCI_FS_ERROR:
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER);
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-12-08 13:02:24 +08:00
|
|
|
iommu = pbdev->iommu;
|
|
|
|
if (!iommu->g_iota) {
|
2018-02-05 15:22:56 +08:00
|
|
|
error = ERR_EVENT_INVALAS;
|
|
|
|
goto err;
|
2016-04-19 15:03:13 +08:00
|
|
|
}
|
|
|
|
|
2016-12-08 13:02:24 +08:00
|
|
|
if (end < iommu->pba || start > iommu->pal) {
|
2018-02-05 15:22:56 +08:00
|
|
|
error = ERR_EVENT_OORANGE;
|
|
|
|
goto err;
|
2016-04-19 15:03:13 +08:00
|
|
|
}
|
|
|
|
|
2015-01-19 15:15:56 +08:00
|
|
|
while (start < end) {
|
2018-02-05 15:22:56 +08:00
|
|
|
error = s390_guest_io_table_walk(iommu->g_iota, start, &entry);
|
|
|
|
if (error) {
|
|
|
|
break;
|
2015-01-19 15:15:56 +08:00
|
|
|
}
|
2018-02-05 15:22:57 +08:00
|
|
|
|
2018-02-05 15:22:56 +08:00
|
|
|
start += entry.len;
|
2018-02-05 15:22:57 +08:00
|
|
|
while (entry.iova < start && entry.iova < end) {
|
|
|
|
s390_pci_update_iotlb(iommu, &entry);
|
|
|
|
entry.iova += PAGE_SIZE;
|
|
|
|
entry.translated_addr += PAGE_SIZE;
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
2018-02-05 15:22:56 +08:00
|
|
|
err:
|
|
|
|
if (error) {
|
|
|
|
pbdev->state = ZPCI_FS_ERROR;
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
|
|
s390_set_status_code(env, r1, ZPCI_PCI_ST_FUNC_IN_ERR);
|
|
|
|
s390_pci_generate_error_event(error, pbdev->fh, pbdev->fid, start, 0);
|
|
|
|
} else {
|
2019-01-09 01:37:30 +08:00
|
|
|
pbdev->fmb.counter[ZPCI_FMB_CNT_RPCIT]++;
|
2018-02-05 15:22:56 +08:00
|
|
|
setcc(cpu, ZPCI_PCI_LS_OK);
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-03-05 17:36:48 +08:00
|
|
|
int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
|
2017-12-01 00:27:33 +08:00
|
|
|
uint8_t ar, uintptr_t ra)
|
2015-01-09 16:04:39 +08:00
|
|
|
{
|
|
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
S390PCIBusDevice *pbdev;
|
|
|
|
MemoryRegion *mr;
|
2016-08-24 18:53:31 +08:00
|
|
|
MemTxResult result;
|
2017-11-30 20:55:27 +08:00
|
|
|
uint64_t offset;
|
2015-01-09 16:04:39 +08:00
|
|
|
int i;
|
|
|
|
uint32_t fh;
|
|
|
|
uint8_t pcias;
|
|
|
|
uint8_t len;
|
2015-02-13 01:09:41 +08:00
|
|
|
uint8_t buffer[128];
|
2015-01-09 16:04:39 +08:00
|
|
|
|
|
|
|
if (env->psw.mask & PSW_MASK_PSTATE) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
fh = env->regs[r1] >> 32;
|
|
|
|
pcias = (env->regs[r1] >> 16) & 0xf;
|
|
|
|
len = env->regs[r1] & 0xff;
|
2017-11-30 20:55:27 +08:00
|
|
|
offset = env->regs[r3];
|
2015-01-09 16:04:39 +08:00
|
|
|
|
2017-11-30 20:55:27 +08:00
|
|
|
if (!(fh & FH_MASK_ENABLE)) {
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-23 11:08:29 +08:00
|
|
|
pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
|
2016-04-19 15:03:13 +08:00
|
|
|
if (!pbdev) {
|
2015-01-09 16:04:39 +08:00
|
|
|
DPRINTF("pcistb no pci dev fh 0x%x\n", fh);
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-04-19 15:03:13 +08:00
|
|
|
switch (pbdev->state) {
|
|
|
|
case ZPCI_FS_PERMANENT_ERROR:
|
|
|
|
case ZPCI_FS_ERROR:
|
2015-01-09 16:04:39 +08:00
|
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
|
|
s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED);
|
|
|
|
return 0;
|
2016-04-19 15:03:13 +08:00
|
|
|
default:
|
|
|
|
break;
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
|
2017-11-30 20:55:27 +08:00
|
|
|
if (pcias > ZPCI_IO_BAR_MAX) {
|
|
|
|
DPRINTF("pcistb invalid space\n");
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
|
|
s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Verify the address, offset and length */
|
|
|
|
/* offset must be a multiple of 8 */
|
|
|
|
if (offset % 8) {
|
|
|
|
goto specification_error;
|
|
|
|
}
|
|
|
|
/* Length must be greater than 8, a multiple of 8 */
|
|
|
|
/* and not greater than maxstbl */
|
|
|
|
if ((len <= 8) || (len % 8) || (len > pbdev->maxstbl)) {
|
|
|
|
goto specification_error;
|
|
|
|
}
|
|
|
|
/* Do not cross a 4K-byte boundary */
|
|
|
|
if (((offset & 0xfff) + len) > 0x1000) {
|
|
|
|
goto specification_error;
|
|
|
|
}
|
|
|
|
/* Guest address must be double word aligned */
|
|
|
|
if (gaddr & 0x07UL) {
|
|
|
|
goto specification_error;
|
|
|
|
}
|
|
|
|
|
2015-01-09 16:04:39 +08:00
|
|
|
mr = pbdev->pdev->io_regions[pcias].memory;
|
2017-11-30 20:55:30 +08:00
|
|
|
mr = s390_get_subregion(mr, offset, len);
|
|
|
|
offset -= mr->addr;
|
|
|
|
|
2018-05-31 21:50:52 +08:00
|
|
|
if (!memory_region_access_valid(mr, offset, len, true,
|
|
|
|
MEMTXATTRS_UNSPECIFIED)) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-03-05 17:36:48 +08:00
|
|
|
if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) {
|
2017-12-01 00:27:35 +08:00
|
|
|
s390_cpu_virt_mem_handle_exc(cpu, ra);
|
2015-02-13 01:09:41 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-01-09 16:04:39 +08:00
|
|
|
for (i = 0; i < len / 8; i++) {
|
2017-11-30 20:55:27 +08:00
|
|
|
result = memory_region_dispatch_write(mr, offset + i * 8,
|
|
|
|
ldq_p(buffer + i * 8), 8,
|
|
|
|
MEMTXATTRS_UNSPECIFIED);
|
2016-08-24 18:53:31 +08:00
|
|
|
if (result != MEMTX_OK) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
|
2016-08-24 18:53:31 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
|
2019-01-09 01:37:30 +08:00
|
|
|
pbdev->fmb.counter[ZPCI_FMB_CNT_STB]++;
|
|
|
|
|
2015-01-09 16:04:39 +08:00
|
|
|
setcc(cpu, ZPCI_PCI_LS_OK);
|
|
|
|
return 0;
|
2017-11-30 20:55:27 +08:00
|
|
|
|
|
|
|
specification_error:
|
|
|
|
s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
|
|
|
|
return 0;
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
|
|
|
|
{
|
2016-01-28 13:26:43 +08:00
|
|
|
int ret, len;
|
2016-11-24 18:10:39 +08:00
|
|
|
uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data));
|
2015-01-09 16:04:39 +08:00
|
|
|
|
2016-11-24 18:10:39 +08:00
|
|
|
pbdev->routes.adapter.adapter_id = css_get_adapter_id(
|
|
|
|
CSS_IO_ADAPTER_PCI, isc);
|
2016-01-28 13:26:43 +08:00
|
|
|
pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t));
|
|
|
|
len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long);
|
|
|
|
pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len);
|
|
|
|
|
2016-04-26 19:26:32 +08:00
|
|
|
ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
|
|
|
|
if (ret) {
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator);
|
|
|
|
if (ret) {
|
|
|
|
goto out;
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
|
|
|
|
pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);
|
|
|
|
pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));
|
|
|
|
pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);
|
|
|
|
pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));
|
2016-11-24 18:10:39 +08:00
|
|
|
pbdev->isc = isc;
|
2015-01-09 16:04:39 +08:00
|
|
|
pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));
|
|
|
|
pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));
|
|
|
|
|
|
|
|
DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
|
|
|
|
return 0;
|
2016-04-26 19:26:32 +08:00
|
|
|
out:
|
|
|
|
release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
|
|
|
|
release_indicator(&pbdev->routes.adapter, pbdev->indicator);
|
|
|
|
pbdev->summary_ind = NULL;
|
|
|
|
pbdev->indicator = NULL;
|
|
|
|
return ret;
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
|
2016-04-26 14:50:16 +08:00
|
|
|
int pci_dereg_irqs(S390PCIBusDevice *pbdev)
|
2015-01-09 16:04:39 +08:00
|
|
|
{
|
2016-01-28 13:26:43 +08:00
|
|
|
release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
|
|
|
|
release_indicator(&pbdev->routes.adapter, pbdev->indicator);
|
2015-01-09 16:04:39 +08:00
|
|
|
|
2016-01-28 13:26:43 +08:00
|
|
|
pbdev->summary_ind = NULL;
|
|
|
|
pbdev->indicator = NULL;
|
2015-01-09 16:04:39 +08:00
|
|
|
pbdev->routes.adapter.summary_addr = 0;
|
|
|
|
pbdev->routes.adapter.summary_offset = 0;
|
|
|
|
pbdev->routes.adapter.ind_addr = 0;
|
|
|
|
pbdev->routes.adapter.ind_offset = 0;
|
|
|
|
pbdev->isc = 0;
|
|
|
|
pbdev->noi = 0;
|
|
|
|
pbdev->sum = 0;
|
|
|
|
|
|
|
|
DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-12-01 00:27:33 +08:00
|
|
|
static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib,
|
|
|
|
uintptr_t ra)
|
2015-01-09 16:04:39 +08:00
|
|
|
{
|
|
|
|
uint64_t pba = ldq_p(&fib.pba);
|
|
|
|
uint64_t pal = ldq_p(&fib.pal);
|
|
|
|
uint64_t g_iota = ldq_p(&fib.iota);
|
|
|
|
uint8_t dt = (g_iota >> 2) & 0x7;
|
|
|
|
uint8_t t = (g_iota >> 11) & 0x1;
|
|
|
|
|
2018-02-05 15:22:58 +08:00
|
|
|
pba &= ~0xfff;
|
|
|
|
pal |= 0xfff;
|
2015-01-09 16:04:39 +08:00
|
|
|
if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* currently we only support designation type 1 with translation */
|
|
|
|
if (!(dt == ZPCI_IOTA_RTTO && t)) {
|
|
|
|
error_report("unsupported ioat dt %d t %d", dt, t);
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2016-12-08 13:02:24 +08:00
|
|
|
iommu->pba = pba;
|
|
|
|
iommu->pal = pal;
|
|
|
|
iommu->g_iota = g_iota;
|
2015-11-04 15:50:45 +08:00
|
|
|
|
2016-12-08 13:02:24 +08:00
|
|
|
s390_pci_iommu_enable(iommu);
|
2015-11-04 15:50:45 +08:00
|
|
|
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-12-08 13:02:24 +08:00
|
|
|
void pci_dereg_ioat(S390PCIIOMMU *iommu)
|
2015-01-09 16:04:39 +08:00
|
|
|
{
|
2016-12-08 13:02:24 +08:00
|
|
|
s390_pci_iommu_disable(iommu);
|
|
|
|
iommu->pba = 0;
|
|
|
|
iommu->pal = 0;
|
|
|
|
iommu->g_iota = 0;
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
|
2019-01-09 01:37:30 +08:00
|
|
|
void fmb_timer_free(S390PCIBusDevice *pbdev)
|
|
|
|
{
|
|
|
|
if (pbdev->fmb_timer) {
|
|
|
|
timer_del(pbdev->fmb_timer);
|
|
|
|
timer_free(pbdev->fmb_timer);
|
|
|
|
pbdev->fmb_timer = NULL;
|
|
|
|
}
|
|
|
|
pbdev->fmb_addr = 0;
|
|
|
|
memset(&pbdev->fmb, 0, sizeof(ZpciFmb));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fmb_do_update(S390PCIBusDevice *pbdev, int offset, uint64_t val,
|
|
|
|
int len)
|
|
|
|
{
|
|
|
|
MemTxResult ret;
|
|
|
|
uint64_t dst = pbdev->fmb_addr + offset;
|
|
|
|
|
|
|
|
switch (len) {
|
|
|
|
case 8:
|
|
|
|
address_space_stq_be(&address_space_memory, dst, val,
|
|
|
|
MEMTXATTRS_UNSPECIFIED,
|
|
|
|
&ret);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
address_space_stl_be(&address_space_memory, dst, val,
|
|
|
|
MEMTXATTRS_UNSPECIFIED,
|
|
|
|
&ret);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
address_space_stw_be(&address_space_memory, dst, val,
|
|
|
|
MEMTXATTRS_UNSPECIFIED,
|
|
|
|
&ret);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
address_space_stb(&address_space_memory, dst, val,
|
|
|
|
MEMTXATTRS_UNSPECIFIED,
|
|
|
|
&ret);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = MEMTX_ERROR;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (ret != MEMTX_OK) {
|
|
|
|
s390_pci_generate_error_event(ERR_EVENT_FMBA, pbdev->fh, pbdev->fid,
|
|
|
|
pbdev->fmb_addr, 0);
|
|
|
|
fmb_timer_free(pbdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fmb_update(void *opaque)
|
|
|
|
{
|
|
|
|
S390PCIBusDevice *pbdev = opaque;
|
|
|
|
int64_t t = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Update U bit */
|
|
|
|
pbdev->fmb.last_update *= 2;
|
|
|
|
pbdev->fmb.last_update |= UPDATE_U_BIT;
|
|
|
|
if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update),
|
|
|
|
pbdev->fmb.last_update,
|
|
|
|
sizeof(pbdev->fmb.last_update))) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Update FMB sample count */
|
|
|
|
if (fmb_do_update(pbdev, offsetof(ZpciFmb, sample),
|
|
|
|
pbdev->fmb.sample++,
|
|
|
|
sizeof(pbdev->fmb.sample))) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Update FMB counters */
|
|
|
|
for (i = 0; i < ZPCI_FMB_CNT_MAX; i++) {
|
|
|
|
if (fmb_do_update(pbdev, offsetof(ZpciFmb, counter[i]),
|
|
|
|
pbdev->fmb.counter[i],
|
|
|
|
sizeof(pbdev->fmb.counter[0]))) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Clear U bit and update the time */
|
|
|
|
pbdev->fmb.last_update = time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
|
|
|
pbdev->fmb.last_update *= 2;
|
|
|
|
if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update),
|
|
|
|
pbdev->fmb.last_update,
|
|
|
|
sizeof(pbdev->fmb.last_update))) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
timer_mod(pbdev->fmb_timer, t + DEFAULT_MUI);
|
|
|
|
}
|
|
|
|
|
2017-12-01 00:27:33 +08:00
|
|
|
int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
|
|
|
|
uintptr_t ra)
|
2015-01-09 16:04:39 +08:00
|
|
|
{
|
|
|
|
CPUS390XState *env = &cpu->env;
|
2016-04-28 13:24:07 +08:00
|
|
|
uint8_t oc, dmaas;
|
2015-01-09 16:04:39 +08:00
|
|
|
uint32_t fh;
|
|
|
|
ZpciFib fib;
|
|
|
|
S390PCIBusDevice *pbdev;
|
|
|
|
uint64_t cc = ZPCI_PCI_LS_OK;
|
|
|
|
|
|
|
|
if (env->psw.mask & PSW_MASK_PSTATE) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
oc = env->regs[r1] & 0xff;
|
2016-04-28 13:24:07 +08:00
|
|
|
dmaas = (env->regs[r1] >> 16) & 0xff;
|
2015-01-09 16:04:39 +08:00
|
|
|
fh = env->regs[r1] >> 32;
|
|
|
|
|
|
|
|
if (fiba & 0x7) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-23 11:08:29 +08:00
|
|
|
pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
|
2016-04-19 15:03:13 +08:00
|
|
|
if (!pbdev) {
|
2015-01-09 16:04:39 +08:00
|
|
|
DPRINTF("mpcifc no pci dev fh 0x%x\n", fh);
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-04-19 15:03:13 +08:00
|
|
|
switch (pbdev->state) {
|
|
|
|
case ZPCI_FS_RESERVED:
|
|
|
|
case ZPCI_FS_STANDBY:
|
|
|
|
case ZPCI_FS_DISABLED:
|
|
|
|
case ZPCI_FS_PERMANENT_ERROR:
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2015-03-05 17:36:48 +08:00
|
|
|
if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
|
2017-12-01 00:27:35 +08:00
|
|
|
s390_cpu_virt_mem_handle_exc(cpu, ra);
|
2015-02-13 01:09:41 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
|
2016-04-28 13:24:07 +08:00
|
|
|
if (fib.fmt != 0) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
|
2016-04-28 13:24:07 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-01-09 16:04:39 +08:00
|
|
|
switch (oc) {
|
|
|
|
case ZPCI_MOD_FC_REG_INT:
|
2016-04-28 13:24:07 +08:00
|
|
|
if (pbdev->summary_ind) {
|
2015-01-09 16:04:39 +08:00
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
2016-04-28 13:24:07 +08:00
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
|
|
|
|
} else if (reg_irqs(env, pbdev, fib)) {
|
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL);
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ZPCI_MOD_FC_DEREG_INT:
|
2016-04-28 13:24:07 +08:00
|
|
|
if (!pbdev->summary_ind) {
|
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
|
|
|
|
} else {
|
|
|
|
pci_dereg_irqs(pbdev);
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
break;
|
|
|
|
case ZPCI_MOD_FC_REG_IOAT:
|
2016-04-28 13:24:07 +08:00
|
|
|
if (dmaas != 0) {
|
2015-01-09 16:04:39 +08:00
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
2016-04-28 13:24:07 +08:00
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
|
2016-12-08 13:02:24 +08:00
|
|
|
} else if (pbdev->iommu->enabled) {
|
2016-04-28 13:24:07 +08:00
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
|
2017-12-01 00:27:33 +08:00
|
|
|
} else if (reg_ioat(env, pbdev->iommu, fib, ra)) {
|
2016-04-28 13:24:07 +08:00
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ZPCI_MOD_FC_DEREG_IOAT:
|
2016-04-28 13:24:07 +08:00
|
|
|
if (dmaas != 0) {
|
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
|
2016-12-08 13:02:24 +08:00
|
|
|
} else if (!pbdev->iommu->enabled) {
|
2016-04-28 13:24:07 +08:00
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
|
|
|
|
} else {
|
2016-12-08 13:02:24 +08:00
|
|
|
pci_dereg_ioat(pbdev->iommu);
|
2016-04-28 13:24:07 +08:00
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
break;
|
|
|
|
case ZPCI_MOD_FC_REREG_IOAT:
|
2016-04-28 13:24:07 +08:00
|
|
|
if (dmaas != 0) {
|
2015-01-09 16:04:39 +08:00
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
2016-04-28 13:24:07 +08:00
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
|
2016-12-08 13:02:24 +08:00
|
|
|
} else if (!pbdev->iommu->enabled) {
|
2016-04-28 13:24:07 +08:00
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
|
|
|
|
} else {
|
2016-12-08 13:02:24 +08:00
|
|
|
pci_dereg_ioat(pbdev->iommu);
|
2017-12-01 00:27:33 +08:00
|
|
|
if (reg_ioat(env, pbdev->iommu, fib, ra)) {
|
2016-04-28 13:24:07 +08:00
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ZPCI_MOD_FC_RESET_ERROR:
|
2016-04-19 15:03:13 +08:00
|
|
|
switch (pbdev->state) {
|
|
|
|
case ZPCI_FS_BLOCKED:
|
|
|
|
case ZPCI_FS_ERROR:
|
|
|
|
pbdev->state = ZPCI_FS_ENABLED;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
break;
|
|
|
|
case ZPCI_MOD_FC_RESET_BLOCK:
|
2016-04-19 15:03:13 +08:00
|
|
|
switch (pbdev->state) {
|
|
|
|
case ZPCI_FS_ERROR:
|
|
|
|
pbdev->state = ZPCI_FS_BLOCKED;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
break;
|
2019-01-09 01:37:30 +08:00
|
|
|
case ZPCI_MOD_FC_SET_MEASURE: {
|
|
|
|
uint64_t fmb_addr = ldq_p(&fib.fmb_addr);
|
|
|
|
|
|
|
|
if (fmb_addr & FMBK_MASK) {
|
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
s390_pci_generate_error_event(ERR_EVENT_FMBPRO, pbdev->fh,
|
|
|
|
pbdev->fid, fmb_addr, 0);
|
|
|
|
fmb_timer_free(pbdev);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!fmb_addr) {
|
|
|
|
/* Stop updating FMB. */
|
|
|
|
fmb_timer_free(pbdev);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!pbdev->fmb_timer) {
|
|
|
|
pbdev->fmb_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
|
|
|
|
fmb_update, pbdev);
|
|
|
|
} else if (timer_pending(pbdev->fmb_timer)) {
|
|
|
|
/* Remove pending timer to update FMB address. */
|
|
|
|
timer_del(pbdev->fmb_timer);
|
|
|
|
}
|
|
|
|
pbdev->fmb_addr = fmb_addr;
|
|
|
|
timer_mod(pbdev->fmb_timer,
|
|
|
|
qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + DEFAULT_MUI);
|
2015-01-09 16:04:39 +08:00
|
|
|
break;
|
2019-01-09 01:37:30 +08:00
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
default:
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(&cpu->env, PGM_OPERAND, 6, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
cc = ZPCI_PCI_LS_ERR;
|
|
|
|
}
|
|
|
|
|
|
|
|
setcc(cpu, cc);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-12-01 00:27:33 +08:00
|
|
|
int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
|
|
|
|
uintptr_t ra)
|
2015-01-09 16:04:39 +08:00
|
|
|
{
|
|
|
|
CPUS390XState *env = &cpu->env;
|
2016-06-15 17:09:10 +08:00
|
|
|
uint8_t dmaas;
|
2015-01-09 16:04:39 +08:00
|
|
|
uint32_t fh;
|
|
|
|
ZpciFib fib;
|
|
|
|
S390PCIBusDevice *pbdev;
|
|
|
|
uint32_t data;
|
|
|
|
uint64_t cc = ZPCI_PCI_LS_OK;
|
|
|
|
|
|
|
|
if (env->psw.mask & PSW_MASK_PSTATE) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
fh = env->regs[r1] >> 32;
|
2016-06-15 17:09:10 +08:00
|
|
|
dmaas = (env->regs[r1] >> 16) & 0xff;
|
|
|
|
|
|
|
|
if (dmaas) {
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
|
|
s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS);
|
|
|
|
return 0;
|
|
|
|
}
|
2015-01-09 16:04:39 +08:00
|
|
|
|
|
|
|
if (fiba & 0x7) {
|
2017-12-01 00:27:33 +08:00
|
|
|
s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
|
2015-01-09 16:04:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-23 11:08:29 +08:00
|
|
|
pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX);
|
2015-01-09 16:04:39 +08:00
|
|
|
if (!pbdev) {
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
memset(&fib, 0, sizeof(fib));
|
2016-04-19 15:03:13 +08:00
|
|
|
|
|
|
|
switch (pbdev->state) {
|
|
|
|
case ZPCI_FS_RESERVED:
|
|
|
|
case ZPCI_FS_STANDBY:
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
|
|
return 0;
|
|
|
|
case ZPCI_FS_DISABLED:
|
|
|
|
if (fh & FH_MASK_ENABLE) {
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
goto out;
|
|
|
|
/* BLOCKED bit is set to one coincident with the setting of ERROR bit.
|
|
|
|
* FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */
|
|
|
|
case ZPCI_FS_ERROR:
|
|
|
|
fib.fc |= 0x20;
|
|
|
|
case ZPCI_FS_BLOCKED:
|
|
|
|
fib.fc |= 0x40;
|
|
|
|
case ZPCI_FS_ENABLED:
|
|
|
|
fib.fc |= 0x80;
|
2016-12-08 13:02:24 +08:00
|
|
|
if (pbdev->iommu->enabled) {
|
2016-04-19 15:03:13 +08:00
|
|
|
fib.fc |= 0x10;
|
|
|
|
}
|
|
|
|
if (!(fh & FH_MASK_ENABLE)) {
|
|
|
|
env->regs[r1] |= 1ULL << 63;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ZPCI_FS_PERMANENT_ERROR:
|
|
|
|
setcc(cpu, ZPCI_PCI_LS_ERR);
|
|
|
|
s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-12-08 13:02:24 +08:00
|
|
|
stq_p(&fib.pba, pbdev->iommu->pba);
|
|
|
|
stq_p(&fib.pal, pbdev->iommu->pal);
|
|
|
|
stq_p(&fib.iota, pbdev->iommu->g_iota);
|
2015-01-09 16:04:39 +08:00
|
|
|
stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
|
|
|
|
stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
|
|
|
|
stq_p(&fib.fmb_addr, pbdev->fmb_addr);
|
|
|
|
|
2015-01-21 23:50:29 +08:00
|
|
|
data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
|
|
|
|
((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
|
|
|
|
((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
|
|
|
|
stl_p(&fib.data, data);
|
2015-01-09 16:04:39 +08:00
|
|
|
|
2016-04-19 15:03:13 +08:00
|
|
|
out:
|
2015-03-05 17:36:48 +08:00
|
|
|
if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
|
2017-12-01 00:27:35 +08:00
|
|
|
s390_cpu_virt_mem_handle_exc(cpu, ra);
|
2015-02-13 01:09:41 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-01-09 16:04:39 +08:00
|
|
|
setcc(cpu, cc);
|
|
|
|
return 0;
|
|
|
|
}
|