2010-03-11 21:38:55 +08:00
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/*
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* i386 CPUID helper functions
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
|
2018-02-01 19:18:31 +08:00
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|
2016-02-23 19:58:02 +08:00
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|
#include "qemu/osdep.h"
|
2016-03-21 01:16:19 +08:00
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|
|
#include "qemu/cutils.h"
|
2010-03-11 21:38:55 +08:00
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|
|
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|
|
|
#include "cpu.h"
|
2016-03-15 20:18:37 +08:00
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|
|
#include "exec/exec-all.h"
|
2012-12-18 01:20:04 +08:00
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|
|
#include "sysemu/kvm.h"
|
2017-09-13 17:05:19 +08:00
|
|
|
#include "sysemu/hvf.h"
|
2013-01-23 04:25:09 +08:00
|
|
|
#include "sysemu/cpus.h"
|
2013-03-20 20:11:56 +08:00
|
|
|
#include "kvm_i386.h"
|
2018-03-08 20:48:58 +08:00
|
|
|
#include "sev_i386.h"
|
2010-03-11 21:38:55 +08:00
|
|
|
|
2015-03-18 01:29:20 +08:00
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|
|
#include "qemu/error-report.h"
|
2012-12-18 01:20:00 +08:00
|
|
|
#include "qemu/option.h"
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|
|
|
|
#include "qemu/config-file.h"
|
2018-02-01 19:18:31 +08:00
|
|
|
#include "qapi/error.h"
|
2018-02-27 07:13:27 +08:00
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|
|
#include "qapi/qapi-visit-misc.h"
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|
|
|
|
#include "qapi/qapi-visit-run-state.h"
|
2018-02-01 19:18:39 +08:00
|
|
|
#include "qapi/qmp/qdict.h"
|
2012-12-18 01:19:43 +08:00
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|
|
#include "qapi/qmp/qerror.h"
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|
|
|
|
#include "qapi/visitor.h"
|
2017-02-23 03:00:28 +08:00
|
|
|
#include "qom/qom-qobject.h"
|
2012-12-18 01:20:04 +08:00
|
|
|
#include "sysemu/arch_init.h"
|
2012-04-17 18:10:29 +08:00
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|
|
2012-08-31 04:28:31 +08:00
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|
|
#if defined(CONFIG_KVM)
|
2012-08-29 22:32:41 +08:00
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|
#include <linux/kvm_para.h>
|
2012-08-31 04:28:31 +08:00
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|
|
#endif
|
2012-07-23 21:22:28 +08:00
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|
|
2012-12-18 01:20:04 +08:00
|
|
|
#include "sysemu/sysemu.h"
|
2013-04-30 01:03:01 +08:00
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|
|
#include "hw/qdev-properties.h"
|
2016-05-13 01:24:26 +08:00
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|
|
#include "hw/i386/topology.h"
|
2012-10-14 04:35:39 +08:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2015-03-31 20:11:09 +08:00
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|
|
#include "exec/address-spaces.h"
|
2014-06-27 14:40:04 +08:00
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|
|
#include "hw/hw.h"
|
2013-02-06 00:06:20 +08:00
|
|
|
#include "hw/xen/xen.h"
|
|
|
|
|
#include "hw/i386/apic_internal.h"
|
2012-10-14 04:35:39 +08:00
|
|
|
#endif
|
|
|
|
|
|
2017-09-15 00:50:05 +08:00
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|
|
#include "disas/capstone.h"
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|
|
2013-08-27 23:24:37 +08:00
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|
|
/* Cache topology CPUID constants: */
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|
|
/* CPUID Leaf 2 Descriptors */
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|
|
#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
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|
|
|
|
#define CPUID_2_L1I_32KB_8WAY_64B 0x30
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|
|
|
|
#define CPUID_2_L2_2MB_8WAY_64B 0x7d
|
target-i386: present virtual L3 cache info for vcpus
Some software algorithms are based on the hardware's cache info, for example,
for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger
a resched IPI and told cpu2 to do the wakeup if they don't share low level
cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc.
The relevant linux-kernel code as bellow:
static void ttwu_queue(struct task_struct *p, int cpu)
{
struct rq *rq = cpu_rq(cpu);
......
if (... && !cpus_share_cache(smp_processor_id(), cpu)) {
......
ttwu_queue_remote(p, cpu); /* will trigger RES IPI */
return;
}
......
ttwu_do_activate(rq, p, 0); /* access target's rq directly */
......
}
In real hardware, the cpus on the same socket share L3 cache, so one won't
trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a
virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs
under some workloads even if the virtual cpus belongs to the same virtual socket.
For KVM, there will be lots of vmexit due to guest send IPIs.
The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates)
and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during
the period:
No-L3 With-L3(applied this patch)
cpu0: 363890 44582
cpu1: 373405 43109
cpu2: 340783 43797
cpu3: 333854 43409
cpu4: 327170 40038
cpu5: 325491 39922
cpu6: 319129 42391
cpu7: 306480 41035
cpu8: 161139 32188
cpu9: 164649 31024
cpu10: 149823 30398
cpu11: 149823 32455
cpu12: 164830 35143
cpu13: 172269 35805
cpu14: 179979 33898
cpu15: 194505 32754
avg: 268963.6 40129.8
The VM's topology is "1*socket 8*cores 2*threads".
After present virtual L3 cache info for VM, the amounts of RES IPIs in guest
reduce 85%.
For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause
severe performance degradation. We had tested the overall system performance if
vcpus actually run on sparate physical socket. With L3 cache, the performance
improves 7.2%~33.1%(avg:15.7%).
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-09-07 13:21:13 +08:00
|
|
|
#define CPUID_2_L3_16MB_16WAY_64B 0x4d
|
2013-08-27 23:24:37 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/* CPUID Leaf 4 constants: */
|
|
|
|
|
|
|
|
|
|
/* EAX: */
|
|
|
|
|
#define CPUID_4_TYPE_DCACHE 1
|
|
|
|
|
#define CPUID_4_TYPE_ICACHE 2
|
|
|
|
|
#define CPUID_4_TYPE_UNIFIED 3
|
|
|
|
|
|
|
|
|
|
#define CPUID_4_LEVEL(l) ((l) << 5)
|
|
|
|
|
|
|
|
|
|
#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
|
|
|
|
|
#define CPUID_4_FULLY_ASSOC (1 << 9)
|
|
|
|
|
|
|
|
|
|
/* EDX: */
|
|
|
|
|
#define CPUID_4_NO_INVD_SHARING (1 << 0)
|
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|
|
|
#define CPUID_4_INCLUSIVE (1 << 1)
|
|
|
|
|
#define CPUID_4_COMPLEX_IDX (1 << 2)
|
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|
|
|
|
|
|
|
|
#define ASSOC_FULL 0xFF
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|
|
|
|
|
|
/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
|
|
|
|
|
#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
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|
|
a == 2 ? 0x2 : \
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|
|
a == 4 ? 0x4 : \
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|
|
a == 8 ? 0x6 : \
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|
|
|
a == 16 ? 0x8 : \
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|
a == 32 ? 0xA : \
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|
a == 48 ? 0xB : \
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|
|
a == 64 ? 0xC : \
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|
|
|
a == 96 ? 0xD : \
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|
|
a == 128 ? 0xE : \
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|
|
|
a == ASSOC_FULL ? 0xF : \
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|
|
|
|
0 /* invalid value */)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Definitions of the hardcoded cache entries we expose: */
|
|
|
|
|
|
|
|
|
|
/* L1 data cache: */
|
|
|
|
|
#define L1D_LINE_SIZE 64
|
|
|
|
|
#define L1D_ASSOCIATIVITY 8
|
|
|
|
|
#define L1D_SETS 64
|
|
|
|
|
#define L1D_PARTITIONS 1
|
|
|
|
|
/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
|
|
|
|
|
#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
|
|
|
|
|
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
|
|
|
|
|
#define L1D_LINES_PER_TAG 1
|
|
|
|
|
#define L1D_SIZE_KB_AMD 64
|
|
|
|
|
#define L1D_ASSOCIATIVITY_AMD 2
|
|
|
|
|
|
|
|
|
|
/* L1 instruction cache: */
|
|
|
|
|
#define L1I_LINE_SIZE 64
|
|
|
|
|
#define L1I_ASSOCIATIVITY 8
|
|
|
|
|
#define L1I_SETS 64
|
|
|
|
|
#define L1I_PARTITIONS 1
|
|
|
|
|
/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
|
|
|
|
|
#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
|
|
|
|
|
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
|
|
|
|
|
#define L1I_LINES_PER_TAG 1
|
|
|
|
|
#define L1I_SIZE_KB_AMD 64
|
|
|
|
|
#define L1I_ASSOCIATIVITY_AMD 2
|
|
|
|
|
|
|
|
|
|
/* Level 2 unified cache: */
|
|
|
|
|
#define L2_LINE_SIZE 64
|
|
|
|
|
#define L2_ASSOCIATIVITY 16
|
|
|
|
|
#define L2_SETS 4096
|
|
|
|
|
#define L2_PARTITIONS 1
|
|
|
|
|
/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
|
|
|
|
|
/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
|
|
|
|
|
#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
|
|
|
|
|
/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
|
|
|
|
|
#define L2_LINES_PER_TAG 1
|
|
|
|
|
#define L2_SIZE_KB_AMD 512
|
|
|
|
|
|
target-i386: present virtual L3 cache info for vcpus
Some software algorithms are based on the hardware's cache info, for example,
for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger
a resched IPI and told cpu2 to do the wakeup if they don't share low level
cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc.
The relevant linux-kernel code as bellow:
static void ttwu_queue(struct task_struct *p, int cpu)
{
struct rq *rq = cpu_rq(cpu);
......
if (... && !cpus_share_cache(smp_processor_id(), cpu)) {
......
ttwu_queue_remote(p, cpu); /* will trigger RES IPI */
return;
}
......
ttwu_do_activate(rq, p, 0); /* access target's rq directly */
......
}
In real hardware, the cpus on the same socket share L3 cache, so one won't
trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a
virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs
under some workloads even if the virtual cpus belongs to the same virtual socket.
For KVM, there will be lots of vmexit due to guest send IPIs.
The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates)
and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during
the period:
No-L3 With-L3(applied this patch)
cpu0: 363890 44582
cpu1: 373405 43109
cpu2: 340783 43797
cpu3: 333854 43409
cpu4: 327170 40038
cpu5: 325491 39922
cpu6: 319129 42391
cpu7: 306480 41035
cpu8: 161139 32188
cpu9: 164649 31024
cpu10: 149823 30398
cpu11: 149823 32455
cpu12: 164830 35143
cpu13: 172269 35805
cpu14: 179979 33898
cpu15: 194505 32754
avg: 268963.6 40129.8
The VM's topology is "1*socket 8*cores 2*threads".
After present virtual L3 cache info for VM, the amounts of RES IPIs in guest
reduce 85%.
For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause
severe performance degradation. We had tested the overall system performance if
vcpus actually run on sparate physical socket. With L3 cache, the performance
improves 7.2%~33.1%(avg:15.7%).
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-09-07 13:21:13 +08:00
|
|
|
/* Level 3 unified cache: */
|
2013-08-27 23:24:37 +08:00
|
|
|
#define L3_SIZE_KB 0 /* disabled */
|
|
|
|
|
#define L3_ASSOCIATIVITY 0 /* disabled */
|
|
|
|
|
#define L3_LINES_PER_TAG 0 /* disabled */
|
|
|
|
|
#define L3_LINE_SIZE 0 /* disabled */
|
target-i386: present virtual L3 cache info for vcpus
Some software algorithms are based on the hardware's cache info, for example,
for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger
a resched IPI and told cpu2 to do the wakeup if they don't share low level
cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc.
The relevant linux-kernel code as bellow:
static void ttwu_queue(struct task_struct *p, int cpu)
{
struct rq *rq = cpu_rq(cpu);
......
if (... && !cpus_share_cache(smp_processor_id(), cpu)) {
......
ttwu_queue_remote(p, cpu); /* will trigger RES IPI */
return;
}
......
ttwu_do_activate(rq, p, 0); /* access target's rq directly */
......
}
In real hardware, the cpus on the same socket share L3 cache, so one won't
trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a
virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs
under some workloads even if the virtual cpus belongs to the same virtual socket.
For KVM, there will be lots of vmexit due to guest send IPIs.
The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates)
and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during
the period:
No-L3 With-L3(applied this patch)
cpu0: 363890 44582
cpu1: 373405 43109
cpu2: 340783 43797
cpu3: 333854 43409
cpu4: 327170 40038
cpu5: 325491 39922
cpu6: 319129 42391
cpu7: 306480 41035
cpu8: 161139 32188
cpu9: 164649 31024
cpu10: 149823 30398
cpu11: 149823 32455
cpu12: 164830 35143
cpu13: 172269 35805
cpu14: 179979 33898
cpu15: 194505 32754
avg: 268963.6 40129.8
The VM's topology is "1*socket 8*cores 2*threads".
After present virtual L3 cache info for VM, the amounts of RES IPIs in guest
reduce 85%.
For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause
severe performance degradation. We had tested the overall system performance if
vcpus actually run on sparate physical socket. With L3 cache, the performance
improves 7.2%~33.1%(avg:15.7%).
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-09-07 13:21:13 +08:00
|
|
|
#define L3_N_LINE_SIZE 64
|
|
|
|
|
#define L3_N_ASSOCIATIVITY 16
|
|
|
|
|
#define L3_N_SETS 16384
|
|
|
|
|
#define L3_N_PARTITIONS 1
|
|
|
|
|
#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
|
|
|
|
|
#define L3_N_LINES_PER_TAG 1
|
|
|
|
|
#define L3_N_SIZE_KB_AMD 16384
|
2013-08-27 23:24:37 +08:00
|
|
|
|
|
|
|
|
/* TLB definitions: */
|
|
|
|
|
|
|
|
|
|
#define L1_DTLB_2M_ASSOC 1
|
|
|
|
|
#define L1_DTLB_2M_ENTRIES 255
|
|
|
|
|
#define L1_DTLB_4K_ASSOC 1
|
|
|
|
|
#define L1_DTLB_4K_ENTRIES 255
|
|
|
|
|
|
|
|
|
|
#define L1_ITLB_2M_ASSOC 1
|
|
|
|
|
#define L1_ITLB_2M_ENTRIES 255
|
|
|
|
|
#define L1_ITLB_4K_ASSOC 1
|
|
|
|
|
#define L1_ITLB_4K_ENTRIES 255
|
|
|
|
|
|
|
|
|
|
#define L2_DTLB_2M_ASSOC 0 /* disabled */
|
|
|
|
|
#define L2_DTLB_2M_ENTRIES 0 /* disabled */
|
|
|
|
|
#define L2_DTLB_4K_ASSOC 4
|
|
|
|
|
#define L2_DTLB_4K_ENTRIES 512
|
|
|
|
|
|
|
|
|
|
#define L2_ITLB_2M_ASSOC 0 /* disabled */
|
|
|
|
|
#define L2_ITLB_2M_ENTRIES 0 /* disabled */
|
|
|
|
|
#define L2_ITLB_4K_ASSOC 4
|
|
|
|
|
#define L2_ITLB_4K_ENTRIES 512
|
|
|
|
|
|
2018-03-05 00:48:35 +08:00
|
|
|
/* CPUID Leaf 0x14 constants: */
|
|
|
|
|
#define INTEL_PT_MAX_SUBLEAF 0x1
|
|
|
|
|
/*
|
|
|
|
|
* bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
|
|
|
|
|
* MSR can be accessed;
|
|
|
|
|
* bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
|
|
|
|
|
* bit[02]: Support IP Filtering, TraceStop filtering, and preservation
|
|
|
|
|
* of Intel PT MSRs across warm reset;
|
|
|
|
|
* bit[03]: Support MTC timing packet and suppression of COFI-based packets;
|
|
|
|
|
*/
|
|
|
|
|
#define INTEL_PT_MINIMAL_EBX 0xf
|
|
|
|
|
/*
|
|
|
|
|
* bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
|
|
|
|
|
* IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
|
|
|
|
|
* accessed;
|
|
|
|
|
* bit[01]: ToPA tables can hold any number of output entries, up to the
|
|
|
|
|
* maximum allowed by the MaskOrTableOffset field of
|
|
|
|
|
* IA32_RTIT_OUTPUT_MASK_PTRS;
|
|
|
|
|
* bit[02]: Support Single-Range Output scheme;
|
|
|
|
|
*/
|
|
|
|
|
#define INTEL_PT_MINIMAL_ECX 0x7
|
2018-03-14 03:26:31 +08:00
|
|
|
/* generated packets which contain IP payloads have LIP values */
|
|
|
|
|
#define INTEL_PT_IP_LIP (1 << 31)
|
2018-03-05 00:48:35 +08:00
|
|
|
#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
|
|
|
|
|
#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
|
|
|
|
|
#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
|
|
|
|
|
#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
|
|
|
|
|
#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
|
2013-08-27 23:24:37 +08:00
|
|
|
|
2013-01-21 22:06:36 +08:00
|
|
|
static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
|
|
|
|
|
uint32_t vendor2, uint32_t vendor3)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
dst[i] = vendor1 >> (8 * i);
|
|
|
|
|
dst[i + 4] = vendor2 >> (8 * i);
|
|
|
|
|
dst[i + 8] = vendor3 >> (8 * i);
|
|
|
|
|
}
|
|
|
|
|
dst[CPUID_VENDOR_SZ] = '\0';
|
|
|
|
|
}
|
|
|
|
|
|
2014-05-01 00:48:36 +08:00
|
|
|
#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
|
|
|
|
|
#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
|
|
|
|
|
CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
|
|
|
|
|
#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
|
|
|
|
|
CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
|
|
|
|
|
CPUID_PSE36 | CPUID_FXSR)
|
|
|
|
|
#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
|
|
|
|
|
#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
|
|
|
|
|
CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
|
|
|
|
|
CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
|
|
|
|
|
CPUID_PAE | CPUID_SEP | CPUID_APIC)
|
|
|
|
|
|
|
|
|
|
#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
|
|
|
|
|
CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
|
|
|
|
|
CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
|
|
|
|
|
CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
|
2015-10-08 03:39:43 +08:00
|
|
|
CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
|
2014-05-01 00:48:36 +08:00
|
|
|
/* partly implemented:
|
|
|
|
|
CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
|
|
|
|
|
/* missing:
|
|
|
|
|
CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
|
|
|
|
|
#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
|
|
|
|
|
CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
|
2015-07-02 21:53:40 +08:00
|
|
|
CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
|
2014-05-01 00:48:36 +08:00
|
|
|
CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
|
|
|
|
|
/* missing:
|
|
|
|
|
CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
|
|
|
|
|
CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
|
|
|
|
|
CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
|
2015-07-02 21:53:40 +08:00
|
|
|
CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
|
|
|
|
|
CPUID_EXT_F16C, CPUID_EXT_RDRAND */
|
2014-05-01 00:48:36 +08:00
|
|
|
|
|
|
|
|
#ifdef TARGET_X86_64
|
|
|
|
|
#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
|
|
|
|
|
#else
|
|
|
|
|
#define TCG_EXT2_X86_64_FEATURES 0
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
|
|
|
|
|
CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
|
|
|
|
|
CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
|
|
|
|
|
TCG_EXT2_X86_64_FEATURES)
|
|
|
|
|
#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
|
|
|
|
|
CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
|
|
|
|
|
#define TCG_EXT4_FEATURES 0
|
|
|
|
|
#define TCG_SVM_FEATURES 0
|
|
|
|
|
#define TCG_KVM_FEATURES 0
|
|
|
|
|
#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
|
2015-10-29 15:31:39 +08:00
|
|
|
CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
|
|
|
|
|
CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
|
2016-06-17 23:47:13 +08:00
|
|
|
CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
|
|
|
|
|
CPUID_7_0_EBX_ERMS)
|
2014-05-01 00:48:36 +08:00
|
|
|
/* missing:
|
2015-11-18 19:55:47 +08:00
|
|
|
CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
|
2016-06-17 23:47:13 +08:00
|
|
|
CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
|
2014-05-01 00:48:36 +08:00
|
|
|
CPUID_7_0_EBX_RDSEED */
|
2016-12-15 08:13:05 +08:00
|
|
|
#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
|
|
|
|
|
CPUID_7_0_ECX_LA57)
|
2016-10-31 16:27:26 +08:00
|
|
|
#define TCG_7_0_EDX_FEATURES 0
|
2014-05-01 00:48:45 +08:00
|
|
|
#define TCG_APM_FEATURES 0
|
2015-06-07 17:15:08 +08:00
|
|
|
#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
|
2015-07-02 22:21:23 +08:00
|
|
|
#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
|
|
|
|
|
/* missing:
|
|
|
|
|
CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
|
2014-05-01 00:48:36 +08:00
|
|
|
|
2013-01-08 02:20:45 +08:00
|
|
|
typedef struct FeatureWordInfo {
|
2016-05-12 22:24:04 +08:00
|
|
|
/* feature flags names are taken from "Intel Processor Identification and
|
|
|
|
|
* the CPUID Instruction" and AMD's "CPUID Specification".
|
|
|
|
|
* In cases of disagreement between feature naming conventions,
|
|
|
|
|
* aliases may be added.
|
|
|
|
|
*/
|
|
|
|
|
const char *feat_names[32];
|
2013-04-23 03:00:16 +08:00
|
|
|
uint32_t cpuid_eax; /* Input EAX for CPUID */
|
|
|
|
|
bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
|
|
|
|
|
uint32_t cpuid_ecx; /* Input ECX value for CPUID */
|
|
|
|
|
int cpuid_reg; /* output register (R_* constant) */
|
2014-05-01 00:48:38 +08:00
|
|
|
uint32_t tcg_features; /* Feature flags supported by TCG */
|
2014-05-01 00:48:41 +08:00
|
|
|
uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
|
2016-09-28 23:00:29 +08:00
|
|
|
uint32_t migratable_flags; /* Feature flags known to be migratable */
|
2013-01-08 02:20:45 +08:00
|
|
|
} FeatureWordInfo;
|
|
|
|
|
|
|
|
|
|
static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
2013-01-08 02:20:46 +08:00
|
|
|
[FEAT_1_EDX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
|
|
|
|
"fpu", "vme", "de", "pse",
|
|
|
|
|
"tsc", "msr", "pae", "mce",
|
|
|
|
|
"cx8", "apic", NULL, "sep",
|
|
|
|
|
"mtrr", "pge", "mca", "cmov",
|
|
|
|
|
"pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
|
|
|
|
|
NULL, "ds" /* Intel dts */, "acpi", "mmx",
|
|
|
|
|
"fxsr", "sse", "sse2", "ss",
|
|
|
|
|
"ht" /* Intel htt */, "tm", "ia64", "pbe",
|
|
|
|
|
},
|
2013-01-08 02:20:46 +08:00
|
|
|
.cpuid_eax = 1, .cpuid_reg = R_EDX,
|
2014-05-01 00:48:38 +08:00
|
|
|
.tcg_features = TCG_FEATURES,
|
2013-01-08 02:20:46 +08:00
|
|
|
},
|
|
|
|
|
[FEAT_1_ECX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
2016-10-01 02:49:41 +08:00
|
|
|
"pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
|
2016-10-01 02:49:40 +08:00
|
|
|
"ds-cpl", "vmx", "smx", "est",
|
2016-05-12 22:24:04 +08:00
|
|
|
"tm2", "ssse3", "cid", NULL,
|
|
|
|
|
"fma", "cx16", "xtpr", "pdcm",
|
2016-10-01 02:49:41 +08:00
|
|
|
NULL, "pcid", "dca", "sse4.1",
|
|
|
|
|
"sse4.2", "x2apic", "movbe", "popcnt",
|
2016-05-12 22:24:04 +08:00
|
|
|
"tsc-deadline", "aes", "xsave", "osxsave",
|
|
|
|
|
"avx", "f16c", "rdrand", "hypervisor",
|
|
|
|
|
},
|
2013-01-08 02:20:46 +08:00
|
|
|
.cpuid_eax = 1, .cpuid_reg = R_ECX,
|
2014-05-01 00:48:38 +08:00
|
|
|
.tcg_features = TCG_EXT_FEATURES,
|
2013-01-08 02:20:46 +08:00
|
|
|
},
|
2016-05-12 22:24:04 +08:00
|
|
|
/* Feature names that are already defined on feature_name[] but
|
|
|
|
|
* are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
|
|
|
|
|
* names on feat_names below. They are copied automatically
|
|
|
|
|
* to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
|
|
|
|
|
*/
|
2013-01-08 02:20:46 +08:00
|
|
|
[FEAT_8000_0001_EDX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
|
|
|
|
NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
|
|
|
|
|
NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
|
|
|
|
|
NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
|
|
|
|
|
NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
|
|
|
|
|
NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
|
2016-10-01 02:49:41 +08:00
|
|
|
"nx", NULL, "mmxext", NULL /* mmx */,
|
|
|
|
|
NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
|
|
|
|
|
NULL, "lm", "3dnowext", "3dnow",
|
2016-05-12 22:24:04 +08:00
|
|
|
},
|
2013-01-08 02:20:46 +08:00
|
|
|
.cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
|
2014-05-01 00:48:38 +08:00
|
|
|
.tcg_features = TCG_EXT2_FEATURES,
|
2013-01-08 02:20:46 +08:00
|
|
|
},
|
|
|
|
|
[FEAT_8000_0001_ECX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
2016-10-01 02:49:40 +08:00
|
|
|
"lahf-lm", "cmp-legacy", "svm", "extapic",
|
2016-05-12 22:24:04 +08:00
|
|
|
"cr8legacy", "abm", "sse4a", "misalignsse",
|
|
|
|
|
"3dnowprefetch", "osvw", "ibs", "xop",
|
|
|
|
|
"skinit", "wdt", NULL, "lwp",
|
2016-10-01 02:49:40 +08:00
|
|
|
"fma4", "tce", NULL, "nodeid-msr",
|
|
|
|
|
NULL, "tbm", "topoext", "perfctr-core",
|
|
|
|
|
"perfctr-nb", NULL, NULL, NULL,
|
2016-05-12 22:24:04 +08:00
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
2013-01-08 02:20:46 +08:00
|
|
|
.cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
|
2014-05-01 00:48:38 +08:00
|
|
|
.tcg_features = TCG_EXT3_FEATURES,
|
2013-01-08 02:20:46 +08:00
|
|
|
},
|
2013-01-08 02:20:47 +08:00
|
|
|
[FEAT_C000_0001_EDX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
|
|
|
|
NULL, NULL, "xstore", "xstore-en",
|
|
|
|
|
NULL, NULL, "xcrypt", "xcrypt-en",
|
|
|
|
|
"ace2", "ace2-en", "phe", "phe-en",
|
|
|
|
|
"pmm", "pmm-en", NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
2013-01-08 02:20:47 +08:00
|
|
|
.cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
|
2014-05-01 00:48:38 +08:00
|
|
|
.tcg_features = TCG_EXT4_FEATURES,
|
2013-01-08 02:20:47 +08:00
|
|
|
},
|
2013-01-08 02:20:46 +08:00
|
|
|
[FEAT_KVM] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
2016-10-01 02:49:40 +08:00
|
|
|
"kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
|
|
|
|
|
"kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
|
2017-11-10 15:45:47 +08:00
|
|
|
NULL, "kvm-pv-tlb-flush", NULL, NULL,
|
2016-05-12 22:24:04 +08:00
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
"kvmclock-stable-bit", NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
2013-01-08 02:20:46 +08:00
|
|
|
.cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
|
2014-05-01 00:48:38 +08:00
|
|
|
.tcg_features = TCG_KVM_FEATURES,
|
2013-01-08 02:20:46 +08:00
|
|
|
},
|
2018-02-09 22:15:25 +08:00
|
|
|
[FEAT_KVM_HINTS] = {
|
|
|
|
|
.feat_names = {
|
|
|
|
|
"kvm-hint-dedicated", NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
|
|
|
|
.cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EDX,
|
|
|
|
|
.tcg_features = TCG_KVM_FEATURES,
|
|
|
|
|
},
|
2016-06-24 18:49:36 +08:00
|
|
|
[FEAT_HYPERV_EAX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
|
|
|
|
NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
|
|
|
|
|
NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
|
|
|
|
|
NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
|
|
|
|
|
NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
|
|
|
|
|
NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
|
|
|
|
|
NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
2016-06-24 18:49:36 +08:00
|
|
|
.cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
|
|
|
|
|
},
|
|
|
|
|
[FEAT_HYPERV_EBX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
|
|
|
|
NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
|
|
|
|
|
NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
|
|
|
|
|
NULL /* hv_post_messages */, NULL /* hv_signal_events */,
|
|
|
|
|
NULL /* hv_create_port */, NULL /* hv_connect_port */,
|
|
|
|
|
NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
|
|
|
|
|
NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
|
|
|
|
|
NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
2016-06-24 18:49:36 +08:00
|
|
|
.cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
|
|
|
|
|
},
|
|
|
|
|
[FEAT_HYPERV_EDX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
|
|
|
|
NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
|
|
|
|
|
NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
|
|
|
|
|
NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
|
|
|
|
|
NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
2016-06-24 18:49:36 +08:00
|
|
|
.cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
|
|
|
|
|
},
|
2013-01-08 02:20:46 +08:00
|
|
|
[FEAT_SVM] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
2016-10-01 02:49:40 +08:00
|
|
|
"npt", "lbrv", "svm-lock", "nrip-save",
|
|
|
|
|
"tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
|
|
|
|
|
NULL, NULL, "pause-filter", NULL,
|
2016-05-12 22:24:04 +08:00
|
|
|
"pfthreshold", NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
2013-01-08 02:20:46 +08:00
|
|
|
.cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
|
2014-05-01 00:48:38 +08:00
|
|
|
.tcg_features = TCG_SVM_FEATURES,
|
2013-01-08 02:20:46 +08:00
|
|
|
},
|
|
|
|
|
[FEAT_7_0_EBX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
2016-10-01 02:49:40 +08:00
|
|
|
"fsgsbase", "tsc-adjust", NULL, "bmi1",
|
2016-05-12 22:24:04 +08:00
|
|
|
"hle", "avx2", NULL, "smep",
|
|
|
|
|
"bmi2", "erms", "invpcid", "rtm",
|
|
|
|
|
NULL, NULL, "mpx", NULL,
|
|
|
|
|
"avx512f", "avx512dq", "rdseed", "adx",
|
|
|
|
|
"smap", "avx512ifma", "pcommit", "clflushopt",
|
2018-03-05 00:48:35 +08:00
|
|
|
"clwb", "intel-pt", "avx512pf", "avx512er",
|
2016-12-14 10:50:03 +08:00
|
|
|
"avx512cd", "sha-ni", "avx512bw", "avx512vl",
|
2016-05-12 22:24:04 +08:00
|
|
|
},
|
2013-04-23 03:00:16 +08:00
|
|
|
.cpuid_eax = 7,
|
|
|
|
|
.cpuid_needs_ecx = true, .cpuid_ecx = 0,
|
|
|
|
|
.cpuid_reg = R_EBX,
|
2014-05-01 00:48:38 +08:00
|
|
|
.tcg_features = TCG_7_0_EBX_FEATURES,
|
2013-01-08 02:20:46 +08:00
|
|
|
},
|
2015-11-18 10:20:15 +08:00
|
|
|
[FEAT_7_0_ECX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
|
|
|
|
NULL, "avx512vbmi", "umip", "pku",
|
2017-11-22 15:27:56 +08:00
|
|
|
"ospke", NULL, "avx512vbmi2", NULL,
|
|
|
|
|
"gfni", "vaes", "vpclmulqdq", "avx512vnni",
|
|
|
|
|
"avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
|
2016-12-15 08:13:05 +08:00
|
|
|
"la57", NULL, NULL, NULL,
|
2016-05-12 22:24:04 +08:00
|
|
|
NULL, NULL, "rdpid", NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
2015-11-18 10:20:15 +08:00
|
|
|
.cpuid_eax = 7,
|
|
|
|
|
.cpuid_needs_ecx = true, .cpuid_ecx = 0,
|
|
|
|
|
.cpuid_reg = R_ECX,
|
|
|
|
|
.tcg_features = TCG_7_0_ECX_FEATURES,
|
|
|
|
|
},
|
2016-10-31 16:27:26 +08:00
|
|
|
[FEAT_7_0_EDX] = {
|
|
|
|
|
.feat_names = {
|
|
|
|
|
NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
2018-01-09 23:45:15 +08:00
|
|
|
NULL, NULL, "spec-ctrl", NULL,
|
2016-10-31 16:27:26 +08:00
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
|
|
|
|
.cpuid_eax = 7,
|
|
|
|
|
.cpuid_needs_ecx = true, .cpuid_ecx = 0,
|
|
|
|
|
.cpuid_reg = R_EDX,
|
|
|
|
|
.tcg_features = TCG_7_0_EDX_FEATURES,
|
|
|
|
|
},
|
2014-05-01 00:48:45 +08:00
|
|
|
[FEAT_8000_0007_EDX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
"invtsc", NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
2014-05-01 00:48:45 +08:00
|
|
|
.cpuid_eax = 0x80000007,
|
|
|
|
|
.cpuid_reg = R_EDX,
|
|
|
|
|
.tcg_features = TCG_APM_FEATURES,
|
|
|
|
|
.unmigratable_flags = CPUID_APM_INVTSC,
|
|
|
|
|
},
|
2018-01-09 23:45:16 +08:00
|
|
|
[FEAT_8000_0008_EBX] = {
|
|
|
|
|
.feat_names = {
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
"ibpb", NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
|
|
|
|
.cpuid_eax = 0x80000008,
|
|
|
|
|
.cpuid_reg = R_EBX,
|
|
|
|
|
.tcg_features = 0,
|
|
|
|
|
.unmigratable_flags = 0,
|
|
|
|
|
},
|
2014-11-24 22:54:43 +08:00
|
|
|
[FEAT_XSAVE] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
|
|
|
|
"xsaveopt", "xsavec", "xgetbv1", "xsaves",
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
2014-11-24 22:54:43 +08:00
|
|
|
.cpuid_eax = 0xd,
|
|
|
|
|
.cpuid_needs_ecx = true, .cpuid_ecx = 1,
|
|
|
|
|
.cpuid_reg = R_EAX,
|
2015-07-02 22:21:23 +08:00
|
|
|
.tcg_features = TCG_XSAVE_FEATURES,
|
2014-11-24 22:54:43 +08:00
|
|
|
},
|
2015-06-07 17:15:08 +08:00
|
|
|
[FEAT_6_EAX] = {
|
2016-05-12 22:24:04 +08:00
|
|
|
.feat_names = {
|
|
|
|
|
NULL, NULL, "arat", NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
NULL, NULL, NULL, NULL,
|
|
|
|
|
},
|
2015-06-07 17:15:08 +08:00
|
|
|
.cpuid_eax = 6, .cpuid_reg = R_EAX,
|
|
|
|
|
.tcg_features = TCG_6_EAX_FEATURES,
|
|
|
|
|
},
|
2016-09-23 04:41:35 +08:00
|
|
|
[FEAT_XSAVE_COMP_LO] = {
|
|
|
|
|
.cpuid_eax = 0xD,
|
|
|
|
|
.cpuid_needs_ecx = true, .cpuid_ecx = 0,
|
|
|
|
|
.cpuid_reg = R_EAX,
|
|
|
|
|
.tcg_features = ~0U,
|
2016-09-28 23:00:29 +08:00
|
|
|
.migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
|
|
|
|
|
XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
|
|
|
|
|
XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
|
|
|
|
|
XSTATE_PKRU_MASK,
|
2016-09-23 04:41:35 +08:00
|
|
|
},
|
|
|
|
|
[FEAT_XSAVE_COMP_HI] = {
|
|
|
|
|
.cpuid_eax = 0xD,
|
|
|
|
|
.cpuid_needs_ecx = true, .cpuid_ecx = 0,
|
|
|
|
|
.cpuid_reg = R_EDX,
|
|
|
|
|
.tcg_features = ~0U,
|
|
|
|
|
},
|
2013-01-08 02:20:45 +08:00
|
|
|
};
|
|
|
|
|
|
2013-05-07 00:20:07 +08:00
|
|
|
typedef struct X86RegisterInfo32 {
|
|
|
|
|
/* Name of register */
|
|
|
|
|
const char *name;
|
|
|
|
|
/* QAPI enum value register */
|
|
|
|
|
X86CPURegister32 qapi_enum;
|
|
|
|
|
} X86RegisterInfo32;
|
|
|
|
|
|
|
|
|
|
#define REGISTER(reg) \
|
2014-03-05 10:44:40 +08:00
|
|
|
[R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
|
2014-03-16 22:03:41 +08:00
|
|
|
static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
|
2013-05-07 00:20:07 +08:00
|
|
|
REGISTER(EAX),
|
|
|
|
|
REGISTER(ECX),
|
|
|
|
|
REGISTER(EDX),
|
|
|
|
|
REGISTER(EBX),
|
|
|
|
|
REGISTER(ESP),
|
|
|
|
|
REGISTER(EBP),
|
|
|
|
|
REGISTER(ESI),
|
|
|
|
|
REGISTER(EDI),
|
|
|
|
|
};
|
|
|
|
|
#undef REGISTER
|
|
|
|
|
|
2016-07-07 04:35:00 +08:00
|
|
|
typedef struct ExtSaveArea {
|
|
|
|
|
uint32_t feature, bits;
|
|
|
|
|
uint32_t offset, size;
|
|
|
|
|
} ExtSaveArea;
|
|
|
|
|
|
|
|
|
|
static const ExtSaveArea x86_ext_save_areas[] = {
|
2016-10-01 02:49:42 +08:00
|
|
|
[XSTATE_FP_BIT] = {
|
|
|
|
|
/* x87 FP state component is always enabled if XSAVE is supported */
|
|
|
|
|
.feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
|
|
|
|
|
/* x87 state is in the legacy region of the XSAVE area */
|
|
|
|
|
.offset = 0,
|
|
|
|
|
.size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
|
|
|
|
|
},
|
|
|
|
|
[XSTATE_SSE_BIT] = {
|
|
|
|
|
/* SSE state component is always enabled if XSAVE is supported */
|
|
|
|
|
.feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
|
|
|
|
|
/* SSE state is in the legacy region of the XSAVE area */
|
|
|
|
|
.offset = 0,
|
|
|
|
|
.size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
|
|
|
|
|
},
|
2016-02-17 17:54:53 +08:00
|
|
|
[XSTATE_YMM_BIT] =
|
|
|
|
|
{ .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
|
2015-11-29 00:32:26 +08:00
|
|
|
.offset = offsetof(X86XSaveArea, avx_state),
|
|
|
|
|
.size = sizeof(XSaveAVX) },
|
2016-02-17 17:54:53 +08:00
|
|
|
[XSTATE_BNDREGS_BIT] =
|
|
|
|
|
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
|
2015-11-29 00:32:26 +08:00
|
|
|
.offset = offsetof(X86XSaveArea, bndreg_state),
|
|
|
|
|
.size = sizeof(XSaveBNDREG) },
|
2016-02-17 17:54:53 +08:00
|
|
|
[XSTATE_BNDCSR_BIT] =
|
|
|
|
|
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
|
2015-11-29 00:32:26 +08:00
|
|
|
.offset = offsetof(X86XSaveArea, bndcsr_state),
|
|
|
|
|
.size = sizeof(XSaveBNDCSR) },
|
2016-02-17 17:54:53 +08:00
|
|
|
[XSTATE_OPMASK_BIT] =
|
|
|
|
|
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
|
2015-11-29 00:32:26 +08:00
|
|
|
.offset = offsetof(X86XSaveArea, opmask_state),
|
|
|
|
|
.size = sizeof(XSaveOpmask) },
|
2016-02-17 17:54:53 +08:00
|
|
|
[XSTATE_ZMM_Hi256_BIT] =
|
|
|
|
|
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
|
2015-11-29 00:32:26 +08:00
|
|
|
.offset = offsetof(X86XSaveArea, zmm_hi256_state),
|
|
|
|
|
.size = sizeof(XSaveZMM_Hi256) },
|
2016-02-17 17:54:53 +08:00
|
|
|
[XSTATE_Hi16_ZMM_BIT] =
|
|
|
|
|
{ .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
|
2015-11-29 00:32:26 +08:00
|
|
|
.offset = offsetof(X86XSaveArea, hi16_zmm_state),
|
|
|
|
|
.size = sizeof(XSaveHi16_ZMM) },
|
2016-02-17 17:54:53 +08:00
|
|
|
[XSTATE_PKRU_BIT] =
|
|
|
|
|
{ .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
|
2015-11-29 00:32:26 +08:00
|
|
|
.offset = offsetof(X86XSaveArea, pkru_state),
|
|
|
|
|
.size = sizeof(XSavePKRU) },
|
2013-10-02 23:54:57 +08:00
|
|
|
};
|
2013-05-07 00:20:07 +08:00
|
|
|
|
2016-09-23 04:14:07 +08:00
|
|
|
static uint32_t xsave_area_size(uint64_t mask)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
2016-10-01 02:49:42 +08:00
|
|
|
uint64_t ret = 0;
|
2016-09-23 04:14:07 +08:00
|
|
|
|
2016-10-01 02:49:42 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
|
2016-09-23 04:14:07 +08:00
|
|
|
const ExtSaveArea *esa = &x86_ext_save_areas[i];
|
|
|
|
|
if ((mask >> i) & 1) {
|
|
|
|
|
ret = MAX(ret, esa->offset + esa->size);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2017-09-13 17:05:19 +08:00
|
|
|
static inline bool accel_uses_host_cpuid(void)
|
|
|
|
|
{
|
|
|
|
|
return kvm_enabled() || hvf_enabled();
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-23 04:41:35 +08:00
|
|
|
static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
|
|
|
|
|
{
|
|
|
|
|
return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
|
|
|
|
|
cpu->env.features[FEAT_XSAVE_COMP_LO];
|
|
|
|
|
}
|
|
|
|
|
|
2013-01-05 06:01:06 +08:00
|
|
|
const char *get_register_name_32(unsigned int reg)
|
|
|
|
|
{
|
2013-06-04 00:23:27 +08:00
|
|
|
if (reg >= CPU_NB_REGS32) {
|
2013-01-05 06:01:06 +08:00
|
|
|
return NULL;
|
|
|
|
|
}
|
2013-05-07 00:20:07 +08:00
|
|
|
return x86_reg_info_32[reg].name;
|
2013-01-05 06:01:06 +08:00
|
|
|
}
|
|
|
|
|
|
2014-05-01 00:48:41 +08:00
|
|
|
/*
|
|
|
|
|
* Returns the set of feature flags that are supported and migratable by
|
|
|
|
|
* QEMU, for a given FeatureWord.
|
|
|
|
|
*/
|
|
|
|
|
static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
|
|
|
|
|
{
|
|
|
|
|
FeatureWordInfo *wi = &feature_word_info[w];
|
|
|
|
|
uint32_t r = 0;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
|
uint32_t f = 1U << i;
|
2016-09-28 23:00:29 +08:00
|
|
|
|
|
|
|
|
/* If the feature name is known, it is implicitly considered migratable,
|
|
|
|
|
* unless it is explicitly set in unmigratable_flags */
|
|
|
|
|
if ((wi->migratable_flags & f) ||
|
|
|
|
|
(wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
|
|
|
|
|
r |= f;
|
2014-05-01 00:48:41 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
2011-01-22 04:48:07 +08:00
|
|
|
void host_cpuid(uint32_t function, uint32_t count,
|
|
|
|
|
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
|
2010-03-11 21:38:58 +08:00
|
|
|
{
|
2011-11-28 01:13:01 +08:00
|
|
|
uint32_t vec[4];
|
|
|
|
|
|
|
|
|
|
#ifdef __x86_64__
|
|
|
|
|
asm volatile("cpuid"
|
|
|
|
|
: "=a"(vec[0]), "=b"(vec[1]),
|
|
|
|
|
"=c"(vec[2]), "=d"(vec[3])
|
|
|
|
|
: "0"(function), "c"(count) : "cc");
|
2014-01-31 03:48:53 +08:00
|
|
|
#elif defined(__i386__)
|
2011-11-28 01:13:01 +08:00
|
|
|
asm volatile("pusha \n\t"
|
|
|
|
|
"cpuid \n\t"
|
|
|
|
|
"mov %%eax, 0(%2) \n\t"
|
|
|
|
|
"mov %%ebx, 4(%2) \n\t"
|
|
|
|
|
"mov %%ecx, 8(%2) \n\t"
|
|
|
|
|
"mov %%edx, 12(%2) \n\t"
|
|
|
|
|
"popa"
|
|
|
|
|
: : "a"(function), "c"(count), "S"(vec)
|
|
|
|
|
: "memory", "cc");
|
2014-01-31 03:48:53 +08:00
|
|
|
#else
|
|
|
|
|
abort();
|
2011-11-28 01:13:01 +08:00
|
|
|
#endif
|
|
|
|
|
|
2010-03-11 21:38:58 +08:00
|
|
|
if (eax)
|
2011-11-28 01:13:01 +08:00
|
|
|
*eax = vec[0];
|
2010-03-11 21:38:58 +08:00
|
|
|
if (ebx)
|
2011-11-28 01:13:01 +08:00
|
|
|
*ebx = vec[1];
|
2010-03-11 21:38:58 +08:00
|
|
|
if (ecx)
|
2011-11-28 01:13:01 +08:00
|
|
|
*ecx = vec[2];
|
2010-03-11 21:38:58 +08:00
|
|
|
if (edx)
|
2011-11-28 01:13:01 +08:00
|
|
|
*edx = vec[3];
|
2010-03-11 21:38:58 +08:00
|
|
|
}
|
2010-03-11 21:38:55 +08:00
|
|
|
|
2017-03-10 02:12:10 +08:00
|
|
|
void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
|
|
|
|
|
{
|
|
|
|
|
uint32_t eax, ebx, ecx, edx;
|
|
|
|
|
|
|
|
|
|
host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
|
|
|
|
|
x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
|
|
|
|
|
|
|
|
|
|
host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
|
|
|
|
|
if (family) {
|
|
|
|
|
*family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
|
|
|
|
|
}
|
|
|
|
|
if (model) {
|
|
|
|
|
*model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
|
|
|
|
|
}
|
|
|
|
|
if (stepping) {
|
|
|
|
|
*stepping = eax & 0x0F;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-02-10 18:21:30 +08:00
|
|
|
/* CPU class name definitions: */
|
|
|
|
|
|
|
|
|
|
/* Return type name for a given CPU model name
|
|
|
|
|
* Caller is responsible for freeing the returned string.
|
|
|
|
|
*/
|
|
|
|
|
static char *x86_cpu_type_name(const char *model_name)
|
|
|
|
|
{
|
|
|
|
|
return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
|
|
|
|
|
}
|
|
|
|
|
|
2014-02-11 05:02:44 +08:00
|
|
|
static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
|
|
|
|
|
{
|
2014-02-10 18:21:30 +08:00
|
|
|
ObjectClass *oc;
|
2018-02-07 22:30:57 +08:00
|
|
|
char *typename = x86_cpu_type_name(cpu_model);
|
2014-02-10 18:21:30 +08:00
|
|
|
oc = object_class_by_name(typename);
|
|
|
|
|
g_free(typename);
|
|
|
|
|
return oc;
|
2014-02-11 05:02:44 +08:00
|
|
|
}
|
|
|
|
|
|
2016-06-06 23:16:45 +08:00
|
|
|
static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
|
|
|
|
|
{
|
|
|
|
|
const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
|
|
|
|
|
assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
|
|
|
|
|
return g_strndup(class_name,
|
|
|
|
|
strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
|
|
|
|
|
}
|
|
|
|
|
|
2014-02-10 18:21:30 +08:00
|
|
|
struct X86CPUDefinition {
|
2010-03-11 21:38:55 +08:00
|
|
|
const char *name;
|
|
|
|
|
uint32_t level;
|
2013-04-23 03:00:12 +08:00
|
|
|
uint32_t xlevel;
|
2013-01-21 22:06:36 +08:00
|
|
|
/* vendor is zero-terminated, 12 character ASCII string */
|
|
|
|
|
char vendor[CPUID_VENDOR_SZ + 1];
|
2010-03-11 21:38:55 +08:00
|
|
|
int family;
|
|
|
|
|
int model;
|
|
|
|
|
int stepping;
|
2013-04-23 03:00:15 +08:00
|
|
|
FeatureWordArray features;
|
2018-01-09 23:45:13 +08:00
|
|
|
const char *model_id;
|
2014-02-10 18:21:30 +08:00
|
|
|
};
|
2010-03-11 21:38:55 +08:00
|
|
|
|
2014-01-31 03:48:58 +08:00
|
|
|
static X86CPUDefinition builtin_x86_defs[] = {
|
2010-03-11 21:38:55 +08:00
|
|
|
{
|
|
|
|
|
.name = "qemu64",
|
2015-07-10 03:07:39 +08:00
|
|
|
.level = 0xd,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_AMD,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 6,
|
2013-09-11 04:48:59 +08:00
|
|
|
.model = 6,
|
2010-03-11 21:38:55 +08:00
|
|
|
.stepping = 3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
PPRO_FEATURES |
|
2010-03-11 21:38:55 +08:00
|
|
|
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
|
|
|
|
|
CPUID_PSE36,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2015-11-04 03:24:18 +08:00
|
|
|
CPUID_EXT_SSE3 | CPUID_EXT_CX16,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2010-03-11 21:38:55 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2015-11-04 03:24:18 +08:00
|
|
|
CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
|
2010-03-11 21:38:55 +08:00
|
|
|
.xlevel = 0x8000000A,
|
2016-04-10 03:44:20 +08:00
|
|
|
.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
|
2010-03-11 21:38:55 +08:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "phenom",
|
|
|
|
|
.level = 5,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_AMD,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 16,
|
|
|
|
|
.model = 2,
|
|
|
|
|
.stepping = 3,
|
2014-10-04 03:39:49 +08:00
|
|
|
/* Missing: CPUID_HT */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
PPRO_FEATURES |
|
2010-03-11 21:38:55 +08:00
|
|
|
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
|
2014-10-04 03:39:49 +08:00
|
|
|
CPUID_PSE36 | CPUID_VME,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
|
2010-03-11 21:38:55 +08:00
|
|
|
CPUID_EXT_POPCNT,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2010-03-11 21:38:55 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
|
2010-03-13 23:43:15 +08:00
|
|
|
CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
|
2010-03-11 21:38:55 +08:00
|
|
|
/* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
|
|
|
|
|
CPUID_EXT3_CR8LEG,
|
|
|
|
|
CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
|
|
|
|
|
CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
|
2010-03-11 21:38:55 +08:00
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
|
2014-10-04 03:39:49 +08:00
|
|
|
/* Missing: CPUID_SVM_LBRV */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_SVM] =
|
2014-10-04 03:39:49 +08:00
|
|
|
CPUID_SVM_NPT,
|
2010-03-11 21:38:55 +08:00
|
|
|
.xlevel = 0x8000001A,
|
|
|
|
|
.model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "core2duo",
|
|
|
|
|
.level = 10,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 6,
|
|
|
|
|
.model = 15,
|
|
|
|
|
.stepping = 11,
|
2014-10-04 03:39:49 +08:00
|
|
|
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
PPRO_FEATURES |
|
2010-03-11 21:38:55 +08:00
|
|
|
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
|
2014-10-04 03:39:49 +08:00
|
|
|
CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
|
|
|
|
|
/* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
|
2014-10-04 03:39:50 +08:00
|
|
|
* CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
|
2014-10-04 03:39:50 +08:00
|
|
|
CPUID_EXT_CX16,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_LAHF_LM,
|
2010-03-11 21:38:55 +08:00
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "kvm64",
|
2015-07-10 03:07:39 +08:00
|
|
|
.level = 0xd,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 15,
|
|
|
|
|
.model = 6,
|
|
|
|
|
.stepping = 1,
|
2014-12-11 00:12:41 +08:00
|
|
|
/* Missing: CPUID_HT */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
PPRO_FEATURES | CPUID_VME |
|
2010-03-11 21:38:55 +08:00
|
|
|
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
|
|
|
|
|
CPUID_PSE36,
|
|
|
|
|
/* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_SSE3 | CPUID_EXT_CX16,
|
2010-03-11 21:38:55 +08:00
|
|
|
/* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2010-03-11 21:38:55 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
|
|
|
|
|
/* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
|
|
|
|
|
CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
|
|
|
|
|
CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
|
|
|
|
|
CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
0,
|
2010-03-11 21:38:55 +08:00
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Common KVM processor"
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "qemu32",
|
|
|
|
|
.level = 4,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 6,
|
2013-09-11 04:48:59 +08:00
|
|
|
.model = 6,
|
2010-03-11 21:38:55 +08:00
|
|
|
.stepping = 3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
PPRO_FEATURES,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2015-11-04 03:24:18 +08:00
|
|
|
CPUID_EXT_SSE3,
|
2010-03-11 21:39:06 +08:00
|
|
|
.xlevel = 0x80000004,
|
2016-04-10 03:44:20 +08:00
|
|
|
.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
|
2010-03-11 21:38:55 +08:00
|
|
|
},
|
2010-05-21 15:50:51 +08:00
|
|
|
{
|
|
|
|
|
.name = "kvm32",
|
|
|
|
|
.level = 5,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2010-05-21 15:50:51 +08:00
|
|
|
.family = 15,
|
|
|
|
|
.model = 6,
|
|
|
|
|
.stepping = 1,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
PPRO_FEATURES | CPUID_VME |
|
2010-05-21 15:50:51 +08:00
|
|
|
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_SSE3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
0,
|
2010-05-21 15:50:51 +08:00
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Common 32-bit KVM processor"
|
|
|
|
|
},
|
2010-03-11 21:38:55 +08:00
|
|
|
{
|
|
|
|
|
.name = "coreduo",
|
|
|
|
|
.level = 10,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 6,
|
|
|
|
|
.model = 14,
|
|
|
|
|
.stepping = 8,
|
2014-10-04 03:39:49 +08:00
|
|
|
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
PPRO_FEATURES | CPUID_VME |
|
2014-10-04 03:39:49 +08:00
|
|
|
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
|
|
|
|
|
CPUID_SS,
|
|
|
|
|
/* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
|
2014-10-04 03:39:50 +08:00
|
|
|
* CPUID_EXT_PDCM, CPUID_EXT_VMX */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2014-10-04 03:39:50 +08:00
|
|
|
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT2_NX,
|
2010-03-11 21:38:55 +08:00
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "486",
|
2010-03-11 21:39:06 +08:00
|
|
|
.level = 1,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 4,
|
2013-05-01 23:30:51 +08:00
|
|
|
.model = 8,
|
2010-03-11 21:38:55 +08:00
|
|
|
.stepping = 0,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
I486_FEATURES,
|
2010-03-11 21:38:55 +08:00
|
|
|
.xlevel = 0,
|
2018-01-09 23:45:13 +08:00
|
|
|
.model_id = "",
|
2010-03-11 21:38:55 +08:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "pentium",
|
|
|
|
|
.level = 1,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 5,
|
|
|
|
|
.model = 4,
|
|
|
|
|
.stepping = 3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
PENTIUM_FEATURES,
|
2010-03-11 21:38:55 +08:00
|
|
|
.xlevel = 0,
|
2018-01-09 23:45:13 +08:00
|
|
|
.model_id = "",
|
2010-03-11 21:38:55 +08:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "pentium2",
|
|
|
|
|
.level = 2,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 6,
|
|
|
|
|
.model = 5,
|
|
|
|
|
.stepping = 2,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
PENTIUM2_FEATURES,
|
2010-03-11 21:38:55 +08:00
|
|
|
.xlevel = 0,
|
2018-01-09 23:45:13 +08:00
|
|
|
.model_id = "",
|
2010-03-11 21:38:55 +08:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "pentium3",
|
2015-07-10 03:07:39 +08:00
|
|
|
.level = 3,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 6,
|
|
|
|
|
.model = 7,
|
|
|
|
|
.stepping = 3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
PENTIUM3_FEATURES,
|
2010-03-11 21:38:55 +08:00
|
|
|
.xlevel = 0,
|
2018-01-09 23:45:13 +08:00
|
|
|
.model_id = "",
|
2010-03-11 21:38:55 +08:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "athlon",
|
|
|
|
|
.level = 2,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_AMD,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 6,
|
|
|
|
|
.model = 2,
|
|
|
|
|
.stepping = 3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
|
2012-09-06 18:05:37 +08:00
|
|
|
CPUID_MCA,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2012-09-06 18:05:37 +08:00
|
|
|
CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
|
2010-03-11 21:38:55 +08:00
|
|
|
.xlevel = 0x80000008,
|
2016-04-10 03:44:20 +08:00
|
|
|
.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
|
2010-03-11 21:38:55 +08:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "n270",
|
2015-07-10 03:07:39 +08:00
|
|
|
.level = 10,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2010-03-11 21:38:55 +08:00
|
|
|
.family = 6,
|
|
|
|
|
.model = 28,
|
|
|
|
|
.stepping = 2,
|
2014-10-04 03:39:49 +08:00
|
|
|
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
PPRO_FEATURES |
|
2014-10-04 03:39:49 +08:00
|
|
|
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
|
|
|
|
|
CPUID_ACPI | CPUID_SS,
|
2010-03-11 21:38:55 +08:00
|
|
|
/* Some CPUs got no CPUID_SEP */
|
2014-10-04 03:39:49 +08:00
|
|
|
/* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
|
|
|
|
|
* CPUID_EXT_XTPR */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
|
2013-04-26 02:43:04 +08:00
|
|
|
CPUID_EXT_MOVBE,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2012-09-06 18:05:37 +08:00
|
|
|
CPUID_EXT2_NX,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_LAHF_LM,
|
2015-07-10 03:07:39 +08:00
|
|
|
.xlevel = 0x80000008,
|
2010-03-11 21:38:55 +08:00
|
|
|
.model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
|
|
|
|
|
},
|
2012-09-06 04:41:10 +08:00
|
|
|
{
|
|
|
|
|
.name = "Conroe",
|
2015-07-10 03:07:39 +08:00
|
|
|
.level = 10,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2012-09-06 04:41:10 +08:00
|
|
|
.family = 6,
|
2013-05-28 04:23:54 +08:00
|
|
|
.model = 15,
|
2012-09-06 04:41:10 +08:00
|
|
|
.stepping = 3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_LAHF_LM,
|
2015-07-10 03:07:39 +08:00
|
|
|
.xlevel = 0x80000008,
|
2012-09-06 04:41:10 +08:00
|
|
|
.model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Penryn",
|
2015-07-10 03:07:39 +08:00
|
|
|
.level = 10,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2012-09-06 04:41:10 +08:00
|
|
|
.family = 6,
|
2013-05-28 04:23:54 +08:00
|
|
|
.model = 23,
|
2012-09-06 04:41:10 +08:00
|
|
|
.stepping = 3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT_SSE3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_LAHF_LM,
|
2015-07-10 03:07:39 +08:00
|
|
|
.xlevel = 0x80000008,
|
2012-09-06 04:41:10 +08:00
|
|
|
.model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Nehalem",
|
2015-07-10 03:07:39 +08:00
|
|
|
.level = 11,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2012-09-06 04:41:10 +08:00
|
|
|
.family = 6,
|
2013-05-28 04:23:54 +08:00
|
|
|
.model = 26,
|
2012-09-06 04:41:10 +08:00
|
|
|
.stepping = 3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_LAHF_LM,
|
2015-07-10 03:07:39 +08:00
|
|
|
.xlevel = 0x80000008,
|
2012-09-06 04:41:10 +08:00
|
|
|
.model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
|
|
|
|
|
},
|
2018-01-09 23:45:17 +08:00
|
|
|
{
|
|
|
|
|
.name = "Nehalem-IBRS",
|
|
|
|
|
.level = 11,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 26,
|
|
|
|
|
.stepping = 3,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
|
|
|
|
|
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
|
|
|
|
|
.features[FEAT_7_0_EDX] =
|
|
|
|
|
CPUID_7_0_EDX_SPEC_CTRL,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_LAHF_LM,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
|
|
|
|
|
},
|
2012-09-06 04:41:10 +08:00
|
|
|
{
|
|
|
|
|
.name = "Westmere",
|
|
|
|
|
.level = 11,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2012-09-06 04:41:10 +08:00
|
|
|
.family = 6,
|
|
|
|
|
.model = 44,
|
|
|
|
|
.stepping = 1,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_LAHF_LM,
|
2015-06-07 17:15:08 +08:00
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
2015-07-10 03:07:39 +08:00
|
|
|
.xlevel = 0x80000008,
|
2012-09-06 04:41:10 +08:00
|
|
|
.model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
|
|
|
|
|
},
|
2018-01-09 23:45:17 +08:00
|
|
|
{
|
|
|
|
|
.name = "Westmere-IBRS",
|
|
|
|
|
.level = 11,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 44,
|
|
|
|
|
.stepping = 1,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_LAHF_LM,
|
|
|
|
|
.features[FEAT_7_0_EDX] =
|
|
|
|
|
CPUID_7_0_EDX_SPEC_CTRL,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
|
|
|
|
|
},
|
2012-09-06 04:41:10 +08:00
|
|
|
{
|
|
|
|
|
.name = "SandyBridge",
|
|
|
|
|
.level = 0xd,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
2012-09-06 04:41:10 +08:00
|
|
|
.family = 6,
|
|
|
|
|
.model = 42,
|
|
|
|
|
.stepping = 1,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
|
|
|
|
|
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
|
|
|
|
|
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
|
|
|
|
|
CPUID_EXT_SSE3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT2_SYSCALL,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_LAHF_LM,
|
2014-11-24 22:54:43 +08:00
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
2015-06-07 17:15:08 +08:00
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
2015-07-10 03:07:39 +08:00
|
|
|
.xlevel = 0x80000008,
|
2012-09-06 04:41:10 +08:00
|
|
|
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
|
|
|
|
|
},
|
2018-01-09 23:45:17 +08:00
|
|
|
{
|
|
|
|
|
.name = "SandyBridge-IBRS",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 42,
|
|
|
|
|
.stepping = 1,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
|
|
|
|
|
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
|
|
|
|
|
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
|
|
|
|
|
CPUID_EXT_SSE3,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_LAHF_LM,
|
|
|
|
|
.features[FEAT_7_0_EDX] =
|
|
|
|
|
CPUID_7_0_EDX_SPEC_CTRL,
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
|
|
|
|
|
},
|
2014-12-05 17:55:23 +08:00
|
|
|
{
|
|
|
|
|
.name = "IvyBridge",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 58,
|
|
|
|
|
.stepping = 9,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
|
|
|
|
|
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
|
|
|
|
|
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
|
|
|
|
|
CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_ERMS,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_LAHF_LM,
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
2015-06-07 17:15:08 +08:00
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
2015-07-10 03:07:39 +08:00
|
|
|
.xlevel = 0x80000008,
|
2014-12-05 17:55:23 +08:00
|
|
|
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
|
|
|
|
|
},
|
2018-01-09 23:45:17 +08:00
|
|
|
{
|
|
|
|
|
.name = "IvyBridge-IBRS",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 58,
|
|
|
|
|
.stepping = 9,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
|
|
|
|
|
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
|
|
|
|
|
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
|
|
|
|
|
CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_ERMS,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_LAHF_LM,
|
|
|
|
|
.features[FEAT_7_0_EDX] =
|
|
|
|
|
CPUID_7_0_EDX_SPEC_CTRL,
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
|
|
|
|
|
},
|
target-i386: Add Haswell CPU model
Features added to the model, in relation to SandyBridge:
fma CPUID[1].ECX[12]
pcid CPUID[1].ECX[17]
movbe CPUID[1].ECX[22]
fsgsbase CPUID[EAX=7,ECX=0].EBX[0]
bmi1 CPUID[EAX=7,ECX=0].EBX[3]
hle CPUID[EAX=7,ECX=0].EBX[4]
avx2 CPUID[EAX=7,ECX=0].EBX[5]
smep CPUID[EAX=7,ECX=0].EBX[7]
bmi2 CPUID[EAX=7,ECX=0].EBX[8]
erms CPUID[EAX=7,ECX=0].EBX[9]
invpcid CPUID[EAX=7,ECX=0].EBX[10]
rtm CPUID[EAX=7,ECX=0].EBX[11]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-11-15 02:28:54 +08:00
|
|
|
{
|
2015-03-14 02:58:09 +08:00
|
|
|
.name = "Haswell-noTSX",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 60,
|
|
|
|
|
.stepping = 1,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
|
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2015-09-28 20:00:18 +08:00
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
|
2015-03-14 02:58:09 +08:00
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
|
|
|
|
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
2015-06-07 17:15:08 +08:00
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
2015-07-10 03:07:39 +08:00
|
|
|
.xlevel = 0x80000008,
|
2015-03-14 02:58:09 +08:00
|
|
|
.model_id = "Intel Core Processor (Haswell, no TSX)",
|
2018-01-09 23:45:17 +08:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Haswell-noTSX-IBRS",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 60,
|
|
|
|
|
.stepping = 1,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
|
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
|
|
|
|
|
.features[FEAT_7_0_EDX] =
|
|
|
|
|
CPUID_7_0_EDX_SPEC_CTRL,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
|
|
|
|
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
|
|
|
|
|
},
|
|
|
|
|
{
|
target-i386: Add Haswell CPU model
Features added to the model, in relation to SandyBridge:
fma CPUID[1].ECX[12]
pcid CPUID[1].ECX[17]
movbe CPUID[1].ECX[22]
fsgsbase CPUID[EAX=7,ECX=0].EBX[0]
bmi1 CPUID[EAX=7,ECX=0].EBX[3]
hle CPUID[EAX=7,ECX=0].EBX[4]
avx2 CPUID[EAX=7,ECX=0].EBX[5]
smep CPUID[EAX=7,ECX=0].EBX[7]
bmi2 CPUID[EAX=7,ECX=0].EBX[8]
erms CPUID[EAX=7,ECX=0].EBX[9]
invpcid CPUID[EAX=7,ECX=0].EBX[10]
rtm CPUID[EAX=7,ECX=0].EBX[11]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-11-15 02:28:54 +08:00
|
|
|
.name = "Haswell",
|
|
|
|
|
.level = 0xd,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
target-i386: Add Haswell CPU model
Features added to the model, in relation to SandyBridge:
fma CPUID[1].ECX[12]
pcid CPUID[1].ECX[17]
movbe CPUID[1].ECX[22]
fsgsbase CPUID[EAX=7,ECX=0].EBX[0]
bmi1 CPUID[EAX=7,ECX=0].EBX[3]
hle CPUID[EAX=7,ECX=0].EBX[4]
avx2 CPUID[EAX=7,ECX=0].EBX[5]
smep CPUID[EAX=7,ECX=0].EBX[7]
bmi2 CPUID[EAX=7,ECX=0].EBX[8]
erms CPUID[EAX=7,ECX=0].EBX[9]
invpcid CPUID[EAX=7,ECX=0].EBX[10]
rtm CPUID[EAX=7,ECX=0].EBX[11]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-11-15 02:28:54 +08:00
|
|
|
.family = 6,
|
|
|
|
|
.model = 60,
|
2017-03-10 02:12:12 +08:00
|
|
|
.stepping = 4,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
2014-12-05 17:52:46 +08:00
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT2_SYSCALL,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2015-09-28 20:00:18 +08:00
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_7_0_EBX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
2015-03-14 02:39:43 +08:00
|
|
|
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
|
|
|
|
|
CPUID_7_0_EBX_RTM,
|
2014-11-24 22:54:43 +08:00
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
2015-06-07 17:15:08 +08:00
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
2015-07-10 03:07:39 +08:00
|
|
|
.xlevel = 0x80000008,
|
target-i386: Add Haswell CPU model
Features added to the model, in relation to SandyBridge:
fma CPUID[1].ECX[12]
pcid CPUID[1].ECX[17]
movbe CPUID[1].ECX[22]
fsgsbase CPUID[EAX=7,ECX=0].EBX[0]
bmi1 CPUID[EAX=7,ECX=0].EBX[3]
hle CPUID[EAX=7,ECX=0].EBX[4]
avx2 CPUID[EAX=7,ECX=0].EBX[5]
smep CPUID[EAX=7,ECX=0].EBX[7]
bmi2 CPUID[EAX=7,ECX=0].EBX[8]
erms CPUID[EAX=7,ECX=0].EBX[9]
invpcid CPUID[EAX=7,ECX=0].EBX[10]
rtm CPUID[EAX=7,ECX=0].EBX[11]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-11-15 02:28:54 +08:00
|
|
|
.model_id = "Intel Core Processor (Haswell)",
|
|
|
|
|
},
|
2018-01-09 23:45:17 +08:00
|
|
|
{
|
|
|
|
|
.name = "Haswell-IBRS",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 60,
|
|
|
|
|
.stepping = 4,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
|
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
|
|
|
|
|
.features[FEAT_7_0_EDX] =
|
|
|
|
|
CPUID_7_0_EDX_SPEC_CTRL,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
|
|
|
|
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
|
|
|
|
|
CPUID_7_0_EBX_RTM,
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel Core Processor (Haswell, IBRS)",
|
|
|
|
|
},
|
2015-03-14 02:58:09 +08:00
|
|
|
{
|
|
|
|
|
.name = "Broadwell-noTSX",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 61,
|
|
|
|
|
.stepping = 2,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
|
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2015-09-28 20:00:18 +08:00
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
|
2015-03-14 02:58:09 +08:00
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
|
|
|
|
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
|
|
|
|
|
CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
|
|
|
|
|
CPUID_7_0_EBX_SMAP,
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
2015-06-07 17:15:08 +08:00
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
2015-07-10 03:07:39 +08:00
|
|
|
.xlevel = 0x80000008,
|
2015-03-14 02:58:09 +08:00
|
|
|
.model_id = "Intel Core Processor (Broadwell, no TSX)",
|
|
|
|
|
},
|
2018-01-09 23:45:17 +08:00
|
|
|
{
|
|
|
|
|
.name = "Broadwell-noTSX-IBRS",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 61,
|
|
|
|
|
.stepping = 2,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
|
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
|
|
|
|
|
.features[FEAT_7_0_EDX] =
|
|
|
|
|
CPUID_7_0_EDX_SPEC_CTRL,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
|
|
|
|
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
|
|
|
|
|
CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
|
|
|
|
|
CPUID_7_0_EBX_SMAP,
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
|
|
|
|
|
},
|
2014-06-18 04:11:40 +08:00
|
|
|
{
|
|
|
|
|
.name = "Broadwell",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 61,
|
|
|
|
|
.stepping = 2,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 04:11:40 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
2014-12-05 17:52:46 +08:00
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
2014-06-18 04:11:40 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2015-09-28 20:00:18 +08:00
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
|
2014-06-18 04:11:40 +08:00
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
2015-03-14 02:39:43 +08:00
|
|
|
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
2014-06-18 04:11:40 +08:00
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
|
2015-03-14 02:39:43 +08:00
|
|
|
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
|
2014-06-18 04:11:40 +08:00
|
|
|
CPUID_7_0_EBX_SMAP,
|
2014-11-24 22:54:43 +08:00
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
2015-06-07 17:15:08 +08:00
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
2015-07-10 03:07:39 +08:00
|
|
|
.xlevel = 0x80000008,
|
2014-06-18 04:11:40 +08:00
|
|
|
.model_id = "Intel Core Processor (Broadwell)",
|
|
|
|
|
},
|
2018-01-09 23:45:17 +08:00
|
|
|
{
|
|
|
|
|
.name = "Broadwell-IBRS",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 61,
|
|
|
|
|
.stepping = 2,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
|
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
|
|
|
|
|
.features[FEAT_7_0_EDX] =
|
|
|
|
|
CPUID_7_0_EDX_SPEC_CTRL,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
|
|
|
|
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
|
|
|
|
|
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
|
|
|
|
|
CPUID_7_0_EBX_SMAP,
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel Core Processor (Broadwell, IBRS)",
|
|
|
|
|
},
|
2016-04-27 16:13:06 +08:00
|
|
|
{
|
|
|
|
|
.name = "Skylake-Client",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 94,
|
|
|
|
|
.stepping = 3,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
|
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
|
|
|
|
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
|
|
|
|
|
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
|
|
|
|
|
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
|
|
|
|
|
/* Missing: XSAVES (not supported by some Linux versions,
|
2017-06-23 23:29:09 +08:00
|
|
|
* including v4.1 to v4.12).
|
2016-04-27 16:13:06 +08:00
|
|
|
* KVM doesn't yet expose any XSAVES state save component,
|
|
|
|
|
* and the only one defined in Skylake (processor tracing)
|
|
|
|
|
* probably will block migration anyway.
|
|
|
|
|
*/
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
|
|
|
|
|
CPUID_XSAVE_XGETBV1,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel Core Processor (Skylake)",
|
|
|
|
|
},
|
2018-01-09 23:45:17 +08:00
|
|
|
{
|
|
|
|
|
.name = "Skylake-Client-IBRS",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 94,
|
|
|
|
|
.stepping = 3,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
|
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
|
|
|
|
|
.features[FEAT_7_0_EDX] =
|
|
|
|
|
CPUID_7_0_EDX_SPEC_CTRL,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
|
|
|
|
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
|
|
|
|
|
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
|
|
|
|
|
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
|
|
|
|
|
/* Missing: XSAVES (not supported by some Linux versions,
|
|
|
|
|
* including v4.1 to v4.12).
|
|
|
|
|
* KVM doesn't yet expose any XSAVES state save component,
|
|
|
|
|
* and the only one defined in Skylake (processor tracing)
|
|
|
|
|
* probably will block migration anyway.
|
|
|
|
|
*/
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
|
|
|
|
|
CPUID_XSAVE_XGETBV1,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel Core Processor (Skylake, IBRS)",
|
|
|
|
|
},
|
2017-06-21 13:29:34 +08:00
|
|
|
{
|
|
|
|
|
.name = "Skylake-Server",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 85,
|
|
|
|
|
.stepping = 4,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
|
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
|
|
|
|
|
CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
|
|
|
|
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
|
|
|
|
|
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
|
|
|
|
|
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
|
|
|
|
|
CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
|
|
|
|
|
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
|
2017-12-19 11:37:30 +08:00
|
|
|
CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
|
2017-06-21 13:29:34 +08:00
|
|
|
/* Missing: XSAVES (not supported by some Linux versions,
|
|
|
|
|
* including v4.1 to v4.12).
|
|
|
|
|
* KVM doesn't yet expose any XSAVES state save component,
|
|
|
|
|
* and the only one defined in Skylake (processor tracing)
|
|
|
|
|
* probably will block migration anyway.
|
|
|
|
|
*/
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
|
|
|
|
|
CPUID_XSAVE_XGETBV1,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel Xeon Processor (Skylake)",
|
|
|
|
|
},
|
2018-01-09 23:45:17 +08:00
|
|
|
{
|
|
|
|
|
.name = "Skylake-Server-IBRS",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_INTEL,
|
|
|
|
|
.family = 6,
|
|
|
|
|
.model = 85,
|
|
|
|
|
.stepping = 4,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
|
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
|
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
|
|
|
|
|
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
|
|
|
|
|
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
|
|
|
|
|
CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
|
|
|
|
|
.features[FEAT_7_0_EDX] =
|
|
|
|
|
CPUID_7_0_EDX_SPEC_CTRL,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
|
|
|
|
|
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
|
|
|
|
|
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
|
|
|
|
|
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
|
|
|
|
|
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
|
|
|
|
|
CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
|
|
|
|
|
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
|
|
|
|
|
CPUID_7_0_EBX_AVX512VL,
|
|
|
|
|
/* Missing: XSAVES (not supported by some Linux versions,
|
|
|
|
|
* including v4.1 to v4.12).
|
|
|
|
|
* KVM doesn't yet expose any XSAVES state save component,
|
|
|
|
|
* and the only one defined in Skylake (processor tracing)
|
|
|
|
|
* probably will block migration anyway.
|
|
|
|
|
*/
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
|
|
|
|
|
CPUID_XSAVE_XGETBV1,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "Intel Xeon Processor (Skylake, IBRS)",
|
|
|
|
|
},
|
2012-09-06 04:41:10 +08:00
|
|
|
{
|
|
|
|
|
.name = "Opteron_G1",
|
|
|
|
|
.level = 5,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_AMD,
|
2012-09-06 04:41:10 +08:00
|
|
|
.family = 15,
|
|
|
|
|
.model = 6,
|
|
|
|
|
.stepping = 1,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_SSE3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2017-01-14 03:00:57 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
|
2012-09-06 04:41:10 +08:00
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Opteron_G2",
|
|
|
|
|
.level = 5,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_AMD,
|
2012-09-06 04:41:10 +08:00
|
|
|
.family = 15,
|
|
|
|
|
.model = 6,
|
|
|
|
|
.stepping = 1,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_CX16 | CPUID_EXT_SSE3,
|
2015-11-14 03:07:13 +08:00
|
|
|
/* Missing: CPUID_EXT2_RDTSCP */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2017-01-14 03:00:57 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
|
2012-09-06 04:41:10 +08:00
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Opteron_G3",
|
|
|
|
|
.level = 5,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_AMD,
|
2016-10-03 19:50:02 +08:00
|
|
|
.family = 16,
|
|
|
|
|
.model = 2,
|
|
|
|
|
.stepping = 3,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT_SSE3,
|
2015-11-14 03:07:13 +08:00
|
|
|
/* Missing: CPUID_EXT2_RDTSCP */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2017-01-14 03:00:57 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
|
2012-09-06 04:41:10 +08:00
|
|
|
.xlevel = 0x80000008,
|
|
|
|
|
.model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.name = "Opteron_G4",
|
|
|
|
|
.level = 0xd,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_AMD,
|
2012-09-06 04:41:10 +08:00
|
|
|
.family = 21,
|
|
|
|
|
.model = 1,
|
|
|
|
|
.stepping = 2,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
|
|
|
|
|
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
|
|
|
|
|
CPUID_EXT_SSE3,
|
2015-11-14 03:07:13 +08:00
|
|
|
/* Missing: CPUID_EXT2_RDTSCP */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2017-01-14 03:00:57 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
|
|
|
|
|
CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
|
|
|
|
|
CPUID_EXT3_LAHF_LM,
|
2014-11-24 22:54:43 +08:00
|
|
|
/* no xsaveopt! */
|
2012-09-06 04:41:10 +08:00
|
|
|
.xlevel = 0x8000001A,
|
|
|
|
|
.model_id = "AMD Opteron 62xx class CPU",
|
|
|
|
|
},
|
2012-11-15 02:28:53 +08:00
|
|
|
{
|
|
|
|
|
.name = "Opteron_G5",
|
|
|
|
|
.level = 0xd,
|
2013-01-21 22:06:36 +08:00
|
|
|
.vendor = CPUID_VENDOR_AMD,
|
2012-11-15 02:28:53 +08:00
|
|
|
.family = 21,
|
|
|
|
|
.model = 2,
|
|
|
|
|
.stepping = 0,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_EDX] =
|
2014-12-11 00:12:41 +08:00
|
|
|
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
|
|
|
|
|
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
|
|
|
|
|
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
|
|
|
|
|
CPUID_DE | CPUID_FP87,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_1_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
|
|
|
|
|
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
|
|
|
|
|
CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
|
2015-11-14 03:07:13 +08:00
|
|
|
/* Missing: CPUID_EXT2_RDTSCP */
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_EDX] =
|
2017-01-14 03:00:57 +08:00
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
2013-04-23 03:00:15 +08:00
|
|
|
.features[FEAT_8000_0001_ECX] =
|
2013-04-23 03:00:14 +08:00
|
|
|
CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
|
2014-06-18 07:05:29 +08:00
|
|
|
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
|
|
|
|
|
CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
|
|
|
|
|
CPUID_EXT3_LAHF_LM,
|
2014-11-24 22:54:43 +08:00
|
|
|
/* no xsaveopt! */
|
2012-11-15 02:28:53 +08:00
|
|
|
.xlevel = 0x8000001A,
|
|
|
|
|
.model_id = "AMD Opteron 63xx class CPU",
|
|
|
|
|
},
|
target-i386/cpu: Add new EPYC CPU model
Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
The following features bits have been added/removed compare to Opteron_G5
Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha
xsaveopt, xsavec, xgetbv1, arat
Removed: xop, fma4, tbm
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Tom Lendacky <Thomas.Lendacky@amd.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20170815170051.127257-1-brijesh.singh@amd.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-08-16 01:00:51 +08:00
|
|
|
{
|
|
|
|
|
.name = "EPYC",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_AMD,
|
|
|
|
|
.family = 23,
|
|
|
|
|
.model = 1,
|
|
|
|
|
.stepping = 2,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
|
|
|
|
|
CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
|
|
|
|
|
CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
|
|
|
|
|
CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
|
|
|
|
|
CPUID_VME | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
|
|
|
|
|
CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
|
|
|
|
|
CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
|
|
|
|
|
CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
|
|
|
|
|
CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
|
|
|
|
|
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
|
|
|
|
|
CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
|
|
|
|
|
CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
|
|
|
|
|
CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
|
|
|
|
|
CPUID_7_0_EBX_SHA_NI,
|
|
|
|
|
/* Missing: XSAVES (not supported by some Linux versions,
|
|
|
|
|
* including v4.1 to v4.12).
|
|
|
|
|
* KVM doesn't yet expose any XSAVES state save component.
|
|
|
|
|
*/
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
|
|
|
|
|
CPUID_XSAVE_XGETBV1,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x8000000A,
|
|
|
|
|
.model_id = "AMD EPYC Processor",
|
|
|
|
|
},
|
2018-01-09 23:45:18 +08:00
|
|
|
{
|
|
|
|
|
.name = "EPYC-IBPB",
|
|
|
|
|
.level = 0xd,
|
|
|
|
|
.vendor = CPUID_VENDOR_AMD,
|
|
|
|
|
.family = 23,
|
|
|
|
|
.model = 1,
|
|
|
|
|
.stepping = 2,
|
|
|
|
|
.features[FEAT_1_EDX] =
|
|
|
|
|
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
|
|
|
|
|
CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
|
|
|
|
|
CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
|
|
|
|
|
CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
|
|
|
|
|
CPUID_VME | CPUID_FP87,
|
|
|
|
|
.features[FEAT_1_ECX] =
|
|
|
|
|
CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
|
|
|
|
|
CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
|
|
|
|
|
CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
|
|
|
|
|
CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
|
|
|
|
|
CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
|
|
|
|
|
.features[FEAT_8000_0001_EDX] =
|
|
|
|
|
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
|
|
|
|
|
CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
|
|
|
|
|
CPUID_EXT2_SYSCALL,
|
|
|
|
|
.features[FEAT_8000_0001_ECX] =
|
|
|
|
|
CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
|
|
|
|
|
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
|
|
|
|
|
CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
|
|
|
|
|
.features[FEAT_8000_0008_EBX] =
|
|
|
|
|
CPUID_8000_0008_EBX_IBPB,
|
|
|
|
|
.features[FEAT_7_0_EBX] =
|
|
|
|
|
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
|
|
|
|
|
CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
|
|
|
|
|
CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
|
|
|
|
|
CPUID_7_0_EBX_SHA_NI,
|
|
|
|
|
/* Missing: XSAVES (not supported by some Linux versions,
|
|
|
|
|
* including v4.1 to v4.12).
|
|
|
|
|
* KVM doesn't yet expose any XSAVES state save component.
|
|
|
|
|
*/
|
|
|
|
|
.features[FEAT_XSAVE] =
|
|
|
|
|
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
|
|
|
|
|
CPUID_XSAVE_XGETBV1,
|
|
|
|
|
.features[FEAT_6_EAX] =
|
|
|
|
|
CPUID_6_EAX_ARAT,
|
|
|
|
|
.xlevel = 0x8000000A,
|
|
|
|
|
.model_id = "AMD EPYC Processor (with IBPB)",
|
|
|
|
|
},
|
2010-03-11 21:38:55 +08:00
|
|
|
};
|
|
|
|
|
|
2015-09-11 23:40:27 +08:00
|
|
|
typedef struct PropValue {
|
|
|
|
|
const char *prop, *value;
|
|
|
|
|
} PropValue;
|
|
|
|
|
|
|
|
|
|
/* KVM-specific features that are automatically added/removed
|
|
|
|
|
* from all CPU models when KVM is enabled.
|
|
|
|
|
*/
|
|
|
|
|
static PropValue kvm_default_props[] = {
|
|
|
|
|
{ "kvmclock", "on" },
|
|
|
|
|
{ "kvm-nopiodelay", "on" },
|
|
|
|
|
{ "kvm-asyncpf", "on" },
|
|
|
|
|
{ "kvm-steal-time", "on" },
|
|
|
|
|
{ "kvm-pv-eoi", "on" },
|
|
|
|
|
{ "kvmclock-stable-bit", "on" },
|
|
|
|
|
{ "x2apic", "on" },
|
|
|
|
|
{ "acpi", "off" },
|
|
|
|
|
{ "monitor", "off" },
|
|
|
|
|
{ "svm", "off" },
|
|
|
|
|
{ NULL, NULL },
|
|
|
|
|
};
|
|
|
|
|
|
2016-10-01 02:49:37 +08:00
|
|
|
/* TCG-specific defaults that override all CPU models when using TCG
|
|
|
|
|
*/
|
|
|
|
|
static PropValue tcg_default_props[] = {
|
|
|
|
|
{ "vme", "off" },
|
|
|
|
|
{ NULL, NULL },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
2015-09-11 23:40:27 +08:00
|
|
|
void x86_cpu_change_kvm_default(const char *prop, const char *value)
|
|
|
|
|
{
|
|
|
|
|
PropValue *pv;
|
|
|
|
|
for (pv = kvm_default_props; pv->prop; pv++) {
|
|
|
|
|
if (!strcmp(pv->prop, prop)) {
|
|
|
|
|
pv->value = value;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* It is valid to call this function only for properties that
|
|
|
|
|
* are already present in the kvm_default_props table.
|
|
|
|
|
*/
|
|
|
|
|
assert(pv->prop);
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-21 04:30:12 +08:00
|
|
|
static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
|
|
|
|
|
bool migratable_only);
|
|
|
|
|
|
2016-06-22 14:56:23 +08:00
|
|
|
static bool lmce_supported(void)
|
|
|
|
|
{
|
2017-02-23 02:39:17 +08:00
|
|
|
uint64_t mce_cap = 0;
|
2016-06-22 14:56:23 +08:00
|
|
|
|
2017-02-23 02:39:17 +08:00
|
|
|
#ifdef CONFIG_KVM
|
2016-06-22 14:56:23 +08:00
|
|
|
if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
|
|
|
|
|
return false;
|
|
|
|
|
}
|
2017-02-23 02:39:17 +08:00
|
|
|
#endif
|
2016-06-22 14:56:23 +08:00
|
|
|
|
|
|
|
|
return !!(mce_cap & MCG_LMCE_P);
|
|
|
|
|
}
|
|
|
|
|
|
2017-07-13 00:20:57 +08:00
|
|
|
#define CPUID_MODEL_ID_SZ 48
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* cpu_x86_fill_model_id:
|
|
|
|
|
* Get CPUID model ID string from host CPU.
|
|
|
|
|
*
|
|
|
|
|
* @str should have at least CPUID_MODEL_ID_SZ bytes
|
|
|
|
|
*
|
|
|
|
|
* The function does NOT add a null terminator to the string
|
|
|
|
|
* automatically.
|
|
|
|
|
*/
|
2010-03-11 21:38:55 +08:00
|
|
|
static int cpu_x86_fill_model_id(char *str)
|
|
|
|
|
{
|
|
|
|
|
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
|
|
host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
|
|
|
|
|
memcpy(str + i * 16 + 0, &eax, 4);
|
|
|
|
|
memcpy(str + i * 16 + 4, &ebx, 4);
|
|
|
|
|
memcpy(str + i * 16 + 8, &ecx, 4);
|
|
|
|
|
memcpy(str + i * 16 + 12, &edx, 4);
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-23 02:39:17 +08:00
|
|
|
static Property max_x86_cpu_properties[] = {
|
2014-06-18 04:31:53 +08:00
|
|
|
DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
|
2015-09-02 22:19:11 +08:00
|
|
|
DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
|
2014-05-01 00:48:41 +08:00
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
|
};
|
|
|
|
|
|
2017-02-23 02:39:17 +08:00
|
|
|
static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
|
2010-03-11 21:38:55 +08:00
|
|
|
{
|
2014-05-01 00:48:41 +08:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2014-02-10 18:21:30 +08:00
|
|
|
X86CPUClass *xcc = X86_CPU_CLASS(oc);
|
2010-03-11 21:38:55 +08:00
|
|
|
|
2017-01-20 05:04:45 +08:00
|
|
|
xcc->ordering = 9;
|
2012-10-25 05:44:06 +08:00
|
|
|
|
2016-10-01 02:49:36 +08:00
|
|
|
xcc->model_description =
|
2017-02-23 02:39:17 +08:00
|
|
|
"Enables all features supported by the accelerator in the current host";
|
2014-02-10 18:21:30 +08:00
|
|
|
|
2017-02-23 02:39:17 +08:00
|
|
|
dc->props = max_x86_cpu_properties;
|
2014-02-10 18:21:30 +08:00
|
|
|
}
|
|
|
|
|
|
2017-02-23 02:39:19 +08:00
|
|
|
static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
|
|
|
|
|
|
2017-02-23 02:39:17 +08:00
|
|
|
static void max_x86_cpu_initfn(Object *obj)
|
2014-02-10 18:21:30 +08:00
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
KVMState *s = kvm_state;
|
|
|
|
|
|
2014-08-21 04:30:12 +08:00
|
|
|
/* We can't fill the features array here because we don't know yet if
|
|
|
|
|
* "migratable" is true or false.
|
|
|
|
|
*/
|
2017-01-20 05:04:46 +08:00
|
|
|
cpu->max_features = true;
|
2014-08-21 04:30:12 +08:00
|
|
|
|
2017-09-13 17:05:19 +08:00
|
|
|
if (accel_uses_host_cpuid()) {
|
target/i386: Don't use x86_cpu_load_def() on "max" CPU model
When commit 0bacd8b3046f ('i386: Don't set CPUClass::cpu_def on
"max" model') removed the CPUClass::cpu_def field, we kept using
the x86_cpu_load_def() helper directly in max_x86_cpu_initfn(),
emulating the previous behavior when CPUClass::cpu_def was set.
However, x86_cpu_load_def() is intended to help initialization of
CPU models from the builtin_x86_defs table, and does lots of
other steps that are not necessary for "max".
One of the things x86_cpu_load_def() do is to set the properties
listed at tcg_default_props/kvm_default_props. We must not do
that on the "max" CPU model, otherwise under KVM we will
incorrectly report all KVM features as always available, and the
"svm" feature as always unavailable. The latter caused the bug
reported at:
https://bugzilla.redhat.com/show_bug.cgi?id=1467599
("Unable to start domain: the CPU is incompatible with host CPU:
Host CPU does not provide required features: svm")
Replace x86_cpu_load_def() with simple object_property_set*()
calls. In addition to fixing the above bug, this makes the KVM
branch in max_x86_cpu_initfn() very similar to the existing TCG
branch.
For reference, the full list of steps performed by
x86_cpu_load_def() is:
* Setting min-level and min-xlevel. Already done by
max_x86_cpu_initfn().
* Setting family/model/stepping/model-id. Done by the code added
to max_x86_cpu_initfn() in this patch.
* Copying def->features. Wrong because "-cpu max" features need to
be calculated at realize time. This was not a problem in the
current code because host_cpudef.features was all zeroes.
* x86_cpu_apply_props() calls. This causes the bug above, and
shouldn't be done.
* Setting CPUID_EXT_HYPERVISOR. Not needed because it is already
reported by x86_cpu_get_supported_feature_word(), and because
"-cpu max" features need to be calculated at realize time.
* Setting CPU vendor to host CPU vendor if on KVM mode.
Redundant, because max_x86_cpu_initfn() already sets it to the
host CPU vendor.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20170712162058.10538-5-ehabkost@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-07-13 00:20:58 +08:00
|
|
|
char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
|
|
|
|
|
char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
|
|
|
|
|
int family, model, stepping;
|
2017-09-13 17:05:19 +08:00
|
|
|
X86CPUDefinition host_cpudef = { };
|
|
|
|
|
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
|
|
|
|
|
|
|
|
|
|
host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
|
|
|
|
|
x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
|
2017-02-23 02:39:19 +08:00
|
|
|
|
target/i386: Don't use x86_cpu_load_def() on "max" CPU model
When commit 0bacd8b3046f ('i386: Don't set CPUClass::cpu_def on
"max" model') removed the CPUClass::cpu_def field, we kept using
the x86_cpu_load_def() helper directly in max_x86_cpu_initfn(),
emulating the previous behavior when CPUClass::cpu_def was set.
However, x86_cpu_load_def() is intended to help initialization of
CPU models from the builtin_x86_defs table, and does lots of
other steps that are not necessary for "max".
One of the things x86_cpu_load_def() do is to set the properties
listed at tcg_default_props/kvm_default_props. We must not do
that on the "max" CPU model, otherwise under KVM we will
incorrectly report all KVM features as always available, and the
"svm" feature as always unavailable. The latter caused the bug
reported at:
https://bugzilla.redhat.com/show_bug.cgi?id=1467599
("Unable to start domain: the CPU is incompatible with host CPU:
Host CPU does not provide required features: svm")
Replace x86_cpu_load_def() with simple object_property_set*()
calls. In addition to fixing the above bug, this makes the KVM
branch in max_x86_cpu_initfn() very similar to the existing TCG
branch.
For reference, the full list of steps performed by
x86_cpu_load_def() is:
* Setting min-level and min-xlevel. Already done by
max_x86_cpu_initfn().
* Setting family/model/stepping/model-id. Done by the code added
to max_x86_cpu_initfn() in this patch.
* Copying def->features. Wrong because "-cpu max" features need to
be calculated at realize time. This was not a problem in the
current code because host_cpudef.features was all zeroes.
* x86_cpu_apply_props() calls. This causes the bug above, and
shouldn't be done.
* Setting CPUID_EXT_HYPERVISOR. Not needed because it is already
reported by x86_cpu_get_supported_feature_word(), and because
"-cpu max" features need to be calculated at realize time.
* Setting CPU vendor to host CPU vendor if on KVM mode.
Redundant, because max_x86_cpu_initfn() already sets it to the
host CPU vendor.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20170712162058.10538-5-ehabkost@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-07-13 00:20:58 +08:00
|
|
|
host_vendor_fms(vendor, &family, &model, &stepping);
|
2017-02-23 02:39:19 +08:00
|
|
|
|
target/i386: Don't use x86_cpu_load_def() on "max" CPU model
When commit 0bacd8b3046f ('i386: Don't set CPUClass::cpu_def on
"max" model') removed the CPUClass::cpu_def field, we kept using
the x86_cpu_load_def() helper directly in max_x86_cpu_initfn(),
emulating the previous behavior when CPUClass::cpu_def was set.
However, x86_cpu_load_def() is intended to help initialization of
CPU models from the builtin_x86_defs table, and does lots of
other steps that are not necessary for "max".
One of the things x86_cpu_load_def() do is to set the properties
listed at tcg_default_props/kvm_default_props. We must not do
that on the "max" CPU model, otherwise under KVM we will
incorrectly report all KVM features as always available, and the
"svm" feature as always unavailable. The latter caused the bug
reported at:
https://bugzilla.redhat.com/show_bug.cgi?id=1467599
("Unable to start domain: the CPU is incompatible with host CPU:
Host CPU does not provide required features: svm")
Replace x86_cpu_load_def() with simple object_property_set*()
calls. In addition to fixing the above bug, this makes the KVM
branch in max_x86_cpu_initfn() very similar to the existing TCG
branch.
For reference, the full list of steps performed by
x86_cpu_load_def() is:
* Setting min-level and min-xlevel. Already done by
max_x86_cpu_initfn().
* Setting family/model/stepping/model-id. Done by the code added
to max_x86_cpu_initfn() in this patch.
* Copying def->features. Wrong because "-cpu max" features need to
be calculated at realize time. This was not a problem in the
current code because host_cpudef.features was all zeroes.
* x86_cpu_apply_props() calls. This causes the bug above, and
shouldn't be done.
* Setting CPUID_EXT_HYPERVISOR. Not needed because it is already
reported by x86_cpu_get_supported_feature_word(), and because
"-cpu max" features need to be calculated at realize time.
* Setting CPU vendor to host CPU vendor if on KVM mode.
Redundant, because max_x86_cpu_initfn() already sets it to the
host CPU vendor.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20170712162058.10538-5-ehabkost@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-07-13 00:20:58 +08:00
|
|
|
cpu_x86_fill_model_id(model_id);
|
2017-02-23 02:39:19 +08:00
|
|
|
|
target/i386: Don't use x86_cpu_load_def() on "max" CPU model
When commit 0bacd8b3046f ('i386: Don't set CPUClass::cpu_def on
"max" model') removed the CPUClass::cpu_def field, we kept using
the x86_cpu_load_def() helper directly in max_x86_cpu_initfn(),
emulating the previous behavior when CPUClass::cpu_def was set.
However, x86_cpu_load_def() is intended to help initialization of
CPU models from the builtin_x86_defs table, and does lots of
other steps that are not necessary for "max".
One of the things x86_cpu_load_def() do is to set the properties
listed at tcg_default_props/kvm_default_props. We must not do
that on the "max" CPU model, otherwise under KVM we will
incorrectly report all KVM features as always available, and the
"svm" feature as always unavailable. The latter caused the bug
reported at:
https://bugzilla.redhat.com/show_bug.cgi?id=1467599
("Unable to start domain: the CPU is incompatible with host CPU:
Host CPU does not provide required features: svm")
Replace x86_cpu_load_def() with simple object_property_set*()
calls. In addition to fixing the above bug, this makes the KVM
branch in max_x86_cpu_initfn() very similar to the existing TCG
branch.
For reference, the full list of steps performed by
x86_cpu_load_def() is:
* Setting min-level and min-xlevel. Already done by
max_x86_cpu_initfn().
* Setting family/model/stepping/model-id. Done by the code added
to max_x86_cpu_initfn() in this patch.
* Copying def->features. Wrong because "-cpu max" features need to
be calculated at realize time. This was not a problem in the
current code because host_cpudef.features was all zeroes.
* x86_cpu_apply_props() calls. This causes the bug above, and
shouldn't be done.
* Setting CPUID_EXT_HYPERVISOR. Not needed because it is already
reported by x86_cpu_get_supported_feature_word(), and because
"-cpu max" features need to be calculated at realize time.
* Setting CPU vendor to host CPU vendor if on KVM mode.
Redundant, because max_x86_cpu_initfn() already sets it to the
host CPU vendor.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20170712162058.10538-5-ehabkost@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-07-13 00:20:58 +08:00
|
|
|
object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
|
|
|
|
|
object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
|
|
|
|
|
object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
|
|
|
|
|
object_property_set_int(OBJECT(cpu), stepping, "stepping",
|
|
|
|
|
&error_abort);
|
|
|
|
|
object_property_set_str(OBJECT(cpu), model_id, "model-id",
|
|
|
|
|
&error_abort);
|
2017-02-23 02:39:19 +08:00
|
|
|
|
2017-09-13 17:05:19 +08:00
|
|
|
if (kvm_enabled()) {
|
|
|
|
|
env->cpuid_min_level =
|
|
|
|
|
kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
|
|
|
|
|
env->cpuid_min_xlevel =
|
|
|
|
|
kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
|
|
|
|
|
env->cpuid_min_xlevel2 =
|
|
|
|
|
kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
|
|
|
|
|
} else {
|
|
|
|
|
env->cpuid_min_level =
|
|
|
|
|
hvf_get_supported_cpuid(0x0, 0, R_EAX);
|
|
|
|
|
env->cpuid_min_xlevel =
|
|
|
|
|
hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
|
|
|
|
|
env->cpuid_min_xlevel2 =
|
|
|
|
|
hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
|
|
|
|
|
}
|
2016-06-22 14:56:23 +08:00
|
|
|
|
|
|
|
|
if (lmce_supported()) {
|
|
|
|
|
object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
|
|
|
|
|
}
|
2017-02-23 02:39:18 +08:00
|
|
|
} else {
|
|
|
|
|
object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
|
|
|
|
|
"vendor", &error_abort);
|
|
|
|
|
object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
|
|
|
|
|
object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
|
|
|
|
|
object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
|
|
|
|
|
object_property_set_str(OBJECT(cpu),
|
|
|
|
|
"QEMU TCG CPU version " QEMU_HW_VERSION,
|
|
|
|
|
"model-id", &error_abort);
|
2016-06-10 19:42:08 +08:00
|
|
|
}
|
2014-01-21 00:41:12 +08:00
|
|
|
|
2014-02-10 18:21:30 +08:00
|
|
|
object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
|
|
|
|
|
2017-02-23 02:39:17 +08:00
|
|
|
static const TypeInfo max_x86_cpu_type_info = {
|
|
|
|
|
.name = X86_CPU_TYPE_NAME("max"),
|
|
|
|
|
.parent = TYPE_X86_CPU,
|
|
|
|
|
.instance_init = max_x86_cpu_initfn,
|
|
|
|
|
.class_init = max_x86_cpu_class_init,
|
|
|
|
|
};
|
|
|
|
|
|
2017-09-13 17:05:19 +08:00
|
|
|
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
|
2017-02-23 02:39:17 +08:00
|
|
|
static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
|
|
|
|
|
{
|
|
|
|
|
X86CPUClass *xcc = X86_CPU_CLASS(oc);
|
|
|
|
|
|
2017-09-13 17:05:19 +08:00
|
|
|
xcc->host_cpuid_required = true;
|
2017-02-23 02:39:17 +08:00
|
|
|
xcc->ordering = 8;
|
|
|
|
|
|
2017-09-13 17:05:19 +08:00
|
|
|
if (kvm_enabled()) {
|
|
|
|
|
xcc->model_description =
|
|
|
|
|
"KVM processor with all supported host features ";
|
|
|
|
|
} else if (hvf_enabled()) {
|
|
|
|
|
xcc->model_description =
|
|
|
|
|
"HVF processor with all supported host features ";
|
|
|
|
|
}
|
2017-02-23 02:39:17 +08:00
|
|
|
}
|
|
|
|
|
|
2014-02-10 18:21:30 +08:00
|
|
|
static const TypeInfo host_x86_cpu_type_info = {
|
|
|
|
|
.name = X86_CPU_TYPE_NAME("host"),
|
2017-02-23 02:39:17 +08:00
|
|
|
.parent = X86_CPU_TYPE_NAME("max"),
|
2014-02-10 18:21:30 +08:00
|
|
|
.class_init = host_x86_cpu_class_init,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
2014-05-01 00:48:31 +08:00
|
|
|
static void report_unavailable_features(FeatureWord w, uint32_t mask)
|
2010-03-11 21:38:55 +08:00
|
|
|
{
|
2014-05-01 00:48:31 +08:00
|
|
|
FeatureWordInfo *f = &feature_word_info[w];
|
2010-03-11 21:38:55 +08:00
|
|
|
int i;
|
|
|
|
|
|
2014-05-01 00:48:29 +08:00
|
|
|
for (i = 0; i < 32; ++i) {
|
2015-09-30 04:34:22 +08:00
|
|
|
if ((1UL << i) & mask) {
|
2013-01-08 02:20:46 +08:00
|
|
|
const char *reg = get_register_name_32(f->cpuid_reg);
|
2013-01-05 06:01:06 +08:00
|
|
|
assert(reg);
|
2017-09-12 03:52:53 +08:00
|
|
|
warn_report("%s doesn't support requested feature: "
|
|
|
|
|
"CPUID.%02XH:%s%s%s [bit %d]",
|
2017-09-13 17:05:19 +08:00
|
|
|
accel_uses_host_cpuid() ? "host" : "TCG",
|
2017-09-12 03:52:53 +08:00
|
|
|
f->cpuid_eax, reg,
|
|
|
|
|
f->feat_names[i] ? "." : "",
|
|
|
|
|
f->feat_names[i] ? f->feat_names[i] : "", i);
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
2014-05-01 00:48:29 +08:00
|
|
|
}
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
|
|
|
|
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
|
|
|
|
|
const char *name, void *opaque,
|
|
|
|
|
Error **errp)
|
2012-04-17 20:42:22 +08:00
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
int64_t value;
|
|
|
|
|
|
|
|
|
|
value = (env->cpuid_version >> 8) & 0xf;
|
|
|
|
|
if (value == 0xf) {
|
|
|
|
|
value += (env->cpuid_version >> 20) & 0xff;
|
|
|
|
|
}
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_int(v, name, &value, errp);
|
2012-04-17 20:42:22 +08:00
|
|
|
}
|
|
|
|
|
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
|
|
|
|
|
const char *name, void *opaque,
|
|
|
|
|
Error **errp)
|
2012-02-18 00:46:01 +08:00
|
|
|
{
|
2012-04-17 18:10:29 +08:00
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
const int64_t min = 0;
|
|
|
|
|
const int64_t max = 0xff + 0xf;
|
2014-04-25 18:44:22 +08:00
|
|
|
Error *local_err = NULL;
|
2012-04-17 18:10:29 +08:00
|
|
|
int64_t value;
|
|
|
|
|
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_int(v, name, &value, &local_err);
|
2014-04-25 18:44:22 +08:00
|
|
|
if (local_err) {
|
|
|
|
|
error_propagate(errp, local_err);
|
2012-04-17 18:10:29 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (value < min || value > max) {
|
2015-03-17 18:54:50 +08:00
|
|
|
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
|
|
|
|
name ? name : "null", value, min, max);
|
2012-04-17 18:10:29 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2012-02-18 00:46:01 +08:00
|
|
|
env->cpuid_version &= ~0xff00f00;
|
2012-04-17 18:10:29 +08:00
|
|
|
if (value > 0x0f) {
|
|
|
|
|
env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
|
2012-02-18 00:46:01 +08:00
|
|
|
} else {
|
2012-04-17 18:10:29 +08:00
|
|
|
env->cpuid_version |= value << 8;
|
2012-02-18 00:46:01 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
|
|
|
|
|
const char *name, void *opaque,
|
|
|
|
|
Error **errp)
|
2012-04-17 20:48:14 +08:00
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
int64_t value;
|
|
|
|
|
|
|
|
|
|
value = (env->cpuid_version >> 4) & 0xf;
|
|
|
|
|
value |= ((env->cpuid_version >> 16) & 0xf) << 4;
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_int(v, name, &value, errp);
|
2012-04-17 20:48:14 +08:00
|
|
|
}
|
|
|
|
|
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
|
|
|
|
|
const char *name, void *opaque,
|
|
|
|
|
Error **errp)
|
2012-02-18 00:46:02 +08:00
|
|
|
{
|
2012-04-17 18:16:39 +08:00
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
const int64_t min = 0;
|
|
|
|
|
const int64_t max = 0xff;
|
2014-04-25 18:44:22 +08:00
|
|
|
Error *local_err = NULL;
|
2012-04-17 18:16:39 +08:00
|
|
|
int64_t value;
|
|
|
|
|
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_int(v, name, &value, &local_err);
|
2014-04-25 18:44:22 +08:00
|
|
|
if (local_err) {
|
|
|
|
|
error_propagate(errp, local_err);
|
2012-04-17 18:16:39 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (value < min || value > max) {
|
2015-03-17 18:54:50 +08:00
|
|
|
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
|
|
|
|
name ? name : "null", value, min, max);
|
2012-04-17 18:16:39 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2012-02-18 00:46:02 +08:00
|
|
|
env->cpuid_version &= ~0xf00f0;
|
2012-04-17 18:16:39 +08:00
|
|
|
env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
|
2012-02-18 00:46:02 +08:00
|
|
|
}
|
|
|
|
|
|
2012-04-17 20:50:53 +08:00
|
|
|
static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
const char *name, void *opaque,
|
2012-04-17 20:50:53 +08:00
|
|
|
Error **errp)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
int64_t value;
|
|
|
|
|
|
|
|
|
|
value = env->cpuid_version & 0xf;
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_int(v, name, &value, errp);
|
2012-04-17 20:50:53 +08:00
|
|
|
}
|
|
|
|
|
|
2012-04-17 20:14:18 +08:00
|
|
|
static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
const char *name, void *opaque,
|
2012-04-17 20:14:18 +08:00
|
|
|
Error **errp)
|
2012-02-18 00:46:03 +08:00
|
|
|
{
|
2012-04-17 20:14:18 +08:00
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
const int64_t min = 0;
|
|
|
|
|
const int64_t max = 0xf;
|
2014-04-25 18:44:22 +08:00
|
|
|
Error *local_err = NULL;
|
2012-04-17 20:14:18 +08:00
|
|
|
int64_t value;
|
|
|
|
|
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_int(v, name, &value, &local_err);
|
2014-04-25 18:44:22 +08:00
|
|
|
if (local_err) {
|
|
|
|
|
error_propagate(errp, local_err);
|
2012-04-17 20:14:18 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (value < min || value > max) {
|
2015-03-17 18:54:50 +08:00
|
|
|
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
|
|
|
|
name ? name : "null", value, min, max);
|
2012-04-17 20:14:18 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2012-02-18 00:46:03 +08:00
|
|
|
env->cpuid_version &= ~0xf;
|
2012-04-17 20:14:18 +08:00
|
|
|
env->cpuid_version |= value & 0xf;
|
2012-02-18 00:46:03 +08:00
|
|
|
}
|
|
|
|
|
|
2012-04-18 01:22:58 +08:00
|
|
|
static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
char *value;
|
|
|
|
|
|
2014-12-04 21:46:46 +08:00
|
|
|
value = g_malloc(CPUID_VENDOR_SZ + 1);
|
2013-01-21 22:06:36 +08:00
|
|
|
x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
|
|
|
|
|
env->cpuid_vendor3);
|
2012-04-18 01:22:58 +08:00
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void x86_cpuid_set_vendor(Object *obj, const char *value,
|
|
|
|
|
Error **errp)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
int i;
|
|
|
|
|
|
2012-10-22 23:03:10 +08:00
|
|
|
if (strlen(value) != CPUID_VENDOR_SZ) {
|
2015-03-17 18:54:50 +08:00
|
|
|
error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
|
2012-04-18 01:22:58 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
env->cpuid_vendor1 = 0;
|
|
|
|
|
env->cpuid_vendor2 = 0;
|
|
|
|
|
env->cpuid_vendor3 = 0;
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
|
|
|
|
|
env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
|
|
|
|
|
env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-18 05:02:26 +08:00
|
|
|
static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
char *value;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
value = g_malloc(48 + 1);
|
|
|
|
|
for (i = 0; i < 48; i++) {
|
|
|
|
|
value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
|
|
|
|
|
}
|
|
|
|
|
value[48] = '\0';
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-17 21:17:27 +08:00
|
|
|
static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
|
|
|
|
|
Error **errp)
|
2012-02-18 00:46:04 +08:00
|
|
|
{
|
2012-04-17 21:17:27 +08:00
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
2012-02-18 00:46:04 +08:00
|
|
|
int c, len, i;
|
|
|
|
|
|
|
|
|
|
if (model_id == NULL) {
|
|
|
|
|
model_id = "";
|
|
|
|
|
}
|
|
|
|
|
len = strlen(model_id);
|
2012-04-18 00:21:52 +08:00
|
|
|
memset(env->cpuid_model, 0, 48);
|
2012-02-18 00:46:04 +08:00
|
|
|
for (i = 0; i < 48; i++) {
|
|
|
|
|
if (i >= len) {
|
|
|
|
|
c = '\0';
|
|
|
|
|
} else {
|
|
|
|
|
c = (uint8_t)model_id[i];
|
|
|
|
|
}
|
|
|
|
|
env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
|
|
|
|
|
void *opaque, Error **errp)
|
2012-04-18 06:12:23 +08:00
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
int64_t value;
|
|
|
|
|
|
|
|
|
|
value = cpu->env.tsc_khz * 1000;
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_int(v, name, &value, errp);
|
2012-04-18 06:12:23 +08:00
|
|
|
}
|
|
|
|
|
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
|
|
|
|
|
void *opaque, Error **errp)
|
2012-04-18 06:12:23 +08:00
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
const int64_t min = 0;
|
2012-09-22 08:13:13 +08:00
|
|
|
const int64_t max = INT64_MAX;
|
2014-04-25 18:44:22 +08:00
|
|
|
Error *local_err = NULL;
|
2012-04-18 06:12:23 +08:00
|
|
|
int64_t value;
|
|
|
|
|
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_int(v, name, &value, &local_err);
|
2014-04-25 18:44:22 +08:00
|
|
|
if (local_err) {
|
|
|
|
|
error_propagate(errp, local_err);
|
2012-04-18 06:12:23 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (value < min || value > max) {
|
2015-03-17 18:54:50 +08:00
|
|
|
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
|
|
|
|
name ? name : "null", value, min, max);
|
2012-04-18 06:12:23 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2015-11-24 11:33:57 +08:00
|
|
|
cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
|
2012-04-18 06:12:23 +08:00
|
|
|
}
|
|
|
|
|
|
2013-05-07 00:20:09 +08:00
|
|
|
/* Generic getter for "feature-words" and "filtered-features" properties */
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
|
|
|
|
|
const char *name, void *opaque,
|
|
|
|
|
Error **errp)
|
2013-05-07 00:20:07 +08:00
|
|
|
{
|
2013-05-07 00:20:09 +08:00
|
|
|
uint32_t *array = (uint32_t *)opaque;
|
2013-05-07 00:20:07 +08:00
|
|
|
FeatureWord w;
|
|
|
|
|
X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
|
|
|
|
|
X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
|
|
|
|
|
X86CPUFeatureWordInfoList *list = NULL;
|
|
|
|
|
|
|
|
|
|
for (w = 0; w < FEATURE_WORDS; w++) {
|
|
|
|
|
FeatureWordInfo *wi = &feature_word_info[w];
|
|
|
|
|
X86CPUFeatureWordInfo *qwi = &word_infos[w];
|
|
|
|
|
qwi->cpuid_input_eax = wi->cpuid_eax;
|
|
|
|
|
qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
|
|
|
|
|
qwi->cpuid_input_ecx = wi->cpuid_ecx;
|
|
|
|
|
qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
|
2013-05-07 00:20:09 +08:00
|
|
|
qwi->features = array[w];
|
2013-05-07 00:20:07 +08:00
|
|
|
|
|
|
|
|
/* List will be in reverse order, but order shouldn't matter */
|
|
|
|
|
list_entries[w].next = list;
|
|
|
|
|
list_entries[w].value = &word_infos[w];
|
|
|
|
|
list = &list_entries[w];
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-14 05:57:57 +08:00
|
|
|
visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
|
2013-05-07 00:20:07 +08:00
|
|
|
}
|
|
|
|
|
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
|
|
|
|
|
void *opaque, Error **errp)
|
2013-06-04 21:05:25 +08:00
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
int64_t value = cpu->hyperv_spinlock_attempts;
|
|
|
|
|
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_int(v, name, &value, errp);
|
2013-06-04 21:05:25 +08:00
|
|
|
}
|
|
|
|
|
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
|
|
|
|
|
void *opaque, Error **errp)
|
2013-06-04 21:05:25 +08:00
|
|
|
{
|
|
|
|
|
const int64_t min = 0xFFF;
|
|
|
|
|
const int64_t max = UINT_MAX;
|
|
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
|
|
|
|
Error *err = NULL;
|
|
|
|
|
int64_t value;
|
|
|
|
|
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_int(v, name, &value, &err);
|
2013-06-04 21:05:25 +08:00
|
|
|
if (err) {
|
|
|
|
|
error_propagate(errp, err);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (value < min || value > max) {
|
|
|
|
|
error_setg(errp, "Property %s.%s doesn't take value %" PRId64
|
2014-07-28 15:13:06 +08:00
|
|
|
" (minimum: %" PRId64 ", maximum: %" PRId64 ")",
|
|
|
|
|
object_get_typename(obj), name ? name : "null",
|
|
|
|
|
value, min, max);
|
2013-06-04 21:05:25 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
cpu->hyperv_spinlock_attempts = value;
|
|
|
|
|
}
|
|
|
|
|
|
2017-07-14 10:14:54 +08:00
|
|
|
static const PropertyInfo qdev_prop_spinlocks = {
|
2013-06-04 21:05:25 +08:00
|
|
|
.name = "int",
|
|
|
|
|
.get = x86_get_hv_spinlocks,
|
|
|
|
|
.set = x86_set_hv_spinlocks,
|
|
|
|
|
};
|
|
|
|
|
|
2013-04-27 00:04:32 +08:00
|
|
|
/* Convert all '_' in a feature string option name to '-', to make feature
|
|
|
|
|
* name conform to QOM property naming rule, which uses '-' instead of '_'.
|
|
|
|
|
*/
|
|
|
|
|
static inline void feat2prop(char *s)
|
|
|
|
|
{
|
|
|
|
|
while ((s = strchr(s, '_'))) {
|
|
|
|
|
*s = '-';
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-04 00:48:13 +08:00
|
|
|
/* Return the feature property name for a feature flag bit */
|
|
|
|
|
static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
|
|
|
|
|
{
|
|
|
|
|
/* XSAVE components are automatically enabled by other features,
|
|
|
|
|
* so return the original feature name instead
|
|
|
|
|
*/
|
|
|
|
|
if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
|
|
|
|
|
int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
|
|
|
|
|
|
|
|
|
|
if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
|
|
|
|
|
x86_ext_save_areas[comp].bits) {
|
|
|
|
|
w = x86_ext_save_areas[comp].feature;
|
|
|
|
|
bitnr = ctz32(x86_ext_save_areas[comp].bits);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
assert(bitnr < 32);
|
|
|
|
|
assert(w < FEATURE_WORDS);
|
|
|
|
|
return feature_word_info[w].feat_names[bitnr];
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-06 23:16:44 +08:00
|
|
|
/* Compatibily hack to maintain legacy +-feat semantic,
|
|
|
|
|
* where +-feat overwrites any feature set by
|
|
|
|
|
* feat=on|feat even if the later is parsed after +-feat
|
|
|
|
|
* (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
|
|
|
|
|
*/
|
2016-10-01 02:49:39 +08:00
|
|
|
static GList *plus_features, *minus_features;
|
2016-06-06 23:16:44 +08:00
|
|
|
|
2016-10-25 03:53:52 +08:00
|
|
|
static gint compare_string(gconstpointer a, gconstpointer b)
|
|
|
|
|
{
|
|
|
|
|
return g_strcmp0(a, b);
|
|
|
|
|
}
|
|
|
|
|
|
2012-12-05 03:34:39 +08:00
|
|
|
/* Parse "+feature,-feature,feature=foo" CPU feature string
|
|
|
|
|
*/
|
2016-06-10 01:11:01 +08:00
|
|
|
static void x86_cpu_parse_featurestr(const char *typename, char *features,
|
2014-03-04 06:19:19 +08:00
|
|
|
Error **errp)
|
2012-12-05 03:34:39 +08:00
|
|
|
{
|
|
|
|
|
char *featurestr; /* Single 'key=value" string being parsed */
|
2016-06-10 01:11:01 +08:00
|
|
|
static bool cpu_globals_initialized;
|
2016-10-25 03:53:52 +08:00
|
|
|
bool ambiguous = false;
|
2016-06-10 01:11:01 +08:00
|
|
|
|
|
|
|
|
if (cpu_globals_initialized) {
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
cpu_globals_initialized = true;
|
2012-12-05 03:34:39 +08:00
|
|
|
|
2016-06-10 01:10:58 +08:00
|
|
|
if (!features) {
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (featurestr = strtok(features, ",");
|
2016-11-25 23:21:53 +08:00
|
|
|
featurestr;
|
2016-06-10 01:10:58 +08:00
|
|
|
featurestr = strtok(NULL, ",")) {
|
|
|
|
|
const char *name;
|
|
|
|
|
const char *val = NULL;
|
|
|
|
|
char *eq = NULL;
|
2016-06-21 20:04:40 +08:00
|
|
|
char num[32];
|
2016-06-10 01:11:01 +08:00
|
|
|
GlobalProperty *prop;
|
2010-03-11 21:38:55 +08:00
|
|
|
|
2016-06-10 01:10:58 +08:00
|
|
|
/* Compatibility syntax: */
|
2010-03-11 21:38:55 +08:00
|
|
|
if (featurestr[0] == '+') {
|
2016-10-01 02:49:39 +08:00
|
|
|
plus_features = g_list_append(plus_features,
|
|
|
|
|
g_strdup(featurestr + 1));
|
2016-06-10 01:10:58 +08:00
|
|
|
continue;
|
2010-03-11 21:38:55 +08:00
|
|
|
} else if (featurestr[0] == '-') {
|
2016-10-01 02:49:39 +08:00
|
|
|
minus_features = g_list_append(minus_features,
|
|
|
|
|
g_strdup(featurestr + 1));
|
2016-06-10 01:10:58 +08:00
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
eq = strchr(featurestr, '=');
|
|
|
|
|
if (eq) {
|
|
|
|
|
*eq++ = 0;
|
|
|
|
|
val = eq;
|
2010-03-11 21:38:55 +08:00
|
|
|
} else {
|
2016-06-10 01:10:58 +08:00
|
|
|
val = "on";
|
2013-01-21 22:06:38 +08:00
|
|
|
}
|
2016-06-10 01:10:58 +08:00
|
|
|
|
|
|
|
|
feat2prop(featurestr);
|
|
|
|
|
name = featurestr;
|
|
|
|
|
|
2016-10-25 03:53:52 +08:00
|
|
|
if (g_list_find_custom(plus_features, name, compare_string)) {
|
2017-07-12 21:57:41 +08:00
|
|
|
warn_report("Ambiguous CPU model string. "
|
|
|
|
|
"Don't mix both \"+%s\" and \"%s=%s\"",
|
|
|
|
|
name, name, val);
|
2016-10-25 03:53:52 +08:00
|
|
|
ambiguous = true;
|
|
|
|
|
}
|
|
|
|
|
if (g_list_find_custom(minus_features, name, compare_string)) {
|
2017-07-12 21:57:41 +08:00
|
|
|
warn_report("Ambiguous CPU model string. "
|
|
|
|
|
"Don't mix both \"-%s\" and \"%s=%s\"",
|
|
|
|
|
name, name, val);
|
2016-10-25 03:53:52 +08:00
|
|
|
ambiguous = true;
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-10 01:10:58 +08:00
|
|
|
/* Special case: */
|
|
|
|
|
if (!strcmp(name, "tsc-freq")) {
|
2017-02-22 04:14:06 +08:00
|
|
|
int ret;
|
2017-02-22 04:14:07 +08:00
|
|
|
uint64_t tsc_freq;
|
2016-06-10 01:10:58 +08:00
|
|
|
|
2017-02-22 04:14:06 +08:00
|
|
|
ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
|
2017-02-22 04:14:07 +08:00
|
|
|
if (ret < 0 || tsc_freq > INT64_MAX) {
|
2016-06-10 01:10:58 +08:00
|
|
|
error_setg(errp, "bad numerical value %s", val);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
|
|
|
|
|
val = num;
|
|
|
|
|
name = "tsc-frequency";
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
2016-06-10 01:10:58 +08:00
|
|
|
|
2016-06-10 01:11:01 +08:00
|
|
|
prop = g_new0(typeof(*prop), 1);
|
|
|
|
|
prop->driver = typename;
|
|
|
|
|
prop->property = g_strdup(name);
|
|
|
|
|
prop->value = g_strdup(val);
|
|
|
|
|
prop->errp = &error_fatal;
|
|
|
|
|
qdev_prop_register_global(prop);
|
2016-06-10 01:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
2016-10-25 03:53:52 +08:00
|
|
|
if (ambiguous) {
|
2017-07-12 21:57:41 +08:00
|
|
|
warn_report("Compatibility of ambiguous CPU model "
|
|
|
|
|
"strings won't be kept on future QEMU versions");
|
2016-10-25 03:53:52 +08:00
|
|
|
}
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
|
|
|
|
|
2017-01-17 05:11:21 +08:00
|
|
|
static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
|
2016-05-04 00:48:13 +08:00
|
|
|
static int x86_cpu_filter_features(X86CPU *cpu);
|
|
|
|
|
|
|
|
|
|
/* Check for missing features that may prevent the CPU class from
|
|
|
|
|
* running using the current machine and accelerator.
|
|
|
|
|
*/
|
|
|
|
|
static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
|
|
|
|
|
strList **missing_feats)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *xc;
|
|
|
|
|
FeatureWord w;
|
|
|
|
|
Error *err = NULL;
|
|
|
|
|
strList **next = missing_feats;
|
|
|
|
|
|
2017-09-13 17:05:19 +08:00
|
|
|
if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
|
2016-05-04 00:48:13 +08:00
|
|
|
strList *new = g_new0(strList, 1);
|
2017-10-17 22:40:51 +08:00
|
|
|
new->value = g_strdup("kvm");
|
2016-05-04 00:48:13 +08:00
|
|
|
*missing_feats = new;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
|
|
|
|
|
|
2017-01-17 05:11:21 +08:00
|
|
|
x86_cpu_expand_features(xc, &err);
|
2016-05-04 00:48:13 +08:00
|
|
|
if (err) {
|
2017-01-17 05:11:21 +08:00
|
|
|
/* Errors at x86_cpu_expand_features should never happen,
|
2016-05-04 00:48:13 +08:00
|
|
|
* but in case it does, just report the model as not
|
|
|
|
|
* runnable at all using the "type" property.
|
|
|
|
|
*/
|
|
|
|
|
strList *new = g_new0(strList, 1);
|
|
|
|
|
new->value = g_strdup("type");
|
|
|
|
|
*next = new;
|
|
|
|
|
next = &new->next;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
x86_cpu_filter_features(xc);
|
|
|
|
|
|
|
|
|
|
for (w = 0; w < FEATURE_WORDS; w++) {
|
|
|
|
|
uint32_t filtered = xc->filtered_features[w];
|
|
|
|
|
int i;
|
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
|
if (filtered & (1UL << i)) {
|
|
|
|
|
strList *new = g_new0(strList, 1);
|
|
|
|
|
new->value = g_strdup(x86_cpu_feature_name(w, i));
|
|
|
|
|
*next = new;
|
|
|
|
|
next = &new->next;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
object_unref(OBJECT(xc));
|
|
|
|
|
}
|
|
|
|
|
|
2015-02-04 01:48:55 +08:00
|
|
|
/* Print all cpuid feature names in featureset
|
2010-03-11 21:38:55 +08:00
|
|
|
*/
|
2015-02-04 01:48:55 +08:00
|
|
|
static void listflags(FILE *f, fprintf_function print, const char **featureset)
|
2015-03-03 08:29:17 +08:00
|
|
|
{
|
2015-02-04 01:48:55 +08:00
|
|
|
int bit;
|
|
|
|
|
bool first = true;
|
|
|
|
|
|
|
|
|
|
for (bit = 0; bit < 32; bit++) {
|
|
|
|
|
if (featureset[bit]) {
|
|
|
|
|
print(f, "%s%s", first ? "" : " ", featureset[bit]);
|
|
|
|
|
first = false;
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
2015-02-04 01:48:55 +08:00
|
|
|
}
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
|
|
|
|
|
2017-01-20 05:04:45 +08:00
|
|
|
/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
|
2016-10-01 02:49:36 +08:00
|
|
|
static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
|
|
|
|
|
{
|
|
|
|
|
ObjectClass *class_a = (ObjectClass *)a;
|
|
|
|
|
ObjectClass *class_b = (ObjectClass *)b;
|
|
|
|
|
X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
|
|
|
|
|
X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
|
|
|
|
|
const char *name_a, *name_b;
|
|
|
|
|
|
2017-01-20 05:04:45 +08:00
|
|
|
if (cc_a->ordering != cc_b->ordering) {
|
|
|
|
|
return cc_a->ordering - cc_b->ordering;
|
2016-10-01 02:49:36 +08:00
|
|
|
} else {
|
|
|
|
|
name_a = object_class_get_name(class_a);
|
|
|
|
|
name_b = object_class_get_name(class_b);
|
|
|
|
|
return strcmp(name_a, name_b);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static GSList *get_sorted_cpu_model_list(void)
|
|
|
|
|
{
|
|
|
|
|
GSList *list = object_class_get_list(TYPE_X86_CPU, false);
|
|
|
|
|
list = g_slist_sort(list, x86_cpu_list_compare);
|
|
|
|
|
return list;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void x86_cpu_list_entry(gpointer data, gpointer user_data)
|
|
|
|
|
{
|
|
|
|
|
ObjectClass *oc = data;
|
|
|
|
|
X86CPUClass *cc = X86_CPU_CLASS(oc);
|
|
|
|
|
CPUListState *s = user_data;
|
|
|
|
|
char *name = x86_cpu_class_get_model_name(cc);
|
|
|
|
|
const char *desc = cc->model_description;
|
2017-02-23 02:39:19 +08:00
|
|
|
if (!desc && cc->cpu_def) {
|
2016-10-01 02:49:36 +08:00
|
|
|
desc = cc->cpu_def->model_id;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
(*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
|
|
|
|
|
name, desc);
|
|
|
|
|
g_free(name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* list available CPU models and flags */
|
2012-09-06 04:41:08 +08:00
|
|
|
void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
|
2010-03-11 21:38:55 +08:00
|
|
|
{
|
2013-01-21 08:02:28 +08:00
|
|
|
int i;
|
2016-10-01 02:49:36 +08:00
|
|
|
CPUListState s = {
|
|
|
|
|
.file = f,
|
|
|
|
|
.cpu_fprintf = cpu_fprintf,
|
|
|
|
|
};
|
|
|
|
|
GSList *list;
|
2010-03-11 21:38:55 +08:00
|
|
|
|
2016-10-01 02:49:36 +08:00
|
|
|
(*cpu_fprintf)(f, "Available CPUs:\n");
|
|
|
|
|
list = get_sorted_cpu_model_list();
|
|
|
|
|
g_slist_foreach(list, x86_cpu_list_entry, &s);
|
|
|
|
|
g_slist_free(list);
|
2013-03-25 00:01:02 +08:00
|
|
|
|
2012-09-06 04:41:07 +08:00
|
|
|
(*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
|
2013-02-27 17:15:51 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
|
|
|
|
|
FeatureWordInfo *fw = &feature_word_info[i];
|
|
|
|
|
|
2015-02-04 01:48:55 +08:00
|
|
|
(*cpu_fprintf)(f, " ");
|
|
|
|
|
listflags(f, cpu_fprintf, fw->feat_names);
|
|
|
|
|
(*cpu_fprintf)(f, "\n");
|
2013-02-27 17:15:51 +08:00
|
|
|
}
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
|
|
|
|
|
2016-10-01 02:49:36 +08:00
|
|
|
static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
|
|
|
|
|
{
|
|
|
|
|
ObjectClass *oc = data;
|
|
|
|
|
X86CPUClass *cc = X86_CPU_CLASS(oc);
|
|
|
|
|
CpuDefinitionInfoList **cpu_list = user_data;
|
|
|
|
|
CpuDefinitionInfoList *entry;
|
|
|
|
|
CpuDefinitionInfo *info;
|
|
|
|
|
|
|
|
|
|
info = g_malloc0(sizeof(*info));
|
|
|
|
|
info->name = x86_cpu_class_get_model_name(cc);
|
2016-05-04 00:48:13 +08:00
|
|
|
x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
|
|
|
|
|
info->has_unavailable_features = true;
|
2016-11-17 02:21:39 +08:00
|
|
|
info->q_typename = g_strdup(object_class_get_name(oc));
|
2017-01-17 02:12:12 +08:00
|
|
|
info->migration_safe = cc->migration_safe;
|
|
|
|
|
info->has_migration_safe = true;
|
i386: Define static "base" CPU model
The query-cpu-model-expand QMP command needs at least one static
model, to allow the "static" expansion mode to be implemented.
Instead of defining static versions of every CPU model, define a
"base" CPU model that has absolutely no feature flag enabled.
Despite having no CPUID data set at all, "-cpu base" is even a
functional CPU:
* It can boot a Slackware Linux 1.01 image with a Linux 0.99.12
kernel[1].
* It is even possible to boot[2] a modern Fedora x86_64 guest by
manually enabling the following CPU features:
-cpu base,+lm,+msr,+pae,+fpu,+cx8,+cmov,+sse,+sse2,+fxsr
[1] http://www.qemu-advent-calendar.org/2014/#day-1
[2] This is what can be seen in the guest:
[root@localhost ~]# cat /proc/cpuinfo
processor : 0
vendor_id : unknown
cpu family : 0
model : 0
model name : 00/00
stepping : 0
physical id : 0
siblings : 1
core id : 0
cpu cores : 1
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu msr pae cx8 cmov fxsr sse sse2 lm nopl
bugs :
bogomips : 5832.70
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
[root@localhost ~]# x86info -v -a
x86info v1.30. Dave Jones 2001-2011
Feedback to <davej@redhat.com>.
No TSC, MHz calculation cannot be performed.
Unknown vendor (0)
MP Table:
Family: 0 Model: 0 Stepping: 0
CPU Model (x86info's best guess):
eax in: 0x00000000, eax = 00000001 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x00000001, eax = 00000000 ebx = 00000800 ecx = 00000000 edx = 07008161
eax in: 0x80000000, eax = 80000001 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 20000000
Feature flags:
fpu Onboard FPU
msr Model-Specific Registers
pae Physical Address Extensions
cx8 CMPXCHG8 instruction
cmov CMOV instruction
fxsr FXSAVE and FXRSTOR instructions
sse SSE support
sse2 SSE2 support
Long NOPs supported: yes
Address sizes : 0 bits physical, 0 bits virtual
0MHz processor (estimate).
running at an estimated 0MHz
[root@localhost ~]#
Message-Id: <20170222190029.17243-2-ehabkost@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Tested-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-02-23 03:00:27 +08:00
|
|
|
info->q_static = cc->static_model;
|
2016-10-01 02:49:36 +08:00
|
|
|
|
|
|
|
|
entry = g_malloc0(sizeof(*entry));
|
|
|
|
|
entry->value = info;
|
|
|
|
|
entry->next = *cpu_list;
|
|
|
|
|
*cpu_list = entry;
|
|
|
|
|
}
|
|
|
|
|
|
2012-08-15 11:17:36 +08:00
|
|
|
CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
|
2012-08-11 00:04:14 +08:00
|
|
|
{
|
|
|
|
|
CpuDefinitionInfoList *cpu_list = NULL;
|
2016-10-01 02:49:36 +08:00
|
|
|
GSList *list = get_sorted_cpu_model_list();
|
|
|
|
|
g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
|
|
|
|
|
g_slist_free(list);
|
2012-08-11 00:04:14 +08:00
|
|
|
return cpu_list;
|
|
|
|
|
}
|
|
|
|
|
|
2014-05-01 00:48:41 +08:00
|
|
|
static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
|
|
|
|
|
bool migratable_only)
|
2014-05-01 00:48:32 +08:00
|
|
|
{
|
|
|
|
|
FeatureWordInfo *wi = &feature_word_info[w];
|
2014-05-01 00:48:41 +08:00
|
|
|
uint32_t r;
|
2014-05-01 00:48:32 +08:00
|
|
|
|
2014-05-01 00:48:39 +08:00
|
|
|
if (kvm_enabled()) {
|
2014-05-01 00:48:41 +08:00
|
|
|
r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
|
|
|
|
|
wi->cpuid_ecx,
|
|
|
|
|
wi->cpuid_reg);
|
2017-09-13 17:05:19 +08:00
|
|
|
} else if (hvf_enabled()) {
|
|
|
|
|
r = hvf_get_supported_cpuid(wi->cpuid_eax,
|
|
|
|
|
wi->cpuid_ecx,
|
|
|
|
|
wi->cpuid_reg);
|
2014-05-01 00:48:39 +08:00
|
|
|
} else if (tcg_enabled()) {
|
2014-05-01 00:48:41 +08:00
|
|
|
r = wi->tcg_features;
|
2014-05-01 00:48:39 +08:00
|
|
|
} else {
|
|
|
|
|
return ~0;
|
|
|
|
|
}
|
2014-05-01 00:48:41 +08:00
|
|
|
if (migratable_only) {
|
|
|
|
|
r &= x86_cpu_get_migratable_flags(w);
|
|
|
|
|
}
|
|
|
|
|
return r;
|
2014-05-01 00:48:32 +08:00
|
|
|
}
|
|
|
|
|
|
2016-05-05 01:50:46 +08:00
|
|
|
static void x86_cpu_report_filtered_features(X86CPU *cpu)
|
|
|
|
|
{
|
|
|
|
|
FeatureWord w;
|
|
|
|
|
|
|
|
|
|
for (w = 0; w < FEATURE_WORDS; w++) {
|
|
|
|
|
report_unavailable_features(w, cpu->filtered_features[w]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-11 23:40:27 +08:00
|
|
|
static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
|
|
|
|
|
{
|
|
|
|
|
PropValue *pv;
|
|
|
|
|
for (pv = props; pv->prop; pv++) {
|
|
|
|
|
if (!pv->value) {
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
object_property_parse(OBJECT(cpu), pv->value, pv->prop,
|
|
|
|
|
&error_abort);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-23 03:00:28 +08:00
|
|
|
/* Load data from X86CPUDefinition into a X86CPU object
|
2014-01-31 03:48:56 +08:00
|
|
|
*/
|
2014-02-10 18:21:30 +08:00
|
|
|
static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
|
2010-03-11 21:38:55 +08:00
|
|
|
{
|
2012-04-17 18:00:51 +08:00
|
|
|
CPUX86State *env = &cpu->env;
|
2014-02-20 03:39:21 +08:00
|
|
|
const char *vendor;
|
|
|
|
|
char host_vendor[CPUID_VENDOR_SZ + 1];
|
2014-05-01 00:48:37 +08:00
|
|
|
FeatureWord w;
|
2010-03-11 21:38:55 +08:00
|
|
|
|
2017-02-23 03:00:28 +08:00
|
|
|
/*NOTE: any property set by this function should be returned by
|
|
|
|
|
* x86_cpu_static_props(), so static expansion of
|
|
|
|
|
* query-cpu-model-expansion is always complete.
|
|
|
|
|
*/
|
|
|
|
|
|
2016-09-22 00:30:12 +08:00
|
|
|
/* CPU models only set _minimum_ values for level/xlevel: */
|
2017-06-08 00:36:31 +08:00
|
|
|
object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
|
|
|
|
|
object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
|
2016-09-22 00:30:12 +08:00
|
|
|
|
2013-02-15 21:06:56 +08:00
|
|
|
object_property_set_int(OBJECT(cpu), def->family, "family", errp);
|
|
|
|
|
object_property_set_int(OBJECT(cpu), def->model, "model", errp);
|
|
|
|
|
object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
|
|
|
|
|
object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
|
2014-05-01 00:48:37 +08:00
|
|
|
for (w = 0; w < FEATURE_WORDS; w++) {
|
|
|
|
|
env->features[w] = def->features[w];
|
|
|
|
|
}
|
2014-01-31 03:48:54 +08:00
|
|
|
|
2014-01-31 03:48:58 +08:00
|
|
|
/* Special cases not set in the X86CPUDefinition structs: */
|
2017-09-13 17:05:19 +08:00
|
|
|
/* TODO: in-kernel irqchip for hvf */
|
2014-01-31 03:48:54 +08:00
|
|
|
if (kvm_enabled()) {
|
2016-02-25 23:15:12 +08:00
|
|
|
if (!kvm_irqchip_in_kernel()) {
|
|
|
|
|
x86_cpu_change_kvm_default("x2apic", "off");
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-11 23:40:27 +08:00
|
|
|
x86_cpu_apply_props(cpu, kvm_default_props);
|
2016-10-01 02:49:37 +08:00
|
|
|
} else if (tcg_enabled()) {
|
|
|
|
|
x86_cpu_apply_props(cpu, tcg_default_props);
|
2014-01-31 03:48:54 +08:00
|
|
|
}
|
2014-02-19 22:58:10 +08:00
|
|
|
|
2014-01-31 03:48:54 +08:00
|
|
|
env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
|
2014-01-31 03:48:55 +08:00
|
|
|
|
|
|
|
|
/* sysenter isn't supported in compatibility mode on AMD,
|
|
|
|
|
* syscall isn't supported in compatibility mode on Intel.
|
|
|
|
|
* Normally we advertise the actual CPU vendor, but you can
|
|
|
|
|
* override this using the 'vendor' property if you want to use
|
|
|
|
|
* KVM's sysenter/syscall emulation in compatibility mode and
|
|
|
|
|
* when doing cross vendor migration
|
|
|
|
|
*/
|
2014-02-20 03:39:21 +08:00
|
|
|
vendor = def->vendor;
|
2017-09-13 17:05:19 +08:00
|
|
|
if (accel_uses_host_cpuid()) {
|
2014-01-31 03:48:55 +08:00
|
|
|
uint32_t ebx = 0, ecx = 0, edx = 0;
|
|
|
|
|
host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
|
|
|
|
|
x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
|
|
|
|
|
vendor = host_vendor;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
|
|
|
|
|
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
|
|
|
|
|
2017-02-23 03:00:28 +08:00
|
|
|
/* Return a QDict containing keys for all properties that can be included
|
|
|
|
|
* in static expansion of CPU models. All properties set by x86_cpu_load_def()
|
|
|
|
|
* must be included in the dictionary.
|
|
|
|
|
*/
|
|
|
|
|
static QDict *x86_cpu_static_props(void)
|
|
|
|
|
{
|
|
|
|
|
FeatureWord w;
|
|
|
|
|
int i;
|
|
|
|
|
static const char *props[] = {
|
|
|
|
|
"min-level",
|
|
|
|
|
"min-xlevel",
|
|
|
|
|
"family",
|
|
|
|
|
"model",
|
|
|
|
|
"stepping",
|
|
|
|
|
"model-id",
|
|
|
|
|
"vendor",
|
|
|
|
|
"lmce",
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
static QDict *d;
|
|
|
|
|
|
|
|
|
|
if (d) {
|
|
|
|
|
return d;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
d = qdict_new();
|
|
|
|
|
for (i = 0; props[i]; i++) {
|
2017-08-25 18:59:00 +08:00
|
|
|
qdict_put_null(d, props[i]);
|
2017-02-23 03:00:28 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (w = 0; w < FEATURE_WORDS; w++) {
|
|
|
|
|
FeatureWordInfo *fi = &feature_word_info[w];
|
|
|
|
|
int bit;
|
|
|
|
|
for (bit = 0; bit < 32; bit++) {
|
|
|
|
|
if (!fi->feat_names[bit]) {
|
|
|
|
|
continue;
|
|
|
|
|
}
|
2017-08-25 18:59:00 +08:00
|
|
|
qdict_put_null(d, fi->feat_names[bit]);
|
2017-02-23 03:00:28 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return d;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Add an entry to @props dict, with the value for property. */
|
|
|
|
|
static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
|
|
|
|
|
{
|
|
|
|
|
QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
|
|
|
|
|
&error_abort);
|
|
|
|
|
|
|
|
|
|
qdict_put_obj(props, prop, value);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Convert CPU model data from X86CPU object to a property dictionary
|
|
|
|
|
* that can recreate exactly the same CPU model.
|
|
|
|
|
*/
|
|
|
|
|
static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
|
|
|
|
|
{
|
|
|
|
|
QDict *sprops = x86_cpu_static_props();
|
|
|
|
|
const QDictEntry *e;
|
|
|
|
|
|
|
|
|
|
for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
|
|
|
|
|
const char *prop = qdict_entry_key(e);
|
|
|
|
|
x86_cpu_expand_prop(cpu, props, prop);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-23 03:00:29 +08:00
|
|
|
/* Convert CPU model data from X86CPU object to a property dictionary
|
|
|
|
|
* that can recreate exactly the same CPU model, including every
|
|
|
|
|
* writeable QOM property.
|
|
|
|
|
*/
|
|
|
|
|
static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
|
|
|
|
|
{
|
|
|
|
|
ObjectPropertyIterator iter;
|
|
|
|
|
ObjectProperty *prop;
|
|
|
|
|
|
|
|
|
|
object_property_iter_init(&iter, OBJECT(cpu));
|
|
|
|
|
while ((prop = object_property_iter_next(&iter))) {
|
|
|
|
|
/* skip read-only or write-only properties */
|
|
|
|
|
if (!prop->get || !prop->set) {
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* "hotplugged" is the only property that is configurable
|
|
|
|
|
* on the command-line but will be set differently on CPUs
|
|
|
|
|
* created using "-cpu ... -smp ..." and by CPUs created
|
|
|
|
|
* on the fly by x86_cpu_from_model() for querying. Skip it.
|
|
|
|
|
*/
|
|
|
|
|
if (!strcmp(prop->name, "hotplugged")) {
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
x86_cpu_expand_prop(cpu, props, prop->name);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-23 03:00:28 +08:00
|
|
|
static void object_apply_props(Object *obj, QDict *props, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
const QDictEntry *prop;
|
|
|
|
|
Error *err = NULL;
|
|
|
|
|
|
|
|
|
|
for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
|
|
|
|
|
object_property_set_qobject(obj, qdict_entry_value(prop),
|
|
|
|
|
qdict_entry_key(prop), &err);
|
|
|
|
|
if (err) {
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
error_propagate(errp, err);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Create X86CPU object according to model+props specification */
|
|
|
|
|
static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *xc = NULL;
|
|
|
|
|
X86CPUClass *xcc;
|
|
|
|
|
Error *err = NULL;
|
|
|
|
|
|
|
|
|
|
xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
|
|
|
|
|
if (xcc == NULL) {
|
|
|
|
|
error_setg(&err, "CPU model '%s' not found", model);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
|
|
|
|
|
if (props) {
|
|
|
|
|
object_apply_props(OBJECT(xc), props, &err);
|
|
|
|
|
if (err) {
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
x86_cpu_expand_features(xc, &err);
|
|
|
|
|
if (err) {
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
if (err) {
|
|
|
|
|
error_propagate(errp, err);
|
|
|
|
|
object_unref(OBJECT(xc));
|
|
|
|
|
xc = NULL;
|
|
|
|
|
}
|
|
|
|
|
return xc;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
CpuModelExpansionInfo *
|
|
|
|
|
arch_query_cpu_model_expansion(CpuModelExpansionType type,
|
|
|
|
|
CpuModelInfo *model,
|
|
|
|
|
Error **errp)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *xc = NULL;
|
|
|
|
|
Error *err = NULL;
|
|
|
|
|
CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
|
|
|
|
|
QDict *props = NULL;
|
|
|
|
|
const char *base_name;
|
|
|
|
|
|
|
|
|
|
xc = x86_cpu_from_model(model->name,
|
|
|
|
|
model->has_props ?
|
2018-02-24 23:40:29 +08:00
|
|
|
qobject_to(QDict, model->props) :
|
2017-02-23 03:00:28 +08:00
|
|
|
NULL, &err);
|
|
|
|
|
if (err) {
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-23 03:00:29 +08:00
|
|
|
props = qdict_new();
|
2017-02-23 03:00:28 +08:00
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
|
case CPU_MODEL_EXPANSION_TYPE_STATIC:
|
|
|
|
|
/* Static expansion will be based on "base" only */
|
|
|
|
|
base_name = "base";
|
2017-02-23 03:00:29 +08:00
|
|
|
x86_cpu_to_dict(xc, props);
|
2017-02-23 03:00:28 +08:00
|
|
|
break;
|
|
|
|
|
case CPU_MODEL_EXPANSION_TYPE_FULL:
|
|
|
|
|
/* As we don't return every single property, full expansion needs
|
|
|
|
|
* to keep the original model name+props, and add extra
|
|
|
|
|
* properties on top of that.
|
|
|
|
|
*/
|
|
|
|
|
base_name = model->name;
|
2017-02-23 03:00:29 +08:00
|
|
|
x86_cpu_to_dict_full(xc, props);
|
2017-02-23 03:00:28 +08:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
error_setg(&err, "Unsupportted expansion type");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!props) {
|
|
|
|
|
props = qdict_new();
|
|
|
|
|
}
|
|
|
|
|
x86_cpu_to_dict(xc, props);
|
|
|
|
|
|
|
|
|
|
ret->model = g_new0(CpuModelInfo, 1);
|
|
|
|
|
ret->model->name = g_strdup(base_name);
|
|
|
|
|
ret->model->props = QOBJECT(props);
|
|
|
|
|
ret->model->has_props = true;
|
|
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
object_unref(OBJECT(xc));
|
|
|
|
|
if (err) {
|
|
|
|
|
error_propagate(errp, err);
|
|
|
|
|
qapi_free_CpuModelExpansionInfo(ret);
|
|
|
|
|
ret = NULL;
|
|
|
|
|
}
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2016-12-29 00:34:02 +08:00
|
|
|
static gchar *x86_gdb_arch_name(CPUState *cs)
|
|
|
|
|
{
|
|
|
|
|
#ifdef TARGET_X86_64
|
|
|
|
|
return g_strdup("i386:x86-64");
|
|
|
|
|
#else
|
|
|
|
|
return g_strdup("i386");
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2014-02-10 18:21:30 +08:00
|
|
|
static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
|
|
|
|
|
{
|
|
|
|
|
X86CPUDefinition *cpudef = data;
|
|
|
|
|
X86CPUClass *xcc = X86_CPU_CLASS(oc);
|
|
|
|
|
|
|
|
|
|
xcc->cpu_def = cpudef;
|
2017-01-17 02:12:12 +08:00
|
|
|
xcc->migration_safe = true;
|
2014-02-10 18:21:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void x86_register_cpudef_type(X86CPUDefinition *def)
|
|
|
|
|
{
|
|
|
|
|
char *typename = x86_cpu_type_name(def->name);
|
|
|
|
|
TypeInfo ti = {
|
|
|
|
|
.name = typename,
|
|
|
|
|
.parent = TYPE_X86_CPU,
|
|
|
|
|
.class_init = x86_cpu_cpudef_class_init,
|
|
|
|
|
.class_data = def,
|
|
|
|
|
};
|
|
|
|
|
|
2017-01-14 03:00:57 +08:00
|
|
|
/* AMD aliases are handled at runtime based on CPUID vendor, so
|
|
|
|
|
* they shouldn't be set on the CPU model table.
|
|
|
|
|
*/
|
|
|
|
|
assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
|
2018-01-09 23:45:13 +08:00
|
|
|
/* catch mistakes instead of silently truncating model_id when too long */
|
|
|
|
|
assert(def->model_id && strlen(def->model_id) <= 48);
|
|
|
|
|
|
2017-01-14 03:00:57 +08:00
|
|
|
|
2014-02-10 18:21:30 +08:00
|
|
|
type_register(&ti);
|
|
|
|
|
g_free(typename);
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-11 21:38:55 +08:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
|
|
2010-06-19 15:42:34 +08:00
|
|
|
void cpu_clear_apic_feature(CPUX86State *env)
|
|
|
|
|
{
|
2013-04-23 03:00:15 +08:00
|
|
|
env->features[FEAT_1_EDX] &= ~CPUID_APIC;
|
2010-06-19 15:42:34 +08:00
|
|
|
}
|
|
|
|
|
|
2010-03-11 21:38:55 +08:00
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
|
|
|
|
|
|
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
|
|
|
|
uint32_t *eax, uint32_t *ebx,
|
|
|
|
|
uint32_t *ecx, uint32_t *edx)
|
|
|
|
|
{
|
2012-12-01 12:35:08 +08:00
|
|
|
X86CPU *cpu = x86_env_get_cpu(env);
|
|
|
|
|
CPUState *cs = CPU(cpu);
|
target-i386: present virtual L3 cache info for vcpus
Some software algorithms are based on the hardware's cache info, for example,
for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger
a resched IPI and told cpu2 to do the wakeup if they don't share low level
cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc.
The relevant linux-kernel code as bellow:
static void ttwu_queue(struct task_struct *p, int cpu)
{
struct rq *rq = cpu_rq(cpu);
......
if (... && !cpus_share_cache(smp_processor_id(), cpu)) {
......
ttwu_queue_remote(p, cpu); /* will trigger RES IPI */
return;
}
......
ttwu_do_activate(rq, p, 0); /* access target's rq directly */
......
}
In real hardware, the cpus on the same socket share L3 cache, so one won't
trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a
virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs
under some workloads even if the virtual cpus belongs to the same virtual socket.
For KVM, there will be lots of vmexit due to guest send IPIs.
The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates)
and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during
the period:
No-L3 With-L3(applied this patch)
cpu0: 363890 44582
cpu1: 373405 43109
cpu2: 340783 43797
cpu3: 333854 43409
cpu4: 327170 40038
cpu5: 325491 39922
cpu6: 319129 42391
cpu7: 306480 41035
cpu8: 161139 32188
cpu9: 164649 31024
cpu10: 149823 30398
cpu11: 149823 32455
cpu12: 164830 35143
cpu13: 172269 35805
cpu14: 179979 33898
cpu15: 194505 32754
avg: 268963.6 40129.8
The VM's topology is "1*socket 8*cores 2*threads".
After present virtual L3 cache info for VM, the amounts of RES IPIs in guest
reduce 85%.
For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause
severe performance degradation. We had tested the overall system performance if
vcpus actually run on sparate physical socket. With L3 cache, the performance
improves 7.2%~33.1%(avg:15.7%).
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-09-07 13:21:13 +08:00
|
|
|
uint32_t pkg_offset;
|
2017-05-09 21:27:35 +08:00
|
|
|
uint32_t limit;
|
2017-05-09 21:27:36 +08:00
|
|
|
uint32_t signature[3];
|
2012-12-01 12:35:08 +08:00
|
|
|
|
2017-05-09 21:27:35 +08:00
|
|
|
/* Calculate & apply limits for different index ranges */
|
|
|
|
|
if (index >= 0xC0000000) {
|
|
|
|
|
limit = env->cpuid_xlevel2;
|
|
|
|
|
} else if (index >= 0x80000000) {
|
|
|
|
|
limit = env->cpuid_xlevel;
|
2017-05-09 21:27:36 +08:00
|
|
|
} else if (index >= 0x40000000) {
|
|
|
|
|
limit = 0x40000001;
|
2010-03-11 21:38:55 +08:00
|
|
|
} else {
|
2017-05-09 21:27:35 +08:00
|
|
|
limit = env->cpuid_level;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (index > limit) {
|
|
|
|
|
/* Intel documentation states that invalid EAX input will
|
|
|
|
|
* return the same information as EAX=cpuid_level
|
|
|
|
|
* (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
|
|
|
|
|
*/
|
|
|
|
|
index = env->cpuid_level;
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch(index) {
|
|
|
|
|
case 0:
|
|
|
|
|
*eax = env->cpuid_level;
|
2015-02-04 01:57:50 +08:00
|
|
|
*ebx = env->cpuid_vendor1;
|
|
|
|
|
*edx = env->cpuid_vendor2;
|
|
|
|
|
*ecx = env->cpuid_vendor3;
|
2010-03-11 21:38:55 +08:00
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
*eax = env->cpuid_version;
|
2014-12-19 09:20:10 +08:00
|
|
|
*ebx = (cpu->apic_id << 24) |
|
|
|
|
|
8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
|
2013-04-23 03:00:15 +08:00
|
|
|
*ecx = env->features[FEAT_1_ECX];
|
2015-07-02 21:53:40 +08:00
|
|
|
if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
|
|
|
|
|
*ecx |= CPUID_EXT_OSXSAVE;
|
|
|
|
|
}
|
2013-04-23 03:00:15 +08:00
|
|
|
*edx = env->features[FEAT_1_EDX];
|
2012-12-17 10:27:07 +08:00
|
|
|
if (cs->nr_cores * cs->nr_threads > 1) {
|
|
|
|
|
*ebx |= (cs->nr_cores * cs->nr_threads) << 16;
|
2015-07-02 21:53:40 +08:00
|
|
|
*edx |= CPUID_HT;
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
/* cache info: needed for Pentium Pro compatibility */
|
2013-09-02 23:06:37 +08:00
|
|
|
if (cpu->cache_info_passthrough) {
|
|
|
|
|
host_cpuid(index, 0, eax, ebx, ecx, edx);
|
|
|
|
|
break;
|
|
|
|
|
}
|
2013-08-27 23:24:37 +08:00
|
|
|
*eax = 1; /* Number of CPUID[EAX=2] calls required */
|
2010-03-11 21:38:55 +08:00
|
|
|
*ebx = 0;
|
target-i386: present virtual L3 cache info for vcpus
Some software algorithms are based on the hardware's cache info, for example,
for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger
a resched IPI and told cpu2 to do the wakeup if they don't share low level
cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc.
The relevant linux-kernel code as bellow:
static void ttwu_queue(struct task_struct *p, int cpu)
{
struct rq *rq = cpu_rq(cpu);
......
if (... && !cpus_share_cache(smp_processor_id(), cpu)) {
......
ttwu_queue_remote(p, cpu); /* will trigger RES IPI */
return;
}
......
ttwu_do_activate(rq, p, 0); /* access target's rq directly */
......
}
In real hardware, the cpus on the same socket share L3 cache, so one won't
trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a
virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs
under some workloads even if the virtual cpus belongs to the same virtual socket.
For KVM, there will be lots of vmexit due to guest send IPIs.
The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates)
and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during
the period:
No-L3 With-L3(applied this patch)
cpu0: 363890 44582
cpu1: 373405 43109
cpu2: 340783 43797
cpu3: 333854 43409
cpu4: 327170 40038
cpu5: 325491 39922
cpu6: 319129 42391
cpu7: 306480 41035
cpu8: 161139 32188
cpu9: 164649 31024
cpu10: 149823 30398
cpu11: 149823 32455
cpu12: 164830 35143
cpu13: 172269 35805
cpu14: 179979 33898
cpu15: 194505 32754
avg: 268963.6 40129.8
The VM's topology is "1*socket 8*cores 2*threads".
After present virtual L3 cache info for VM, the amounts of RES IPIs in guest
reduce 85%.
For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause
severe performance degradation. We had tested the overall system performance if
vcpus actually run on sparate physical socket. With L3 cache, the performance
improves 7.2%~33.1%(avg:15.7%).
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-09-07 13:21:13 +08:00
|
|
|
if (!cpu->enable_l3_cache) {
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
} else {
|
|
|
|
|
*ecx = L3_N_DESCRIPTOR;
|
|
|
|
|
}
|
2013-08-27 23:24:37 +08:00
|
|
|
*edx = (L1D_DESCRIPTOR << 16) | \
|
|
|
|
|
(L1I_DESCRIPTOR << 8) | \
|
|
|
|
|
(L2_DESCRIPTOR);
|
2010-03-11 21:38:55 +08:00
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
/* cache info: needed for Core compatibility */
|
2013-09-02 23:06:37 +08:00
|
|
|
if (cpu->cache_info_passthrough) {
|
|
|
|
|
host_cpuid(index, count, eax, ebx, ecx, edx);
|
2013-11-20 00:49:46 +08:00
|
|
|
*eax &= ~0xFC000000;
|
2010-03-11 21:38:55 +08:00
|
|
|
} else {
|
2010-03-13 23:46:33 +08:00
|
|
|
*eax = 0;
|
2013-11-20 00:49:46 +08:00
|
|
|
switch (count) {
|
2010-03-11 21:38:55 +08:00
|
|
|
case 0: /* L1 dcache info */
|
2013-08-27 23:24:37 +08:00
|
|
|
*eax |= CPUID_4_TYPE_DCACHE | \
|
|
|
|
|
CPUID_4_LEVEL(1) | \
|
|
|
|
|
CPUID_4_SELF_INIT_LEVEL;
|
|
|
|
|
*ebx = (L1D_LINE_SIZE - 1) | \
|
|
|
|
|
((L1D_PARTITIONS - 1) << 12) | \
|
|
|
|
|
((L1D_ASSOCIATIVITY - 1) << 22);
|
|
|
|
|
*ecx = L1D_SETS - 1;
|
|
|
|
|
*edx = CPUID_4_NO_INVD_SHARING;
|
2010-03-11 21:38:55 +08:00
|
|
|
break;
|
|
|
|
|
case 1: /* L1 icache info */
|
2013-08-27 23:24:37 +08:00
|
|
|
*eax |= CPUID_4_TYPE_ICACHE | \
|
|
|
|
|
CPUID_4_LEVEL(1) | \
|
|
|
|
|
CPUID_4_SELF_INIT_LEVEL;
|
|
|
|
|
*ebx = (L1I_LINE_SIZE - 1) | \
|
|
|
|
|
((L1I_PARTITIONS - 1) << 12) | \
|
|
|
|
|
((L1I_ASSOCIATIVITY - 1) << 22);
|
|
|
|
|
*ecx = L1I_SETS - 1;
|
|
|
|
|
*edx = CPUID_4_NO_INVD_SHARING;
|
2010-03-11 21:38:55 +08:00
|
|
|
break;
|
|
|
|
|
case 2: /* L2 cache info */
|
2013-08-27 23:24:37 +08:00
|
|
|
*eax |= CPUID_4_TYPE_UNIFIED | \
|
|
|
|
|
CPUID_4_LEVEL(2) | \
|
|
|
|
|
CPUID_4_SELF_INIT_LEVEL;
|
2012-12-17 10:27:07 +08:00
|
|
|
if (cs->nr_threads > 1) {
|
|
|
|
|
*eax |= (cs->nr_threads - 1) << 14;
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
2013-08-27 23:24:37 +08:00
|
|
|
*ebx = (L2_LINE_SIZE - 1) | \
|
|
|
|
|
((L2_PARTITIONS - 1) << 12) | \
|
|
|
|
|
((L2_ASSOCIATIVITY - 1) << 22);
|
|
|
|
|
*ecx = L2_SETS - 1;
|
|
|
|
|
*edx = CPUID_4_NO_INVD_SHARING;
|
2010-03-11 21:38:55 +08:00
|
|
|
break;
|
target-i386: present virtual L3 cache info for vcpus
Some software algorithms are based on the hardware's cache info, for example,
for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger
a resched IPI and told cpu2 to do the wakeup if they don't share low level
cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc.
The relevant linux-kernel code as bellow:
static void ttwu_queue(struct task_struct *p, int cpu)
{
struct rq *rq = cpu_rq(cpu);
......
if (... && !cpus_share_cache(smp_processor_id(), cpu)) {
......
ttwu_queue_remote(p, cpu); /* will trigger RES IPI */
return;
}
......
ttwu_do_activate(rq, p, 0); /* access target's rq directly */
......
}
In real hardware, the cpus on the same socket share L3 cache, so one won't
trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a
virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs
under some workloads even if the virtual cpus belongs to the same virtual socket.
For KVM, there will be lots of vmexit due to guest send IPIs.
The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates)
and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during
the period:
No-L3 With-L3(applied this patch)
cpu0: 363890 44582
cpu1: 373405 43109
cpu2: 340783 43797
cpu3: 333854 43409
cpu4: 327170 40038
cpu5: 325491 39922
cpu6: 319129 42391
cpu7: 306480 41035
cpu8: 161139 32188
cpu9: 164649 31024
cpu10: 149823 30398
cpu11: 149823 32455
cpu12: 164830 35143
cpu13: 172269 35805
cpu14: 179979 33898
cpu15: 194505 32754
avg: 268963.6 40129.8
The VM's topology is "1*socket 8*cores 2*threads".
After present virtual L3 cache info for VM, the amounts of RES IPIs in guest
reduce 85%.
For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause
severe performance degradation. We had tested the overall system performance if
vcpus actually run on sparate physical socket. With L3 cache, the performance
improves 7.2%~33.1%(avg:15.7%).
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-09-07 13:21:13 +08:00
|
|
|
case 3: /* L3 cache info */
|
|
|
|
|
if (!cpu->enable_l3_cache) {
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
*eax |= CPUID_4_TYPE_UNIFIED | \
|
|
|
|
|
CPUID_4_LEVEL(3) | \
|
|
|
|
|
CPUID_4_SELF_INIT_LEVEL;
|
|
|
|
|
pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
|
|
|
|
|
*eax |= ((1 << pkg_offset) - 1) << 14;
|
|
|
|
|
*ebx = (L3_N_LINE_SIZE - 1) | \
|
|
|
|
|
((L3_N_PARTITIONS - 1) << 12) | \
|
|
|
|
|
((L3_N_ASSOCIATIVITY - 1) << 22);
|
|
|
|
|
*ecx = L3_N_SETS - 1;
|
|
|
|
|
*edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
|
|
|
|
|
break;
|
2010-03-11 21:38:55 +08:00
|
|
|
default: /* end of info */
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
break;
|
2013-11-20 00:49:46 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
|
|
|
|
|
if ((*eax & 31) && cs->nr_cores > 1) {
|
|
|
|
|
*eax |= (cs->nr_cores - 1) << 26;
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
|
|
|
|
/* mwait info: needed for Core compatibility */
|
|
|
|
|
*eax = 0; /* Smallest monitor-line size in bytes */
|
|
|
|
|
*ebx = 0; /* Largest monitor-line size in bytes */
|
|
|
|
|
*ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
break;
|
|
|
|
|
case 6:
|
|
|
|
|
/* Thermal and Power Leaf */
|
2015-06-07 17:15:08 +08:00
|
|
|
*eax = env->features[FEAT_6_EAX];
|
2010-03-11 21:38:55 +08:00
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
break;
|
2011-05-30 23:17:42 +08:00
|
|
|
case 7:
|
Expose CPUID leaf 7 only for -cpu host
Changes v2 -> v3;
- Check for kvm_enabled() before setting cpuid_7_0_ebx_features
Changes v1 -> v2:
- Use kvm_arch_get_supported_cpuid() instead of host_cpuid() on
cpu_x86_fill_host().
We should use GET_SUPPORTED_CPUID for all bits on "-cpu host"
eventually, but I am not changing all the other CPUID leaves because
we may not be able to test such an intrusive change in time for 1.1.
Description of the bug:
Since QEMU 0.15, the CPUID information on CPUID[EAX=7,ECX=0] is being
returned unfiltered to the guest, directly from the GET_SUPPORTED_CPUID
return value.
The problem is that this makes the resulting CPU feature flags
unpredictable and dependent on the host CPU and kernel version. This
breaks live-migration badly if migrating from a host CPU that supports
some features on that CPUID leaf (running a recent kernel) to a kernel
or host CPU that doesn't support it.
Migration also is incorrect (the virtual CPU changes under the guest's
feet) if you migrate in the opposite direction (from an old CPU/kernel
to a new CPU/kernel), but with less serious consequences (guests
normally query CPUID information only once on boot).
Fortunately, the bug affects only users using cpudefs with level >= 7.
The right behavior should be to explicitly enable those features on
[cpudef] config sections or on the "-cpu" command-line arguments. Right
now there is no predefined CPU model on QEMU that has those features:
the latest Intel model we have is Sandy Bridge.
I would like to get this fixed on 1.1, so I am submitting this patch,
that enables those features only if "-cpu host" is being used (as we
don't have any pre-defined CPU model that actually have those features).
After 1.1 is released, we can make those features properly configurable
on [cpudef] and -cpu configuration.
One problem is: with this patch, users with the following setup:
- Running QEMU 1.0;
- Using a cpudef having level >= 7;
- Running a kernel that supports the features on CPUID leaf 7; and
- Running on a CPU that supports some features on CPUID leaf 7
won't be able to live-migrate to QEMU 1.1. But for these users
live-migration is already broken (they can't live-migrate to hosts with
older CPUs or older kernels, already), I don't see how to avoid this
problem.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-05-21 22:27:02 +08:00
|
|
|
/* Structured Extended Feature Flags Enumeration Leaf */
|
|
|
|
|
if (count == 0) {
|
|
|
|
|
*eax = 0; /* Maximum ECX value for sub-leaves */
|
2013-04-23 03:00:15 +08:00
|
|
|
*ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
|
2015-11-18 10:20:15 +08:00
|
|
|
*ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
|
2016-02-09 21:14:28 +08:00
|
|
|
if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
|
|
|
|
|
*ecx |= CPUID_7_0_ECX_OSPKE;
|
|
|
|
|
}
|
2016-10-31 16:27:26 +08:00
|
|
|
*edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
|
2011-05-30 23:17:42 +08:00
|
|
|
} else {
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
}
|
|
|
|
|
break;
|
2010-03-11 21:38:55 +08:00
|
|
|
case 9:
|
|
|
|
|
/* Direct Cache Access Information Leaf */
|
|
|
|
|
*eax = 0; /* Bits 0-31 in DCA_CAP MSR */
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
break;
|
|
|
|
|
case 0xA:
|
|
|
|
|
/* Architectural Performance Monitoring Leaf */
|
2013-07-27 04:09:36 +08:00
|
|
|
if (kvm_enabled() && cpu->enable_pmu) {
|
2012-12-01 12:35:08 +08:00
|
|
|
KVMState *s = cs->kvm_state;
|
2011-12-15 18:44:05 +08:00
|
|
|
|
|
|
|
|
*eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
|
|
|
|
|
*ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
|
|
|
|
|
*ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
|
|
|
|
|
*edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
|
2017-09-13 17:05:19 +08:00
|
|
|
} else if (hvf_enabled() && cpu->enable_pmu) {
|
|
|
|
|
*eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
|
|
|
|
|
*ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
|
|
|
|
|
*ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
|
|
|
|
|
*edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
|
2011-12-15 18:44:05 +08:00
|
|
|
} else {
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
}
|
2010-03-11 21:38:55 +08:00
|
|
|
break;
|
2016-05-13 01:24:26 +08:00
|
|
|
case 0xB:
|
|
|
|
|
/* Extended Topology Enumeration Leaf */
|
|
|
|
|
if (!cpu->enable_cpuid_0xb) {
|
|
|
|
|
*eax = *ebx = *ecx = *edx = 0;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*ecx = count & 0xff;
|
|
|
|
|
*edx = cpu->apic_id;
|
|
|
|
|
|
|
|
|
|
switch (count) {
|
|
|
|
|
case 0:
|
2016-09-16 23:50:24 +08:00
|
|
|
*eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
|
|
|
|
|
*ebx = cs->nr_threads;
|
2016-05-13 01:24:26 +08:00
|
|
|
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
2016-09-16 23:50:24 +08:00
|
|
|
*eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
|
|
|
|
|
*ebx = cs->nr_cores * cs->nr_threads;
|
2016-05-13 01:24:26 +08:00
|
|
|
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
assert(!(*eax & ~0x1f));
|
|
|
|
|
*ebx &= 0xffff; /* The count doesn't need to be reliable. */
|
|
|
|
|
break;
|
2013-10-02 23:54:57 +08:00
|
|
|
case 0xD: {
|
2010-06-17 15:18:14 +08:00
|
|
|
/* Processor Extended State */
|
2013-10-02 23:54:57 +08:00
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
2015-07-02 21:53:40 +08:00
|
|
|
if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
|
2010-06-17 15:18:14 +08:00
|
|
|
break;
|
|
|
|
|
}
|
2016-09-23 01:33:01 +08:00
|
|
|
|
2013-10-02 23:54:57 +08:00
|
|
|
if (count == 0) {
|
2016-09-23 04:41:35 +08:00
|
|
|
*ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
|
|
|
|
|
*eax = env->features[FEAT_XSAVE_COMP_LO];
|
|
|
|
|
*edx = env->features[FEAT_XSAVE_COMP_HI];
|
2013-10-02 23:54:57 +08:00
|
|
|
*ebx = *ecx;
|
|
|
|
|
} else if (count == 1) {
|
2014-11-24 22:54:43 +08:00
|
|
|
*eax = env->features[FEAT_XSAVE];
|
2015-07-02 22:57:14 +08:00
|
|
|
} else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
|
2016-09-23 04:41:35 +08:00
|
|
|
if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
|
|
|
|
|
const ExtSaveArea *esa = &x86_ext_save_areas[count];
|
2013-12-03 04:17:50 +08:00
|
|
|
*eax = esa->size;
|
|
|
|
|
*ebx = esa->offset;
|
2013-10-02 23:54:57 +08:00
|
|
|
}
|
2010-06-17 15:18:14 +08:00
|
|
|
}
|
|
|
|
|
break;
|
2013-10-02 23:54:57 +08:00
|
|
|
}
|
2018-03-05 00:48:35 +08:00
|
|
|
case 0x14: {
|
|
|
|
|
/* Intel Processor Trace Enumeration */
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
|
|
|
|
|
!kvm_enabled()) {
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (count == 0) {
|
|
|
|
|
*eax = INTEL_PT_MAX_SUBLEAF;
|
|
|
|
|
*ebx = INTEL_PT_MINIMAL_EBX;
|
|
|
|
|
*ecx = INTEL_PT_MINIMAL_ECX;
|
|
|
|
|
} else if (count == 1) {
|
|
|
|
|
*eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
|
|
|
|
|
*ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
2017-05-09 21:27:36 +08:00
|
|
|
case 0x40000000:
|
|
|
|
|
/*
|
|
|
|
|
* CPUID code in kvm_arch_init_vcpu() ignores stuff
|
|
|
|
|
* set here, but we restrict to TCG none the less.
|
|
|
|
|
*/
|
|
|
|
|
if (tcg_enabled() && cpu->expose_tcg) {
|
|
|
|
|
memcpy(signature, "TCGTCGTCGTCG", 12);
|
|
|
|
|
*eax = 0x40000001;
|
|
|
|
|
*ebx = signature[0];
|
|
|
|
|
*ecx = signature[1];
|
|
|
|
|
*edx = signature[2];
|
|
|
|
|
} else {
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x40000001:
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
break;
|
2010-03-11 21:38:55 +08:00
|
|
|
case 0x80000000:
|
|
|
|
|
*eax = env->cpuid_xlevel;
|
|
|
|
|
*ebx = env->cpuid_vendor1;
|
|
|
|
|
*edx = env->cpuid_vendor2;
|
|
|
|
|
*ecx = env->cpuid_vendor3;
|
|
|
|
|
break;
|
|
|
|
|
case 0x80000001:
|
|
|
|
|
*eax = env->cpuid_version;
|
|
|
|
|
*ebx = 0;
|
2013-04-23 03:00:15 +08:00
|
|
|
*ecx = env->features[FEAT_8000_0001_ECX];
|
|
|
|
|
*edx = env->features[FEAT_8000_0001_EDX];
|
2010-03-11 21:38:55 +08:00
|
|
|
|
|
|
|
|
/* The Linux kernel checks for the CMPLegacy bit and
|
|
|
|
|
* discards multiple thread information if it is set.
|
2016-03-23 22:59:57 +08:00
|
|
|
* So don't set it here for Intel to make Linux guests happy.
|
2010-03-11 21:38:55 +08:00
|
|
|
*/
|
2012-12-17 10:27:07 +08:00
|
|
|
if (cs->nr_cores * cs->nr_threads > 1) {
|
2015-02-04 01:57:50 +08:00
|
|
|
if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
|
|
|
|
|
env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
|
|
|
|
|
env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
|
2010-03-11 21:38:55 +08:00
|
|
|
*ecx |= 1 << 1; /* CmpLegacy bit */
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x80000002:
|
|
|
|
|
case 0x80000003:
|
|
|
|
|
case 0x80000004:
|
|
|
|
|
*eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
|
|
|
|
|
*ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
|
|
|
|
|
*ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
|
|
|
|
|
*edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
|
|
|
|
|
break;
|
|
|
|
|
case 0x80000005:
|
|
|
|
|
/* cache info (L1 cache) */
|
2013-09-02 23:06:37 +08:00
|
|
|
if (cpu->cache_info_passthrough) {
|
|
|
|
|
host_cpuid(index, 0, eax, ebx, ecx, edx);
|
|
|
|
|
break;
|
|
|
|
|
}
|
2013-08-27 23:24:37 +08:00
|
|
|
*eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
|
|
|
|
|
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
|
|
|
|
|
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
|
|
|
|
|
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
|
|
|
|
|
*ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
|
|
|
|
|
(L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
|
|
|
|
|
*edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
|
|
|
|
|
(L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
|
2010-03-11 21:38:55 +08:00
|
|
|
break;
|
|
|
|
|
case 0x80000006:
|
|
|
|
|
/* cache info (L2 cache) */
|
2013-09-02 23:06:37 +08:00
|
|
|
if (cpu->cache_info_passthrough) {
|
|
|
|
|
host_cpuid(index, 0, eax, ebx, ecx, edx);
|
|
|
|
|
break;
|
|
|
|
|
}
|
2013-08-27 23:24:37 +08:00
|
|
|
*eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
|
|
|
|
|
(L2_DTLB_2M_ENTRIES << 16) | \
|
|
|
|
|
(AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
|
|
|
|
|
(L2_ITLB_2M_ENTRIES);
|
|
|
|
|
*ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
|
|
|
|
|
(L2_DTLB_4K_ENTRIES << 16) | \
|
|
|
|
|
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
|
|
|
|
|
(L2_ITLB_4K_ENTRIES);
|
|
|
|
|
*ecx = (L2_SIZE_KB_AMD << 16) | \
|
|
|
|
|
(AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
|
|
|
|
|
(L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
|
target-i386: present virtual L3 cache info for vcpus
Some software algorithms are based on the hardware's cache info, for example,
for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger
a resched IPI and told cpu2 to do the wakeup if they don't share low level
cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc.
The relevant linux-kernel code as bellow:
static void ttwu_queue(struct task_struct *p, int cpu)
{
struct rq *rq = cpu_rq(cpu);
......
if (... && !cpus_share_cache(smp_processor_id(), cpu)) {
......
ttwu_queue_remote(p, cpu); /* will trigger RES IPI */
return;
}
......
ttwu_do_activate(rq, p, 0); /* access target's rq directly */
......
}
In real hardware, the cpus on the same socket share L3 cache, so one won't
trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a
virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs
under some workloads even if the virtual cpus belongs to the same virtual socket.
For KVM, there will be lots of vmexit due to guest send IPIs.
The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates)
and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during
the period:
No-L3 With-L3(applied this patch)
cpu0: 363890 44582
cpu1: 373405 43109
cpu2: 340783 43797
cpu3: 333854 43409
cpu4: 327170 40038
cpu5: 325491 39922
cpu6: 319129 42391
cpu7: 306480 41035
cpu8: 161139 32188
cpu9: 164649 31024
cpu10: 149823 30398
cpu11: 149823 32455
cpu12: 164830 35143
cpu13: 172269 35805
cpu14: 179979 33898
cpu15: 194505 32754
avg: 268963.6 40129.8
The VM's topology is "1*socket 8*cores 2*threads".
After present virtual L3 cache info for VM, the amounts of RES IPIs in guest
reduce 85%.
For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause
severe performance degradation. We had tested the overall system performance if
vcpus actually run on sparate physical socket. With L3 cache, the performance
improves 7.2%~33.1%(avg:15.7%).
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-09-07 13:21:13 +08:00
|
|
|
if (!cpu->enable_l3_cache) {
|
|
|
|
|
*edx = ((L3_SIZE_KB / 512) << 18) | \
|
|
|
|
|
(AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
|
|
|
|
|
(L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
|
|
|
|
|
} else {
|
|
|
|
|
*edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
|
|
|
|
|
(AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
|
|
|
|
|
(L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
|
|
|
|
|
}
|
2010-03-11 21:38:55 +08:00
|
|
|
break;
|
2014-05-01 00:48:45 +08:00
|
|
|
case 0x80000007:
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = env->features[FEAT_8000_0007_EDX];
|
|
|
|
|
break;
|
2010-03-11 21:38:55 +08:00
|
|
|
case 0x80000008:
|
|
|
|
|
/* virtual & phys address size in low 2 bytes. */
|
2013-04-23 03:00:15 +08:00
|
|
|
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
|
2016-12-15 08:13:05 +08:00
|
|
|
/* 64 bit processor */
|
|
|
|
|
*eax = cpu->phys_bits; /* configurable physical bits */
|
|
|
|
|
if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
|
|
|
|
|
*eax |= 0x00003900; /* 57 bits virtual */
|
|
|
|
|
} else {
|
|
|
|
|
*eax |= 0x00003000; /* 48 bits virtual */
|
|
|
|
|
}
|
2010-03-11 21:38:55 +08:00
|
|
|
} else {
|
2016-07-08 23:01:36 +08:00
|
|
|
*eax = cpu->phys_bits;
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
2018-01-09 23:45:16 +08:00
|
|
|
*ebx = env->features[FEAT_8000_0008_EBX];
|
2010-03-11 21:38:55 +08:00
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
2012-12-17 10:27:07 +08:00
|
|
|
if (cs->nr_cores * cs->nr_threads > 1) {
|
|
|
|
|
*ecx |= (cs->nr_cores * cs->nr_threads) - 1;
|
2010-03-11 21:38:55 +08:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x8000000A:
|
2013-04-23 03:00:15 +08:00
|
|
|
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
|
2012-12-05 03:34:38 +08:00
|
|
|
*eax = 0x00000001; /* SVM Revision */
|
|
|
|
|
*ebx = 0x00000010; /* nr of ASIDs */
|
|
|
|
|
*ecx = 0;
|
2013-04-23 03:00:15 +08:00
|
|
|
*edx = env->features[FEAT_SVM]; /* optional features */
|
2012-12-05 03:34:38 +08:00
|
|
|
} else {
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
}
|
2010-03-11 21:38:55 +08:00
|
|
|
break;
|
2011-06-01 09:59:52 +08:00
|
|
|
case 0xC0000000:
|
|
|
|
|
*eax = env->cpuid_xlevel2;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
break;
|
|
|
|
|
case 0xC0000001:
|
|
|
|
|
/* Support for VIA CPU's CPUID instruction */
|
|
|
|
|
*eax = env->cpuid_version;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
2013-04-23 03:00:15 +08:00
|
|
|
*edx = env->features[FEAT_C000_0001_EDX];
|
2011-06-01 09:59:52 +08:00
|
|
|
break;
|
|
|
|
|
case 0xC0000002:
|
|
|
|
|
case 0xC0000003:
|
|
|
|
|
case 0xC0000004:
|
|
|
|
|
/* Reserved for the future, and now filled with zero */
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
break;
|
2018-03-08 20:48:58 +08:00
|
|
|
case 0x8000001F:
|
|
|
|
|
*eax = sev_enabled() ? 0x2 : 0;
|
|
|
|
|
*ebx = sev_get_cbit_position();
|
|
|
|
|
*ebx |= sev_get_reduced_phys_bits() << 6;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
break;
|
2010-03-11 21:38:55 +08:00
|
|
|
default:
|
|
|
|
|
/* reserved values: zero */
|
|
|
|
|
*eax = 0;
|
|
|
|
|
*ebx = 0;
|
|
|
|
|
*ecx = 0;
|
|
|
|
|
*edx = 0;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
2012-04-03 05:20:08 +08:00
|
|
|
|
|
|
|
|
/* CPUClass::reset() */
|
|
|
|
|
static void x86_cpu_reset(CPUState *s)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(s);
|
|
|
|
|
X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
2015-07-07 23:13:10 +08:00
|
|
|
target_ulong cr4;
|
|
|
|
|
uint64_t xcr0;
|
2012-04-03 06:16:24 +08:00
|
|
|
int i;
|
|
|
|
|
|
2012-04-03 05:20:08 +08:00
|
|
|
xcc->parent_reset(s);
|
|
|
|
|
|
2015-04-25 02:49:15 +08:00
|
|
|
memset(env, 0, offsetof(CPUX86State, end_reset_fields));
|
2012-04-03 06:16:24 +08:00
|
|
|
|
|
|
|
|
env->old_exception = -1;
|
|
|
|
|
|
|
|
|
|
/* init to reset state */
|
|
|
|
|
|
|
|
|
|
env->hflags2 |= HF2_GIF_MASK;
|
|
|
|
|
|
|
|
|
|
cpu_x86_update_cr0(env, 0x60000010);
|
|
|
|
|
env->a20_mask = ~0x0;
|
|
|
|
|
env->smbase = 0x30000;
|
2018-02-27 18:22:12 +08:00
|
|
|
env->msr_smi_count = 0;
|
2012-04-03 06:16:24 +08:00
|
|
|
|
|
|
|
|
env->idt.limit = 0xffff;
|
|
|
|
|
env->gdt.limit = 0xffff;
|
|
|
|
|
env->ldt.limit = 0xffff;
|
|
|
|
|
env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
|
|
|
|
|
env->tr.limit = 0xffff;
|
|
|
|
|
env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
|
|
|
|
|
|
|
|
|
|
cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
|
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
|
|
|
|
|
DESC_R_MASK | DESC_A_MASK);
|
|
|
|
|
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
|
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
|
|
|
|
|
DESC_A_MASK);
|
|
|
|
|
cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
|
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
|
|
|
|
|
DESC_A_MASK);
|
|
|
|
|
cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
|
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
|
|
|
|
|
DESC_A_MASK);
|
|
|
|
|
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
|
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
|
|
|
|
|
DESC_A_MASK);
|
|
|
|
|
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
|
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
|
|
|
|
|
DESC_A_MASK);
|
|
|
|
|
|
|
|
|
|
env->eip = 0xfff0;
|
|
|
|
|
env->regs[R_EDX] = env->cpuid_version;
|
|
|
|
|
|
|
|
|
|
env->eflags = 0x2;
|
|
|
|
|
|
|
|
|
|
/* FPU init */
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
|
env->fptags[i] = 1;
|
|
|
|
|
}
|
2014-09-17 16:05:19 +08:00
|
|
|
cpu_set_fpuc(env, 0x37f);
|
2012-04-03 06:16:24 +08:00
|
|
|
|
|
|
|
|
env->mxcsr = 0x1f80;
|
2015-07-07 23:13:10 +08:00
|
|
|
/* All units are in INIT state. */
|
|
|
|
|
env->xstate_bv = 0;
|
2012-04-03 06:16:24 +08:00
|
|
|
|
|
|
|
|
env->pat = 0x0007040600070406ULL;
|
|
|
|
|
env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
|
|
|
|
|
|
|
|
|
|
memset(env->dr, 0, sizeof(env->dr));
|
|
|
|
|
env->dr[6] = DR6_FIXED_1;
|
|
|
|
|
env->dr[7] = DR7_FIXED_1;
|
2013-09-02 23:26:20 +08:00
|
|
|
cpu_breakpoint_remove_all(s, BP_CPU);
|
2013-09-02 22:57:02 +08:00
|
|
|
cpu_watchpoint_remove_all(s, BP_CPU);
|
2012-07-23 21:22:27 +08:00
|
|
|
|
2015-07-07 23:13:10 +08:00
|
|
|
cr4 = 0;
|
2016-02-17 17:54:53 +08:00
|
|
|
xcr0 = XSTATE_FP_MASK;
|
2015-07-07 23:13:10 +08:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
|
|
|
/* Enable all the features for user-mode. */
|
|
|
|
|
if (env->features[FEAT_1_EDX] & CPUID_SSE) {
|
2016-02-17 17:54:53 +08:00
|
|
|
xcr0 |= XSTATE_SSE_MASK;
|
2015-07-07 23:13:10 +08:00
|
|
|
}
|
2016-02-09 21:14:28 +08:00
|
|
|
for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
|
|
|
|
|
const ExtSaveArea *esa = &x86_ext_save_areas[i];
|
2016-09-23 05:58:39 +08:00
|
|
|
if (env->features[esa->feature] & esa->bits) {
|
2016-02-09 21:14:28 +08:00
|
|
|
xcr0 |= 1ull << i;
|
|
|
|
|
}
|
2015-07-07 23:13:10 +08:00
|
|
|
}
|
2016-02-09 21:14:28 +08:00
|
|
|
|
2015-07-07 23:13:10 +08:00
|
|
|
if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
|
|
|
|
|
cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
|
|
|
|
|
}
|
2015-11-18 19:55:47 +08:00
|
|
|
if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
|
|
|
|
|
cr4 |= CR4_FSGSBASE_MASK;
|
|
|
|
|
}
|
2015-07-07 23:13:10 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
env->xcr0 = xcr0;
|
|
|
|
|
cpu_x86_update_cr4(env, cr4);
|
2013-12-06 16:33:01 +08:00
|
|
|
|
2014-08-15 05:39:39 +08:00
|
|
|
/*
|
|
|
|
|
* SDM 11.11.5 requires:
|
|
|
|
|
* - IA32_MTRR_DEF_TYPE MSR.E = 0
|
|
|
|
|
* - IA32_MTRR_PHYSMASKn.V = 0
|
|
|
|
|
* All other bits are undefined. For simplification, zero it all.
|
|
|
|
|
*/
|
|
|
|
|
env->mtrr_deftype = 0;
|
|
|
|
|
memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
|
|
|
|
|
memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
|
|
|
|
|
|
2017-09-13 17:05:21 +08:00
|
|
|
env->interrupt_injected = -1;
|
|
|
|
|
env->exception_injected = -1;
|
|
|
|
|
env->nmi_injected = false;
|
2012-07-23 21:22:27 +08:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
|
/* We hard-wire the BSP to the first CPU. */
|
2015-04-02 07:58:36 +08:00
|
|
|
apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
|
2012-07-23 21:22:27 +08:00
|
|
|
|
2013-01-18 01:51:17 +08:00
|
|
|
s->halted = !cpu_is_bsp(cpu);
|
2013-03-20 20:11:56 +08:00
|
|
|
|
|
|
|
|
if (kvm_enabled()) {
|
|
|
|
|
kvm_arch_reset_vcpu(cpu);
|
|
|
|
|
}
|
2017-09-13 17:05:19 +08:00
|
|
|
else if (hvf_enabled()) {
|
|
|
|
|
hvf_reset_vcpu(s);
|
|
|
|
|
}
|
2012-07-23 21:22:27 +08:00
|
|
|
#endif
|
2012-04-03 05:20:08 +08:00
|
|
|
}
|
|
|
|
|
|
2012-07-23 21:22:27 +08:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
|
bool cpu_is_bsp(X86CPU *cpu)
|
|
|
|
|
{
|
2013-12-23 17:04:02 +08:00
|
|
|
return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
|
2012-07-23 21:22:27 +08:00
|
|
|
}
|
2012-07-23 21:22:28 +08:00
|
|
|
|
|
|
|
|
/* TODO: remove me, when reset over QOM tree is implemented */
|
|
|
|
|
static void x86_cpu_machine_reset_cb(void *opaque)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = opaque;
|
|
|
|
|
cpu_reset(CPU(cpu));
|
|
|
|
|
}
|
2012-07-23 21:22:27 +08:00
|
|
|
#endif
|
|
|
|
|
|
2012-04-03 06:00:17 +08:00
|
|
|
static void mce_init(X86CPU *cpu)
|
|
|
|
|
{
|
|
|
|
|
CPUX86State *cenv = &cpu->env;
|
|
|
|
|
unsigned int bank;
|
|
|
|
|
|
|
|
|
|
if (((cenv->cpuid_version >> 8) & 0xf) >= 6
|
2013-04-23 03:00:15 +08:00
|
|
|
&& (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
|
2012-04-03 06:00:17 +08:00
|
|
|
(CPUID_MCE | CPUID_MCA)) {
|
2016-06-22 14:56:21 +08:00
|
|
|
cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
|
|
|
|
|
(cpu->enable_lmce ? MCG_LMCE_P : 0);
|
2012-04-03 06:00:17 +08:00
|
|
|
cenv->mcg_ctl = ~(uint64_t)0;
|
|
|
|
|
for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
|
|
|
|
|
cenv->mce_banks[bank * 4] = ~(uint64_t)0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2012-10-14 04:35:39 +08:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2016-10-10 23:28:42 +08:00
|
|
|
APICCommonClass *apic_get_class(void)
|
2012-10-14 04:35:39 +08:00
|
|
|
{
|
|
|
|
|
const char *apic_type = "apic";
|
|
|
|
|
|
2017-09-13 17:05:19 +08:00
|
|
|
/* TODO: in-kernel irqchip for hvf */
|
2015-12-18 00:16:08 +08:00
|
|
|
if (kvm_apic_in_kernel()) {
|
2012-10-14 04:35:39 +08:00
|
|
|
apic_type = "kvm-apic";
|
|
|
|
|
} else if (xen_enabled()) {
|
|
|
|
|
apic_type = "xen-apic";
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-10 23:28:42 +08:00
|
|
|
return APIC_COMMON_CLASS(object_class_by_name(apic_type));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
APICCommonState *apic;
|
|
|
|
|
ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
|
|
|
|
|
|
|
|
|
|
cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
|
2012-10-14 04:35:39 +08:00
|
|
|
|
2016-07-06 14:20:52 +08:00
|
|
|
object_property_add_child(OBJECT(cpu), "lapic",
|
|
|
|
|
OBJECT(cpu->apic_state), &error_abort);
|
2016-07-06 14:20:53 +08:00
|
|
|
object_unref(OBJECT(cpu->apic_state));
|
2016-07-06 14:20:52 +08:00
|
|
|
|
2016-10-19 20:05:35 +08:00
|
|
|
qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
|
2012-10-14 04:35:39 +08:00
|
|
|
/* TODO: convert to link<> */
|
2013-12-23 17:04:02 +08:00
|
|
|
apic = APIC_COMMON(cpu->apic_state);
|
2012-10-10 20:10:07 +08:00
|
|
|
apic->cpu = cpu;
|
2015-09-16 17:19:11 +08:00
|
|
|
apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
|
2013-04-05 22:36:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
|
|
|
|
|
{
|
2015-09-16 17:19:11 +08:00
|
|
|
APICCommonState *apic;
|
|
|
|
|
static bool apic_mmio_map_once;
|
|
|
|
|
|
2013-12-23 17:04:02 +08:00
|
|
|
if (cpu->apic_state == NULL) {
|
2013-04-05 22:36:54 +08:00
|
|
|
return;
|
|
|
|
|
}
|
2015-02-05 17:29:15 +08:00
|
|
|
object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
|
|
|
|
|
errp);
|
2015-09-16 17:19:11 +08:00
|
|
|
|
|
|
|
|
/* Map APIC MMIO area */
|
|
|
|
|
apic = APIC_COMMON(cpu->apic_state);
|
|
|
|
|
if (!apic_mmio_map_once) {
|
|
|
|
|
memory_region_add_subregion_overlap(get_system_memory(),
|
|
|
|
|
apic->apicbase &
|
|
|
|
|
MSR_IA32_APICBASE_BASE,
|
|
|
|
|
&apic->io_memory,
|
|
|
|
|
0x1000);
|
|
|
|
|
apic_mmio_map_once = true;
|
|
|
|
|
}
|
2012-10-14 04:35:39 +08:00
|
|
|
}
|
2015-03-31 20:12:25 +08:00
|
|
|
|
|
|
|
|
static void x86_cpu_machine_done(Notifier *n, void *unused)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = container_of(n, X86CPU, machine_done);
|
|
|
|
|
MemoryRegion *smram =
|
|
|
|
|
(MemoryRegion *) object_resolve_path("/machine/smram", NULL);
|
|
|
|
|
|
|
|
|
|
if (smram) {
|
|
|
|
|
cpu->smram = g_new(MemoryRegion, 1);
|
|
|
|
|
memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
|
|
|
|
|
smram, 0, 1ull << 32);
|
2017-03-01 17:34:48 +08:00
|
|
|
memory_region_set_enabled(cpu->smram, true);
|
2015-03-31 20:12:25 +08:00
|
|
|
memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
|
|
|
|
|
}
|
|
|
|
|
}
|
2013-04-05 22:36:54 +08:00
|
|
|
#else
|
|
|
|
|
static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
}
|
2012-10-14 04:35:39 +08:00
|
|
|
#endif
|
|
|
|
|
|
2016-07-12 03:28:46 +08:00
|
|
|
/* Note: Only safe for use on x86(-64) hosts */
|
|
|
|
|
static uint32_t x86_host_phys_bits(void)
|
|
|
|
|
{
|
|
|
|
|
uint32_t eax;
|
|
|
|
|
uint32_t host_phys_bits;
|
|
|
|
|
|
|
|
|
|
host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
|
|
|
|
|
if (eax >= 0x80000008) {
|
|
|
|
|
host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
|
|
|
|
|
/* Note: According to AMD doc 25481 rev 2.34 they have a field
|
|
|
|
|
* at 23:16 that can specify a maximum physical address bits for
|
|
|
|
|
* the guest that can override this value; but I've not seen
|
|
|
|
|
* anything with that set.
|
|
|
|
|
*/
|
|
|
|
|
host_phys_bits = eax & 0xff;
|
|
|
|
|
} else {
|
|
|
|
|
/* It's an odd 64 bit machine that doesn't have the leaf for
|
|
|
|
|
* physical address bits; fall back to 36 that's most older
|
|
|
|
|
* Intel.
|
|
|
|
|
*/
|
|
|
|
|
host_phys_bits = 36;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return host_phys_bits;
|
|
|
|
|
}
|
2014-10-21 23:00:45 +08:00
|
|
|
|
2016-09-22 00:30:12 +08:00
|
|
|
static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
|
|
|
|
|
{
|
|
|
|
|
if (*min < value) {
|
|
|
|
|
*min = value;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
|
|
|
|
|
static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
|
|
|
|
|
{
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
FeatureWordInfo *fi = &feature_word_info[w];
|
|
|
|
|
uint32_t eax = fi->cpuid_eax;
|
|
|
|
|
uint32_t region = eax & 0xF0000000;
|
|
|
|
|
|
|
|
|
|
if (!env->features[w]) {
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (region) {
|
|
|
|
|
case 0x00000000:
|
|
|
|
|
x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
|
|
|
|
|
break;
|
|
|
|
|
case 0x80000000:
|
|
|
|
|
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
|
|
|
|
|
break;
|
|
|
|
|
case 0xC0000000:
|
|
|
|
|
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-23 04:27:56 +08:00
|
|
|
/* Calculate XSAVE components based on the configured CPU feature flags */
|
|
|
|
|
static void x86_cpu_enable_xsave_components(X86CPU *cpu)
|
|
|
|
|
{
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
int i;
|
2016-09-23 04:41:35 +08:00
|
|
|
uint64_t mask;
|
2016-09-23 04:27:56 +08:00
|
|
|
|
|
|
|
|
if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-01 02:49:42 +08:00
|
|
|
mask = 0;
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
|
2016-09-23 04:27:56 +08:00
|
|
|
const ExtSaveArea *esa = &x86_ext_save_areas[i];
|
|
|
|
|
if (env->features[esa->feature] & esa->bits) {
|
2016-09-23 04:41:35 +08:00
|
|
|
mask |= (1ULL << i);
|
2016-09-23 04:27:56 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-23 04:41:35 +08:00
|
|
|
env->features[FEAT_XSAVE_COMP_LO] = mask;
|
|
|
|
|
env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
|
2016-09-23 04:27:56 +08:00
|
|
|
}
|
|
|
|
|
|
2017-01-17 05:11:21 +08:00
|
|
|
/***** Steps involved on loading and filtering CPUID data
|
|
|
|
|
*
|
|
|
|
|
* When initializing and realizing a CPU object, the steps
|
|
|
|
|
* involved in setting up CPUID data are:
|
|
|
|
|
*
|
|
|
|
|
* 1) Loading CPU model definition (X86CPUDefinition). This is
|
|
|
|
|
* implemented by x86_cpu_load_def() and should be completely
|
|
|
|
|
* transparent, as it is done automatically by instance_init.
|
|
|
|
|
* No code should need to look at X86CPUDefinition structs
|
|
|
|
|
* outside instance_init.
|
|
|
|
|
*
|
|
|
|
|
* 2) CPU expansion. This is done by realize before CPUID
|
|
|
|
|
* filtering, and will make sure host/accelerator data is
|
|
|
|
|
* loaded for CPU models that depend on host capabilities
|
|
|
|
|
* (e.g. "host"). Done by x86_cpu_expand_features().
|
|
|
|
|
*
|
|
|
|
|
* 3) CPUID filtering. This initializes extra data related to
|
|
|
|
|
* CPUID, and checks if the host supports all capabilities
|
|
|
|
|
* required by the CPU. Runnability of a CPU model is
|
|
|
|
|
* determined at this step. Done by x86_cpu_filter_features().
|
|
|
|
|
*
|
|
|
|
|
* Some operations don't require all steps to be performed.
|
|
|
|
|
* More precisely:
|
|
|
|
|
*
|
|
|
|
|
* - CPU instance creation (instance_init) will run only CPU
|
|
|
|
|
* model loading. CPU expansion can't run at instance_init-time
|
|
|
|
|
* because host/accelerator data may be not available yet.
|
|
|
|
|
* - CPU realization will perform both CPU model expansion and CPUID
|
|
|
|
|
* filtering, and return an error in case one of them fails.
|
|
|
|
|
* - query-cpu-definitions needs to run all 3 steps. It needs
|
|
|
|
|
* to run CPUID filtering, as the 'unavailable-features'
|
|
|
|
|
* field is set based on the filtering results.
|
|
|
|
|
* - The query-cpu-model-expansion QMP command only needs to run
|
|
|
|
|
* CPU model loading and CPU expansion. It should not filter
|
|
|
|
|
* any CPUID data based on host capabilities.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* Expand CPU configuration data, based on configured features
|
|
|
|
|
* and host/accelerator capabilities when appropriate.
|
|
|
|
|
*/
|
|
|
|
|
static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
|
2012-05-10 05:15:32 +08:00
|
|
|
{
|
2012-10-22 23:03:00 +08:00
|
|
|
CPUX86State *env = &cpu->env;
|
2016-06-06 23:16:44 +08:00
|
|
|
FeatureWord w;
|
2016-10-01 02:49:39 +08:00
|
|
|
GList *l;
|
2016-09-29 02:03:26 +08:00
|
|
|
Error *local_err = NULL;
|
2014-12-19 09:31:11 +08:00
|
|
|
|
2017-03-27 22:48:15 +08:00
|
|
|
/*TODO: Now cpu->max_features doesn't overwrite features
|
|
|
|
|
* set using QOM properties, and we can convert
|
2016-06-06 23:16:44 +08:00
|
|
|
* plus_features & minus_features to global properties
|
|
|
|
|
* inside x86_cpu_parse_featurestr() too.
|
|
|
|
|
*/
|
2017-01-20 05:04:46 +08:00
|
|
|
if (cpu->max_features) {
|
2016-06-06 23:16:44 +08:00
|
|
|
for (w = 0; w < FEATURE_WORDS; w++) {
|
2017-03-27 22:48:15 +08:00
|
|
|
/* Override only features that weren't set explicitly
|
|
|
|
|
* by the user.
|
|
|
|
|
*/
|
|
|
|
|
env->features[w] |=
|
|
|
|
|
x86_cpu_get_supported_feature_word(w, cpu->migratable) &
|
|
|
|
|
~env->user_features[w];
|
2016-06-06 23:16:44 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-01 02:49:39 +08:00
|
|
|
for (l = plus_features; l; l = l->next) {
|
|
|
|
|
const char *prop = l->data;
|
|
|
|
|
object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
|
|
|
|
|
if (local_err) {
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (l = minus_features; l; l = l->next) {
|
|
|
|
|
const char *prop = l->data;
|
|
|
|
|
object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
|
|
|
|
|
if (local_err) {
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2016-06-06 23:16:44 +08:00
|
|
|
}
|
|
|
|
|
|
2016-09-27 06:11:14 +08:00
|
|
|
if (!kvm_enabled() || !cpu->expose_kvm) {
|
|
|
|
|
env->features[FEAT_KVM] = 0;
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-23 04:27:56 +08:00
|
|
|
x86_cpu_enable_xsave_components(cpu);
|
2016-09-22 00:30:12 +08:00
|
|
|
|
|
|
|
|
/* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
|
|
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
|
|
|
|
|
if (cpu->full_cpuid_auto_level) {
|
|
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
|
|
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
|
|
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
|
|
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
|
|
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
|
|
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
|
|
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
|
2018-01-09 23:45:16 +08:00
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
|
2016-09-22 00:30:12 +08:00
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
|
|
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
|
|
|
|
|
x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
|
2016-09-22 02:01:35 +08:00
|
|
|
/* SVM requires CPUID[0x8000000A] */
|
|
|
|
|
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
|
|
|
|
|
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
|
|
|
|
|
}
|
2018-03-08 20:48:58 +08:00
|
|
|
|
|
|
|
|
/* SEV requires CPUID[0x8000001F] */
|
|
|
|
|
if (sev_enabled()) {
|
|
|
|
|
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
|
|
|
|
|
}
|
2016-09-22 00:30:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
|
|
|
|
|
if (env->cpuid_level == UINT32_MAX) {
|
|
|
|
|
env->cpuid_level = env->cpuid_min_level;
|
|
|
|
|
}
|
|
|
|
|
if (env->cpuid_xlevel == UINT32_MAX) {
|
|
|
|
|
env->cpuid_xlevel = env->cpuid_min_xlevel;
|
|
|
|
|
}
|
|
|
|
|
if (env->cpuid_xlevel2 == UINT32_MAX) {
|
|
|
|
|
env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
|
2012-10-22 23:03:00 +08:00
|
|
|
}
|
2012-05-10 05:15:32 +08:00
|
|
|
|
2016-09-29 02:03:26 +08:00
|
|
|
out:
|
|
|
|
|
if (local_err != NULL) {
|
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-17 05:11:21 +08:00
|
|
|
/*
|
|
|
|
|
* Finishes initialization of CPUID data, filters CPU feature
|
|
|
|
|
* words based on host availability of each feature.
|
|
|
|
|
*
|
|
|
|
|
* Returns: 0 if all flags are supported by the host, non-zero otherwise.
|
|
|
|
|
*/
|
|
|
|
|
static int x86_cpu_filter_features(X86CPU *cpu)
|
|
|
|
|
{
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
FeatureWord w;
|
|
|
|
|
int rv = 0;
|
|
|
|
|
|
|
|
|
|
for (w = 0; w < FEATURE_WORDS; w++) {
|
|
|
|
|
uint32_t host_feat =
|
|
|
|
|
x86_cpu_get_supported_feature_word(w, false);
|
|
|
|
|
uint32_t requested_features = env->features[w];
|
|
|
|
|
env->features[w] &= host_feat;
|
|
|
|
|
cpu->filtered_features[w] = requested_features & ~env->features[w];
|
|
|
|
|
if (cpu->filtered_features[w]) {
|
|
|
|
|
rv = 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2018-03-05 00:48:35 +08:00
|
|
|
if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
|
|
|
|
|
kvm_enabled()) {
|
|
|
|
|
KVMState *s = CPU(cpu)->kvm_state;
|
|
|
|
|
uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
|
|
|
|
|
uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
|
|
|
|
|
uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
|
|
|
|
|
uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
|
|
|
|
|
uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
|
|
|
|
|
|
|
|
|
|
if (!eax_0 ||
|
|
|
|
|
((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
|
|
|
|
|
((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
|
|
|
|
|
((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
|
|
|
|
|
((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
|
|
|
|
|
INTEL_PT_ADDR_RANGES_NUM) ||
|
|
|
|
|
((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
|
2018-03-14 03:26:31 +08:00
|
|
|
(INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
|
|
|
|
|
(ecx_0 & INTEL_PT_IP_LIP)) {
|
2018-03-05 00:48:35 +08:00
|
|
|
/*
|
|
|
|
|
* Processor Trace capabilities aren't configurable, so if the
|
|
|
|
|
* host can't emulate the capabilities we report on
|
|
|
|
|
* cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
|
|
|
|
|
*/
|
|
|
|
|
env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
|
|
|
|
|
cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
|
|
|
|
|
rv = 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-17 05:11:21 +08:00
|
|
|
return rv;
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-29 02:03:26 +08:00
|
|
|
#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
|
|
|
|
|
(env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
|
|
|
|
|
(env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
|
|
|
|
|
#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
|
|
|
|
|
(env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
|
|
|
|
|
(env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
|
|
|
|
|
static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
CPUState *cs = CPU(dev);
|
|
|
|
|
X86CPU *cpu = X86_CPU(dev);
|
|
|
|
|
X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
Error *local_err = NULL;
|
|
|
|
|
static bool ht_warned;
|
|
|
|
|
|
2017-09-13 17:05:19 +08:00
|
|
|
if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
|
2016-09-29 02:03:26 +08:00
|
|
|
char *name = x86_cpu_class_get_model_name(xcc);
|
|
|
|
|
error_setg(&local_err, "CPU model '%s' requires KVM", name);
|
|
|
|
|
g_free(name);
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cpu->apic_id == UNASSIGNED_APIC_ID) {
|
|
|
|
|
error_setg(errp, "apic-id property was not initialized properly");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-17 05:11:21 +08:00
|
|
|
x86_cpu_expand_features(cpu, &local_err);
|
2016-09-29 02:03:26 +08:00
|
|
|
if (local_err) {
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-05 01:50:46 +08:00
|
|
|
if (x86_cpu_filter_features(cpu) &&
|
|
|
|
|
(cpu->check_cpuid || cpu->enforce_cpuid)) {
|
|
|
|
|
x86_cpu_report_filtered_features(cpu);
|
|
|
|
|
if (cpu->enforce_cpuid) {
|
|
|
|
|
error_setg(&local_err,
|
2017-09-13 17:05:19 +08:00
|
|
|
accel_uses_host_cpuid() ?
|
2016-05-05 01:50:46 +08:00
|
|
|
"Host doesn't support requested features" :
|
|
|
|
|
"TCG doesn't support requested features");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
target-i386: Set AMD alias bits after filtering CPUID data
QEMU complains about -cpu host on an AMD machine:
warning: host doesn't support requested feature: CPUID.80000001H:EDX [bit 0]
For bits 0,1,3,4,5,6,7,8,9,12,13,14,15,16,17,23,24.
KVM_GET_SUPPORTED_CPUID and and x86_cpu_get_migratable_flags()
don't handle the AMD CPUID aliases bits, making
x86_cpu_filter_features() print warnings and clear those CPUID
bits incorrectly.
To avoid hacking x86_cpu_get_migratable_flags() to handle
CPUID_EXT2_AMD_ALIASES (just like the existing hack inside
kvm_arch_get_supported_cpuid()), simply move the
CPUID_EXT2_AMD_ALIASES code in x86_cpu_realizefn() after the
x86_cpu_filter_features() call.
This will probably make the CPUID_EXT2_AMD_ALIASES hack in
kvm_arch_get_supported_cpuid() unnecessary, too. The hack will be
removed in a follow-up patch after v2.6.0.
Reported-by: Radim Krčmář <rkrcmar@redhat.com>
Tested-by: Radim Krčmář <rkrcmar@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-04-16 01:54:26 +08:00
|
|
|
}
|
|
|
|
|
|
2012-12-29 04:01:17 +08:00
|
|
|
/* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
|
|
|
|
|
* CPUID[1].EDX.
|
|
|
|
|
*/
|
2014-10-21 23:00:45 +08:00
|
|
|
if (IS_AMD_CPU(env)) {
|
2013-04-23 03:00:15 +08:00
|
|
|
env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
|
|
|
|
|
env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
|
2012-12-29 04:01:17 +08:00
|
|
|
& CPUID_EXT2_AMD_ALIASES);
|
|
|
|
|
}
|
|
|
|
|
|
2016-07-12 03:28:46 +08:00
|
|
|
/* For 64bit systems think about the number of physical bits to present.
|
|
|
|
|
* ideally this should be the same as the host; anything other than matching
|
|
|
|
|
* the host can cause incorrect guest behaviour.
|
|
|
|
|
* QEMU used to pick the magic value of 40 bits that corresponds to
|
|
|
|
|
* consumer AMD devices but nothing else.
|
|
|
|
|
*/
|
2016-07-08 23:01:36 +08:00
|
|
|
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
|
2017-09-13 17:05:19 +08:00
|
|
|
if (accel_uses_host_cpuid()) {
|
2016-07-12 03:28:46 +08:00
|
|
|
uint32_t host_phys_bits = x86_host_phys_bits();
|
|
|
|
|
static bool warned;
|
|
|
|
|
|
|
|
|
|
if (cpu->host_phys_bits) {
|
|
|
|
|
/* The user asked for us to use the host physical bits */
|
|
|
|
|
cpu->phys_bits = host_phys_bits;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Print a warning if the user set it to a value that's not the
|
|
|
|
|
* host value.
|
|
|
|
|
*/
|
|
|
|
|
if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
|
|
|
|
|
!warned) {
|
2017-07-12 21:57:41 +08:00
|
|
|
warn_report("Host physical bits (%u)"
|
|
|
|
|
" does not match phys-bits property (%u)",
|
|
|
|
|
host_phys_bits, cpu->phys_bits);
|
2016-07-12 03:28:46 +08:00
|
|
|
warned = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cpu->phys_bits &&
|
|
|
|
|
(cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
|
|
|
|
|
cpu->phys_bits < 32)) {
|
2016-07-08 23:01:36 +08:00
|
|
|
error_setg(errp, "phys-bits should be between 32 and %u "
|
|
|
|
|
" (but is %u)",
|
|
|
|
|
TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2016-07-12 03:28:46 +08:00
|
|
|
if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
|
2016-07-08 23:01:36 +08:00
|
|
|
error_setg(errp, "TCG only supports phys-bits=%u",
|
|
|
|
|
TCG_PHYS_ADDR_BITS);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
2016-07-12 03:28:46 +08:00
|
|
|
/* 0 means it was not explicitly set by the user (or by machine
|
|
|
|
|
* compat_props or by the host code above). In this case, the default
|
|
|
|
|
* is the value used by TCG (40).
|
|
|
|
|
*/
|
|
|
|
|
if (cpu->phys_bits == 0) {
|
|
|
|
|
cpu->phys_bits = TCG_PHYS_ADDR_BITS;
|
|
|
|
|
}
|
2016-07-08 23:01:36 +08:00
|
|
|
} else {
|
|
|
|
|
/* For 32 bit systems don't use the user set value, but keep
|
|
|
|
|
* phys_bits consistent with what we tell the guest.
|
|
|
|
|
*/
|
|
|
|
|
if (cpu->phys_bits != 0) {
|
|
|
|
|
error_setg(errp, "phys-bits is not user-configurable in 32 bit");
|
|
|
|
|
return;
|
|
|
|
|
}
|
2014-05-01 00:48:39 +08:00
|
|
|
|
2016-07-08 23:01:36 +08:00
|
|
|
if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
|
|
|
|
|
cpu->phys_bits = 36;
|
|
|
|
|
} else {
|
|
|
|
|
cpu->phys_bits = 32;
|
|
|
|
|
}
|
|
|
|
|
}
|
2016-10-20 19:26:03 +08:00
|
|
|
cpu_exec_realizefn(cs, &local_err);
|
|
|
|
|
if (local_err != NULL) {
|
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2015-02-13 09:04:50 +08:00
|
|
|
|
2012-07-23 21:22:28 +08:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
|
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
|
2012-10-14 04:35:39 +08:00
|
|
|
|
2013-04-23 03:00:15 +08:00
|
|
|
if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
|
2013-04-05 22:36:54 +08:00
|
|
|
x86_cpu_apic_create(cpu, &local_err);
|
2013-01-16 10:41:47 +08:00
|
|
|
if (local_err != NULL) {
|
2013-04-05 22:36:53 +08:00
|
|
|
goto out;
|
2012-10-14 04:35:39 +08:00
|
|
|
}
|
|
|
|
|
}
|
2012-07-23 21:22:28 +08:00
|
|
|
#endif
|
|
|
|
|
|
2012-05-10 05:15:32 +08:00
|
|
|
mce_init(cpu);
|
2015-03-31 20:11:09 +08:00
|
|
|
|
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
|
if (tcg_enabled()) {
|
2015-03-31 20:12:25 +08:00
|
|
|
cpu->cpu_as_mem = g_new(MemoryRegion, 1);
|
2015-03-31 20:11:09 +08:00
|
|
|
cpu->cpu_as_root = g_new(MemoryRegion, 1);
|
2015-03-31 20:12:25 +08:00
|
|
|
|
|
|
|
|
/* Outer container... */
|
|
|
|
|
memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
|
2015-03-31 20:11:09 +08:00
|
|
|
memory_region_set_enabled(cpu->cpu_as_root, true);
|
2015-03-31 20:12:25 +08:00
|
|
|
|
|
|
|
|
/* ... with two regions inside: normal system memory with low
|
|
|
|
|
* priority, and...
|
|
|
|
|
*/
|
|
|
|
|
memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
|
|
|
|
|
get_system_memory(), 0, ~0ull);
|
|
|
|
|
memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
|
|
|
|
|
memory_region_set_enabled(cpu->cpu_as_mem, true);
|
2017-03-01 17:34:48 +08:00
|
|
|
|
|
|
|
|
cs->num_ases = 2;
|
2017-11-23 17:23:32 +08:00
|
|
|
cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
|
|
|
|
|
cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
|
2015-03-31 20:12:25 +08:00
|
|
|
|
|
|
|
|
/* ... SMRAM with higher priority, linked from /machine/smram. */
|
|
|
|
|
cpu->machine_done.notify = x86_cpu_machine_done;
|
|
|
|
|
qemu_add_machine_init_done_notifier(&cpu->machine_done);
|
2015-03-31 20:11:09 +08:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2013-07-27 08:53:25 +08:00
|
|
|
qemu_init_vcpu(cs);
|
2013-04-05 22:36:54 +08:00
|
|
|
|
2014-10-21 23:00:45 +08:00
|
|
|
/* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
|
|
|
|
|
* issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
|
|
|
|
|
* based on inputs (sockets,cores,threads), it is still better to gives
|
|
|
|
|
* users a warning.
|
|
|
|
|
*
|
|
|
|
|
* NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
|
|
|
|
|
* cs->nr_threads hasn't be populated yet and the checking is incorrect.
|
|
|
|
|
*/
|
|
|
|
|
if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
|
|
|
|
|
error_report("AMD CPU doesn't support hyperthreading. Please configure"
|
|
|
|
|
" -smp options properly.");
|
|
|
|
|
ht_warned = true;
|
|
|
|
|
}
|
|
|
|
|
|
2013-04-05 22:36:54 +08:00
|
|
|
x86_cpu_apic_realize(cpu, &local_err);
|
|
|
|
|
if (local_err != NULL) {
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2013-07-27 08:53:25 +08:00
|
|
|
cpu_reset(cs);
|
2013-01-16 10:41:47 +08:00
|
|
|
|
2013-04-05 22:36:53 +08:00
|
|
|
xcc->parent_realize(dev, &local_err);
|
2015-03-31 20:11:09 +08:00
|
|
|
|
2013-04-05 22:36:53 +08:00
|
|
|
out:
|
|
|
|
|
if (local_err != NULL) {
|
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2012-05-10 05:15:32 +08:00
|
|
|
}
|
|
|
|
|
|
2016-06-24 22:01:02 +08:00
|
|
|
static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(dev);
|
2016-10-20 19:26:04 +08:00
|
|
|
X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
|
|
|
|
|
Error *local_err = NULL;
|
2016-06-24 22:01:02 +08:00
|
|
|
|
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
|
cpu_remove_sync(CPU(dev));
|
|
|
|
|
qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
if (cpu->apic_state) {
|
|
|
|
|
object_unparent(OBJECT(cpu->apic_state));
|
|
|
|
|
cpu->apic_state = NULL;
|
|
|
|
|
}
|
2016-10-20 19:26:04 +08:00
|
|
|
|
|
|
|
|
xcc->parent_unrealize(dev, &local_err);
|
|
|
|
|
if (local_err != NULL) {
|
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2016-06-24 22:01:02 +08:00
|
|
|
}
|
|
|
|
|
|
2015-03-24 04:29:32 +08:00
|
|
|
typedef struct BitProperty {
|
2017-03-27 22:48:14 +08:00
|
|
|
FeatureWord w;
|
2015-03-24 04:29:32 +08:00
|
|
|
uint32_t mask;
|
|
|
|
|
} BitProperty;
|
|
|
|
|
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
|
|
|
|
|
void *opaque, Error **errp)
|
2015-03-24 04:29:32 +08:00
|
|
|
{
|
2017-03-27 22:48:14 +08:00
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
2015-03-24 04:29:32 +08:00
|
|
|
BitProperty *fp = opaque;
|
2017-03-27 22:48:14 +08:00
|
|
|
uint32_t f = cpu->env.features[fp->w];
|
|
|
|
|
bool value = (f & fp->mask) == fp->mask;
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_bool(v, name, &value, errp);
|
2015-03-24 04:29:32 +08:00
|
|
|
}
|
|
|
|
|
|
qom: Swap 'name' next to visitor in ObjectPropertyAccessor
Similar to the previous patch, it's nice to have all functions
in the tree that involve a visitor and a name for conversion to
or from QAPI to consistently stick the 'name' parameter next
to the Visitor parameter.
Done by manually changing include/qom/object.h and qom/object.c,
then running this Coccinelle script and touching up the fallout
(Coccinelle insisted on adding some trailing whitespace).
@ rule1 @
identifier fn;
typedef Object, Visitor, Error;
identifier obj, v, opaque, name, errp;
@@
void fn
- (Object *obj, Visitor *v, void *opaque, const char *name,
+ (Object *obj, Visitor *v, const char *name, void *opaque,
Error **errp) { ... }
@@
identifier rule1.fn;
expression obj, v, opaque, name, errp;
@@
fn(obj, v,
- opaque, name,
+ name, opaque,
errp)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-20-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:55 +08:00
|
|
|
static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
|
|
|
|
|
void *opaque, Error **errp)
|
2015-03-24 04:29:32 +08:00
|
|
|
{
|
|
|
|
|
DeviceState *dev = DEVICE(obj);
|
2017-03-27 22:48:14 +08:00
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
2015-03-24 04:29:32 +08:00
|
|
|
BitProperty *fp = opaque;
|
|
|
|
|
Error *local_err = NULL;
|
|
|
|
|
bool value;
|
|
|
|
|
|
|
|
|
|
if (dev->realized) {
|
|
|
|
|
qdev_prop_set_after_realize(dev, name, errp);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
qapi: Swap visit_* arguments for consistent 'name' placement
JSON uses "name":value, but many of our visitor interfaces were
called with visit_type_FOO(v, &value, name, errp). This can be
a bit confusing to have to mentally swap the parameter order to
match JSON order. It's particularly bad for visit_start_struct(),
where the 'name' parameter is smack in the middle of the
otherwise-related group of 'obj, kind, size' parameters! It's
time to do a global swap of the parameter ordering, so that the
'name' parameter is always immediately after the Visitor argument.
Additional reason in favor of the swap: the existing include/qjson.h
prefers listing 'name' first in json_prop_*(), and I have plans to
unify that file with the qapi visitors; listing 'name' first in
qapi will minimize churn to the (admittedly few) qjson.h clients.
Later patches will then fix docs, object.h, visitor-impl.h, and
those clients to match.
Done by first patching scripts/qapi*.py by hand to make generated
files do what I want, then by running the following Coccinelle
script to affect the rest of the code base:
$ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'`
I then had to apply some touchups (Coccinelle insisted on TAB
indentation in visitor.h, and botched the signature of
visit_type_enum() by rewriting 'const char *const strings[]' to
the syntactically invalid 'const char*const[] strings'). The
movement of parameters is sufficient to provoke compiler errors
if any callers were missed.
// Part 1: Swap declaration order
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_start_struct
-(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type bool, TV, T1;
identifier ARG1;
@@
bool visit_optional
-(TV v, T1 ARG1, const char *name)
+(TV v, const char *name, T1 ARG1)
{ ... }
@@
type TV, TErr, TObj, T1;
identifier OBJ, ARG1;
@@
void visit_get_next_type
-(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp)
{ ... }
@@
type TV, TErr, TObj, T1, T2;
identifier OBJ, ARG1, ARG2;
@@
void visit_type_enum
-(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp)
{ ... }
@@
type TV, TErr, TObj;
identifier OBJ;
identifier VISIT_TYPE =~ "^visit_type_";
@@
void VISIT_TYPE
-(TV v, TObj OBJ, const char *name, TErr errp)
+(TV v, const char *name, TObj OBJ, TErr errp)
{ ... }
// Part 2: swap caller order
@@
expression V, NAME, OBJ, ARG1, ARG2, ERR;
identifier VISIT_TYPE =~ "^visit_type_";
@@
(
-visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR)
+visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-visit_optional(V, ARG1, NAME)
+visit_optional(V, NAME, ARG1)
|
-visit_get_next_type(V, OBJ, ARG1, NAME, ERR)
+visit_get_next_type(V, NAME, OBJ, ARG1, ERR)
|
-visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR)
+visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR)
|
-VISIT_TYPE(V, OBJ, NAME, ERR)
+VISIT_TYPE(V, NAME, OBJ, ERR)
)
Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <1454075341-13658-19-git-send-email-eblake@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2016-01-29 21:48:54 +08:00
|
|
|
visit_type_bool(v, name, &value, &local_err);
|
2015-03-24 04:29:32 +08:00
|
|
|
if (local_err) {
|
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (value) {
|
2017-03-27 22:48:14 +08:00
|
|
|
cpu->env.features[fp->w] |= fp->mask;
|
2015-03-24 04:29:32 +08:00
|
|
|
} else {
|
2017-03-27 22:48:14 +08:00
|
|
|
cpu->env.features[fp->w] &= ~fp->mask;
|
2015-03-24 04:29:32 +08:00
|
|
|
}
|
2017-03-27 22:48:15 +08:00
|
|
|
cpu->env.user_features[fp->w] |= fp->mask;
|
2015-03-24 04:29:32 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void x86_cpu_release_bit_prop(Object *obj, const char *name,
|
|
|
|
|
void *opaque)
|
|
|
|
|
{
|
|
|
|
|
BitProperty *prop = opaque;
|
|
|
|
|
g_free(prop);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Register a boolean property to get/set a single bit in a uint32_t field.
|
|
|
|
|
*
|
|
|
|
|
* The same property name can be registered multiple times to make it affect
|
|
|
|
|
* multiple bits in the same FeatureWord. In that case, the getter will return
|
|
|
|
|
* true only if all bits are set.
|
|
|
|
|
*/
|
|
|
|
|
static void x86_cpu_register_bit_prop(X86CPU *cpu,
|
|
|
|
|
const char *prop_name,
|
2017-03-27 22:48:14 +08:00
|
|
|
FeatureWord w,
|
2015-03-24 04:29:32 +08:00
|
|
|
int bitnr)
|
|
|
|
|
{
|
|
|
|
|
BitProperty *fp;
|
|
|
|
|
ObjectProperty *op;
|
|
|
|
|
uint32_t mask = (1UL << bitnr);
|
|
|
|
|
|
|
|
|
|
op = object_property_find(OBJECT(cpu), prop_name, NULL);
|
|
|
|
|
if (op) {
|
|
|
|
|
fp = op->opaque;
|
2017-03-27 22:48:14 +08:00
|
|
|
assert(fp->w == w);
|
2015-03-24 04:29:32 +08:00
|
|
|
fp->mask |= mask;
|
|
|
|
|
} else {
|
|
|
|
|
fp = g_new0(BitProperty, 1);
|
2017-03-27 22:48:14 +08:00
|
|
|
fp->w = w;
|
2015-03-24 04:29:32 +08:00
|
|
|
fp->mask = mask;
|
|
|
|
|
object_property_add(OBJECT(cpu), prop_name, "bool",
|
|
|
|
|
x86_cpu_get_bit_prop,
|
|
|
|
|
x86_cpu_set_bit_prop,
|
|
|
|
|
x86_cpu_release_bit_prop, fp, &error_abort);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
|
|
|
|
|
FeatureWord w,
|
|
|
|
|
int bitnr)
|
|
|
|
|
{
|
|
|
|
|
FeatureWordInfo *fi = &feature_word_info[w];
|
2016-10-01 02:49:41 +08:00
|
|
|
const char *name = fi->feat_names[bitnr];
|
2015-03-24 04:29:32 +08:00
|
|
|
|
2016-10-01 02:49:41 +08:00
|
|
|
if (!name) {
|
2015-03-24 04:29:32 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-01 02:49:40 +08:00
|
|
|
/* Property names should use "-" instead of "_".
|
|
|
|
|
* Old names containing underscores are registered as aliases
|
|
|
|
|
* using object_property_add_alias()
|
|
|
|
|
*/
|
2016-10-01 02:49:41 +08:00
|
|
|
assert(!strchr(name, '_'));
|
|
|
|
|
/* aliases don't use "|" delimiters anymore, they are registered
|
|
|
|
|
* manually using object_property_add_alias() */
|
|
|
|
|
assert(!strchr(name, '|'));
|
2017-03-27 22:48:14 +08:00
|
|
|
x86_cpu_register_bit_prop(cpu, name, w, bitnr);
|
2015-03-24 04:29:32 +08:00
|
|
|
}
|
|
|
|
|
|
2017-02-14 14:25:22 +08:00
|
|
|
static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
GuestPanicInformation *panic_info = NULL;
|
|
|
|
|
|
2017-07-14 04:15:21 +08:00
|
|
|
if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
|
2017-02-14 14:25:22 +08:00
|
|
|
panic_info = g_malloc0(sizeof(GuestPanicInformation));
|
|
|
|
|
|
2017-02-21 02:21:54 +08:00
|
|
|
panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
|
2017-02-14 14:25:22 +08:00
|
|
|
|
2017-07-14 04:15:21 +08:00
|
|
|
assert(HV_CRASH_PARAMS >= 5);
|
2017-02-21 02:21:54 +08:00
|
|
|
panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
|
|
|
|
|
panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
|
|
|
|
|
panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
|
|
|
|
|
panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
|
|
|
|
|
panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
|
2017-02-14 14:25:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return panic_info;
|
|
|
|
|
}
|
|
|
|
|
static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
|
|
|
|
|
const char *name, void *opaque,
|
|
|
|
|
Error **errp)
|
|
|
|
|
{
|
|
|
|
|
CPUState *cs = CPU(obj);
|
|
|
|
|
GuestPanicInformation *panic_info;
|
|
|
|
|
|
|
|
|
|
if (!cs->crash_occurred) {
|
|
|
|
|
error_setg(errp, "No crash occured");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
panic_info = x86_cpu_get_crash_info(cs);
|
|
|
|
|
if (panic_info == NULL) {
|
|
|
|
|
error_setg(errp, "No crash information");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
|
|
|
|
|
errp);
|
|
|
|
|
qapi_free_GuestPanicInformation(panic_info);
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-03 06:00:17 +08:00
|
|
|
static void x86_cpu_initfn(Object *obj)
|
|
|
|
|
{
|
2012-12-17 13:18:02 +08:00
|
|
|
CPUState *cs = CPU(obj);
|
2012-04-03 06:00:17 +08:00
|
|
|
X86CPU *cpu = X86_CPU(obj);
|
2014-02-10 18:21:30 +08:00
|
|
|
X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
|
2012-04-03 06:00:17 +08:00
|
|
|
CPUX86State *env = &cpu->env;
|
2015-03-24 04:29:32 +08:00
|
|
|
FeatureWord w;
|
2012-04-03 06:00:17 +08:00
|
|
|
|
2013-01-17 19:13:41 +08:00
|
|
|
cs->env_ptr = env;
|
2012-04-17 18:10:29 +08:00
|
|
|
|
|
|
|
|
object_property_add(obj, "family", "int",
|
2012-04-17 20:42:22 +08:00
|
|
|
x86_cpuid_version_get_family,
|
2012-04-17 18:10:29 +08:00
|
|
|
x86_cpuid_version_set_family, NULL, NULL, NULL);
|
2012-04-17 18:16:39 +08:00
|
|
|
object_property_add(obj, "model", "int",
|
2012-04-17 20:48:14 +08:00
|
|
|
x86_cpuid_version_get_model,
|
2012-04-17 18:16:39 +08:00
|
|
|
x86_cpuid_version_set_model, NULL, NULL, NULL);
|
2012-04-17 20:14:18 +08:00
|
|
|
object_property_add(obj, "stepping", "int",
|
2012-04-17 20:50:53 +08:00
|
|
|
x86_cpuid_version_get_stepping,
|
2012-04-17 20:14:18 +08:00
|
|
|
x86_cpuid_version_set_stepping, NULL, NULL, NULL);
|
2012-04-18 01:22:58 +08:00
|
|
|
object_property_add_str(obj, "vendor",
|
|
|
|
|
x86_cpuid_get_vendor,
|
|
|
|
|
x86_cpuid_set_vendor, NULL);
|
2012-04-17 21:17:27 +08:00
|
|
|
object_property_add_str(obj, "model-id",
|
2012-04-18 05:02:26 +08:00
|
|
|
x86_cpuid_get_model_id,
|
2012-04-17 21:17:27 +08:00
|
|
|
x86_cpuid_set_model_id, NULL);
|
2012-04-18 06:12:23 +08:00
|
|
|
object_property_add(obj, "tsc-frequency", "int",
|
|
|
|
|
x86_cpuid_get_tsc_freq,
|
|
|
|
|
x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
|
2013-05-07 00:20:07 +08:00
|
|
|
object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
|
|
|
|
|
x86_cpu_get_feature_words,
|
2013-05-07 00:20:09 +08:00
|
|
|
NULL, NULL, (void *)env->features, NULL);
|
|
|
|
|
object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
|
|
|
|
|
x86_cpu_get_feature_words,
|
|
|
|
|
NULL, NULL, (void *)cpu->filtered_features, NULL);
|
2012-04-17 18:10:29 +08:00
|
|
|
|
2017-02-14 14:25:22 +08:00
|
|
|
object_property_add(obj, "crash-information", "GuestPanicInformation",
|
|
|
|
|
x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
|
|
|
|
|
|
2013-06-05 21:18:40 +08:00
|
|
|
cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
|
2012-06-19 21:39:46 +08:00
|
|
|
|
2015-03-24 04:29:32 +08:00
|
|
|
for (w = 0; w < FEATURE_WORDS; w++) {
|
|
|
|
|
int bitnr;
|
|
|
|
|
|
|
|
|
|
for (bitnr = 0; bitnr < 32; bitnr++) {
|
|
|
|
|
x86_cpu_register_feature_bit_props(cpu, w, bitnr);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-10-01 02:49:41 +08:00
|
|
|
object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
|
|
|
|
|
|
2016-10-01 02:49:38 +08:00
|
|
|
object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
|
|
|
|
|
object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
|
|
|
|
|
|
2017-02-23 02:39:19 +08:00
|
|
|
if (xcc->cpu_def) {
|
|
|
|
|
x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
|
|
|
|
|
}
|
2012-04-03 06:00:17 +08:00
|
|
|
}
|
|
|
|
|
|
2013-04-23 16:29:41 +08:00
|
|
|
static int64_t x86_cpu_get_arch_id(CPUState *cs)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
|
|
2014-12-19 09:20:10 +08:00
|
|
|
return cpu->apic_id;
|
2013-04-23 16:29:41 +08:00
|
|
|
}
|
|
|
|
|
|
2013-05-28 19:28:38 +08:00
|
|
|
static bool x86_cpu_get_paging_enabled(const CPUState *cs)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
|
|
|
|
|
|
return cpu->env.cr[0] & CR0_PG_MASK;
|
|
|
|
|
}
|
|
|
|
|
|
2013-06-22 01:09:18 +08:00
|
|
|
static void x86_cpu_set_pc(CPUState *cs, vaddr value)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
|
|
|
|
|
|
cpu->env.eip = value;
|
|
|
|
|
}
|
|
|
|
|
|
2013-06-29 01:31:32 +08:00
|
|
|
static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
|
|
|
|
|
|
cpu->env.eip = tb->pc - tb->cs_base;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-26 00:53:55 +08:00
|
|
|
static bool x86_cpu_has_work(CPUState *cs)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
|
2015-09-18 00:23:31 +08:00
|
|
|
return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
|
|
|
|
|
CPU_INTERRUPT_POLL)) &&
|
2013-08-26 00:53:55 +08:00
|
|
|
(env->eflags & IF_MASK)) ||
|
|
|
|
|
(cs->interrupt_request & (CPU_INTERRUPT_NMI |
|
|
|
|
|
CPU_INTERRUPT_INIT |
|
|
|
|
|
CPU_INTERRUPT_SIPI |
|
2015-05-19 19:46:47 +08:00
|
|
|
CPU_INTERRUPT_MCE)) ||
|
|
|
|
|
((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
|
|
|
|
|
!(env->hflags & HF_SMM_MASK));
|
2013-08-26 00:53:55 +08:00
|
|
|
}
|
|
|
|
|
|
2017-09-14 23:10:53 +08:00
|
|
|
static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
|
|
|
|
|
{
|
|
|
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
|
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
|
|
|
|
|
|
info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
|
|
|
|
|
: env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
|
|
|
|
|
: bfd_mach_i386_i8086);
|
|
|
|
|
info->print_insn = print_insn_i386;
|
2017-09-15 00:50:05 +08:00
|
|
|
|
|
|
|
|
info->cap_arch = CS_ARCH_X86;
|
|
|
|
|
info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
|
|
|
|
|
: env->hflags & HF_CS32_MASK ? CS_MODE_32
|
|
|
|
|
: CS_MODE_16);
|
2017-11-07 20:19:18 +08:00
|
|
|
info->cap_insn_unit = 1;
|
|
|
|
|
info->cap_insn_split = 8;
|
2017-09-14 23:10:53 +08:00
|
|
|
}
|
|
|
|
|
|
2018-01-11 03:50:54 +08:00
|
|
|
void x86_update_hflags(CPUX86State *env)
|
|
|
|
|
{
|
|
|
|
|
uint32_t hflags;
|
|
|
|
|
#define HFLAG_COPY_MASK \
|
|
|
|
|
~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
|
|
|
|
|
HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
|
|
|
|
|
HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
|
|
|
|
|
HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
|
|
|
|
|
|
|
|
|
|
hflags = env->hflags & HFLAG_COPY_MASK;
|
|
|
|
|
hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
|
|
|
|
|
hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
|
|
|
|
|
hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
|
|
|
|
|
(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
|
|
|
|
|
hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
|
|
|
|
|
|
|
|
|
|
if (env->cr[4] & CR4_OSFXSR_MASK) {
|
|
|
|
|
hflags |= HF_OSFXSR_MASK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (env->efer & MSR_EFER_LMA) {
|
|
|
|
|
hflags |= HF_LMA_MASK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
|
|
|
|
|
hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
|
|
|
|
|
} else {
|
|
|
|
|
hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
|
|
|
|
|
(DESC_B_SHIFT - HF_CS32_SHIFT);
|
|
|
|
|
hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
|
|
|
|
|
(DESC_B_SHIFT - HF_SS32_SHIFT);
|
|
|
|
|
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
|
|
|
|
|
!(hflags & HF_CS32_MASK)) {
|
|
|
|
|
hflags |= HF_ADDSEG_MASK;
|
|
|
|
|
} else {
|
|
|
|
|
hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
|
|
|
|
|
env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
env->hflags = hflags;
|
|
|
|
|
}
|
|
|
|
|
|
2013-07-27 04:09:36 +08:00
|
|
|
static Property x86_cpu_properties[] = {
|
2016-07-06 14:20:41 +08:00
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
|
|
|
/* apic_id = 0 by default for *-user, see commit 9886e834 */
|
|
|
|
|
DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
|
2016-07-06 14:20:42 +08:00
|
|
|
DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
|
|
|
|
|
DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
|
|
|
|
|
DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
|
2016-07-06 14:20:41 +08:00
|
|
|
#else
|
|
|
|
|
DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
|
2016-07-06 14:20:42 +08:00
|
|
|
DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
|
|
|
|
|
DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
|
|
|
|
|
DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
|
2016-07-06 14:20:41 +08:00
|
|
|
#endif
|
2017-05-31 00:24:00 +08:00
|
|
|
DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
|
2013-07-27 04:09:36 +08:00
|
|
|
DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
|
2013-06-04 21:05:25 +08:00
|
|
|
{ .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
|
2012-08-08 19:52:51 +08:00
|
|
|
DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
|
2012-08-08 19:54:27 +08:00
|
|
|
DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
|
2014-01-23 21:40:49 +08:00
|
|
|
DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
|
2015-09-09 20:41:30 +08:00
|
|
|
DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
|
2015-09-16 17:59:42 +08:00
|
|
|
DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
|
2015-09-16 17:59:43 +08:00
|
|
|
DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
|
2015-09-16 17:59:44 +08:00
|
|
|
DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
|
2015-11-11 18:18:38 +08:00
|
|
|
DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
|
2015-11-25 23:21:25 +08:00
|
|
|
DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
|
2018-03-31 01:02:08 +08:00
|
|
|
DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
|
2015-08-27 00:25:44 +08:00
|
|
|
DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
|
2013-06-04 21:13:14 +08:00
|
|
|
DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
|
2014-06-03 01:28:50 +08:00
|
|
|
DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
|
2016-07-08 23:01:36 +08:00
|
|
|
DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
|
2016-07-12 03:28:46 +08:00
|
|
|
DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
|
2016-07-08 23:01:38 +08:00
|
|
|
DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
|
2016-09-22 00:30:12 +08:00
|
|
|
DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
|
|
|
|
|
DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
|
|
|
|
|
DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
|
|
|
|
|
DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
|
|
|
|
|
DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
|
|
|
|
|
DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
|
|
|
|
|
DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
|
2015-10-16 23:38:22 +08:00
|
|
|
DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
|
2016-05-13 01:24:26 +08:00
|
|
|
DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
|
2016-06-22 14:56:21 +08:00
|
|
|
DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
|
target-i386: present virtual L3 cache info for vcpus
Some software algorithms are based on the hardware's cache info, for example,
for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger
a resched IPI and told cpu2 to do the wakeup if they don't share low level
cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc.
The relevant linux-kernel code as bellow:
static void ttwu_queue(struct task_struct *p, int cpu)
{
struct rq *rq = cpu_rq(cpu);
......
if (... && !cpus_share_cache(smp_processor_id(), cpu)) {
......
ttwu_queue_remote(p, cpu); /* will trigger RES IPI */
return;
}
......
ttwu_do_activate(rq, p, 0); /* access target's rq directly */
......
}
In real hardware, the cpus on the same socket share L3 cache, so one won't
trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a
virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs
under some workloads even if the virtual cpus belongs to the same virtual socket.
For KVM, there will be lots of vmexit due to guest send IPIs.
The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates)
and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during
the period:
No-L3 With-L3(applied this patch)
cpu0: 363890 44582
cpu1: 373405 43109
cpu2: 340783 43797
cpu3: 333854 43409
cpu4: 327170 40038
cpu5: 325491 39922
cpu6: 319129 42391
cpu7: 306480 41035
cpu8: 161139 32188
cpu9: 164649 31024
cpu10: 149823 30398
cpu11: 149823 32455
cpu12: 164830 35143
cpu13: 172269 35805
cpu14: 179979 33898
cpu15: 194505 32754
avg: 268963.6 40129.8
The VM's topology is "1*socket 8*cores 2*threads".
After present virtual L3 cache info for VM, the amounts of RES IPIs in guest
reduce 85%.
For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause
severe performance degradation. We had tested the overall system performance if
vcpus actually run on sparate physical socket. With L3 cache, the performance
improves 7.2%~33.1%(avg:15.7%).
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-09-07 13:21:13 +08:00
|
|
|
DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
|
2017-02-23 21:34:41 +08:00
|
|
|
DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
|
|
|
|
|
false),
|
2017-01-20 22:11:36 +08:00
|
|
|
DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
|
2017-05-09 21:27:36 +08:00
|
|
|
DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
|
2017-09-11 23:20:27 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* From "Requirements for Implementing the Microsoft
|
|
|
|
|
* Hypervisor Interface":
|
|
|
|
|
* https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
|
|
|
|
|
*
|
|
|
|
|
* "Starting with Windows Server 2012 and Windows 8, if
|
|
|
|
|
* CPUID.40000005.EAX contains a value of -1, Windows assumes that
|
|
|
|
|
* the hypervisor imposes no specific limit to the number of VPs.
|
|
|
|
|
* In this case, Windows Server 2012 guest VMs may use more than
|
|
|
|
|
* 64 VPs, up to the maximum supported number of processors applicable
|
|
|
|
|
* to the specific Windows version being used."
|
|
|
|
|
*/
|
|
|
|
|
DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
|
2013-07-27 04:09:36 +08:00
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
|
};
|
|
|
|
|
|
2012-04-03 05:20:08 +08:00
|
|
|
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
|
|
|
|
|
{
|
|
|
|
|
X86CPUClass *xcc = X86_CPU_CLASS(oc);
|
|
|
|
|
CPUClass *cc = CPU_CLASS(oc);
|
2013-01-16 10:41:47 +08:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
2018-01-14 10:04:12 +08:00
|
|
|
device_class_set_parent_realize(dc, x86_cpu_realizefn,
|
|
|
|
|
&xcc->parent_realize);
|
|
|
|
|
device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
|
|
|
|
|
&xcc->parent_unrealize);
|
2013-07-27 04:09:36 +08:00
|
|
|
dc->props = x86_cpu_properties;
|
2012-04-03 05:20:08 +08:00
|
|
|
|
|
|
|
|
xcc->parent_reset = cc->reset;
|
|
|
|
|
cc->reset = x86_cpu_reset;
|
2013-06-16 13:49:48 +08:00
|
|
|
cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
|
2013-02-02 20:38:08 +08:00
|
|
|
|
2014-02-11 05:02:44 +08:00
|
|
|
cc->class_by_name = x86_cpu_class_by_name;
|
2014-03-04 06:19:19 +08:00
|
|
|
cc->parse_features = x86_cpu_parse_featurestr;
|
2013-08-26 00:53:55 +08:00
|
|
|
cc->has_work = x86_cpu_has_work;
|
2017-07-03 18:12:22 +08:00
|
|
|
#ifdef CONFIG_TCG
|
2013-02-02 17:57:51 +08:00
|
|
|
cc->do_interrupt = x86_cpu_do_interrupt;
|
2014-09-14 00:45:33 +08:00
|
|
|
cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
|
2017-07-03 18:12:22 +08:00
|
|
|
#endif
|
2013-05-27 07:33:50 +08:00
|
|
|
cc->dump_state = x86_cpu_dump_state;
|
2017-02-14 14:25:23 +08:00
|
|
|
cc->get_crash_info = x86_cpu_get_crash_info;
|
2013-06-22 01:09:18 +08:00
|
|
|
cc->set_pc = x86_cpu_set_pc;
|
2013-06-29 01:31:32 +08:00
|
|
|
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
|
2013-06-29 10:18:45 +08:00
|
|
|
cc->gdb_read_register = x86_cpu_gdb_read_register;
|
|
|
|
|
cc->gdb_write_register = x86_cpu_gdb_write_register;
|
2013-05-28 19:28:38 +08:00
|
|
|
cc->get_arch_id = x86_cpu_get_arch_id;
|
|
|
|
|
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
|
2013-08-26 09:01:33 +08:00
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
|
|
|
cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
|
|
|
|
|
#else
|
2017-03-01 17:34:48 +08:00
|
|
|
cc->asidx_from_attrs = x86_asidx_from_attrs;
|
2013-05-28 19:52:01 +08:00
|
|
|
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
|
2013-06-30 00:55:54 +08:00
|
|
|
cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
|
2013-04-19 22:45:06 +08:00
|
|
|
cc->write_elf64_note = x86_cpu_write_elf64_note;
|
|
|
|
|
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
|
|
|
|
|
cc->write_elf32_note = x86_cpu_write_elf32_note;
|
|
|
|
|
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
|
2013-06-30 00:55:54 +08:00
|
|
|
cc->vmsd = &vmstate_x86_cpu;
|
2013-04-19 22:45:06 +08:00
|
|
|
#endif
|
2016-12-29 00:34:02 +08:00
|
|
|
cc->gdb_arch_name = x86_gdb_arch_name;
|
|
|
|
|
#ifdef TARGET_X86_64
|
2017-06-01 17:33:15 +08:00
|
|
|
cc->gdb_core_xml_file = "i386-64bit.xml";
|
|
|
|
|
cc->gdb_num_core_regs = 57;
|
2016-12-29 00:34:02 +08:00
|
|
|
#else
|
2017-06-01 17:33:15 +08:00
|
|
|
cc->gdb_core_xml_file = "i386-32bit.xml";
|
|
|
|
|
cc->gdb_num_core_regs = 41;
|
2016-12-29 00:34:02 +08:00
|
|
|
#endif
|
2017-07-03 18:12:22 +08:00
|
|
|
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
|
2014-09-12 21:06:48 +08:00
|
|
|
cc->debug_excp_handler = breakpoint_handler;
|
|
|
|
|
#endif
|
2014-09-14 00:45:14 +08:00
|
|
|
cc->cpu_exec_enter = x86_cpu_exec_enter;
|
|
|
|
|
cc->cpu_exec_exit = x86_cpu_exec_exit;
|
2017-10-26 21:58:14 +08:00
|
|
|
#ifdef CONFIG_TCG
|
2017-10-16 10:02:42 +08:00
|
|
|
cc->tcg_initialize = tcg_x86_init;
|
2017-10-26 21:58:14 +08:00
|
|
|
#endif
|
2017-09-14 23:10:53 +08:00
|
|
|
cc->disas_set_info = x86_disas_set_info;
|
qdev: Protect device-list-properties against broken devices
Several devices don't survive object_unref(object_new(T)): they crash
or hang during cleanup, or they leave dangling pointers behind.
This breaks at least device-list-properties, because
qmp_device_list_properties() needs to create a device to find its
properties. Broken in commit f4eb32b "qmp: show QOM properties in
device-list-properties", v2.1. Example reproducer:
$ qemu-system-aarch64 -nodefaults -display none -machine none -S -qmp stdio
{"QMP": {"version": {"qemu": {"micro": 50, "minor": 4, "major": 2}, "package": ""}, "capabilities": []}}
{ "execute": "qmp_capabilities" }
{"return": {}}
{ "execute": "device-list-properties", "arguments": { "typename": "pxa2xx-pcmcia" } }
qemu-system-aarch64: /home/armbru/work/qemu/memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed.
Aborted (core dumped)
[Exit 134 (SIGABRT)]
Unfortunately, I can't fix the problems in these devices right now.
Instead, add DeviceClass member cannot_destroy_with_object_finalize_yet
to mark them:
* Hang during cleanup (didn't debug, so I can't say why):
"realview_pci", "versatile_pci".
* Dangling pointer in cpus: most CPUs, plus "allwinner-a10", "digic",
"fsl,imx25", "fsl,imx31", "xlnx,zynqmp", because they create such
CPUs
* Assert kvm_enabled(): "host-x86_64-cpu", host-i386-cpu",
"host-powerpc64-cpu", "host-embedded-powerpc-cpu",
"host-powerpc-cpu" (the powerpc ones can't currently reach the
assertion, because the CPUs are only registered when KVM is enabled,
but the assertion is arguably in the wrong place all the same)
Make qmp_device_list_properties() fail cleanly when the device is so
marked. This improves device-list-properties from "crashes, hangs or
leaves dangling pointers behind" to "fails". Not a complete fix, just
a better-than-nothing work-around. In the above reproducer,
device-list-properties now fails with "Can't list properties of device
'pxa2xx-pcmcia'".
This also protects -device FOO,help, which uses the same machinery
since commit ef52358 "qdev-monitor: include QOM properties in -device
FOO, help output", v2.2. Example reproducer:
$ qemu-system-aarch64 -machine none -device pxa2xx-pcmcia,help
Before:
qemu-system-aarch64: .../memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed.
After:
Can't list properties of device 'pxa2xx-pcmcia'
Cc: "Andreas Färber" <afaerber@suse.de>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Anthony Green <green@moxielogic.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: Jia Liu <proljc@gmail.com>
Cc: Leon Alrae <leon.alrae@imgtec.com>
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Richard Henderson <rth@twiddle.net>
Cc: qemu-ppc@nongnu.org
Cc: qemu-stable@nongnu.org
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <1443689999-12182-10-git-send-email-armbru@redhat.com>
2015-10-01 16:59:58 +08:00
|
|
|
|
2017-05-04 04:35:44 +08:00
|
|
|
dc->user_creatable = true;
|
2012-04-03 05:20:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const TypeInfo x86_cpu_type_info = {
|
|
|
|
|
.name = TYPE_X86_CPU,
|
|
|
|
|
.parent = TYPE_CPU,
|
|
|
|
|
.instance_size = sizeof(X86CPU),
|
2012-04-03 06:00:17 +08:00
|
|
|
.instance_init = x86_cpu_initfn,
|
2014-02-10 18:21:30 +08:00
|
|
|
.abstract = true,
|
2012-04-03 05:20:08 +08:00
|
|
|
.class_size = sizeof(X86CPUClass),
|
|
|
|
|
.class_init = x86_cpu_common_class_init,
|
|
|
|
|
};
|
|
|
|
|
|
i386: Define static "base" CPU model
The query-cpu-model-expand QMP command needs at least one static
model, to allow the "static" expansion mode to be implemented.
Instead of defining static versions of every CPU model, define a
"base" CPU model that has absolutely no feature flag enabled.
Despite having no CPUID data set at all, "-cpu base" is even a
functional CPU:
* It can boot a Slackware Linux 1.01 image with a Linux 0.99.12
kernel[1].
* It is even possible to boot[2] a modern Fedora x86_64 guest by
manually enabling the following CPU features:
-cpu base,+lm,+msr,+pae,+fpu,+cx8,+cmov,+sse,+sse2,+fxsr
[1] http://www.qemu-advent-calendar.org/2014/#day-1
[2] This is what can be seen in the guest:
[root@localhost ~]# cat /proc/cpuinfo
processor : 0
vendor_id : unknown
cpu family : 0
model : 0
model name : 00/00
stepping : 0
physical id : 0
siblings : 1
core id : 0
cpu cores : 1
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu msr pae cx8 cmov fxsr sse sse2 lm nopl
bugs :
bogomips : 5832.70
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
[root@localhost ~]# x86info -v -a
x86info v1.30. Dave Jones 2001-2011
Feedback to <davej@redhat.com>.
No TSC, MHz calculation cannot be performed.
Unknown vendor (0)
MP Table:
Family: 0 Model: 0 Stepping: 0
CPU Model (x86info's best guess):
eax in: 0x00000000, eax = 00000001 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x00000001, eax = 00000000 ebx = 00000800 ecx = 00000000 edx = 07008161
eax in: 0x80000000, eax = 80000001 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 20000000
Feature flags:
fpu Onboard FPU
msr Model-Specific Registers
pae Physical Address Extensions
cx8 CMPXCHG8 instruction
cmov CMOV instruction
fxsr FXSAVE and FXRSTOR instructions
sse SSE support
sse2 SSE2 support
Long NOPs supported: yes
Address sizes : 0 bits physical, 0 bits virtual
0MHz processor (estimate).
running at an estimated 0MHz
[root@localhost ~]#
Message-Id: <20170222190029.17243-2-ehabkost@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Tested-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-02-23 03:00:27 +08:00
|
|
|
|
|
|
|
|
/* "base" CPU model, used by query-cpu-model-expansion */
|
|
|
|
|
static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
|
|
|
|
|
{
|
|
|
|
|
X86CPUClass *xcc = X86_CPU_CLASS(oc);
|
|
|
|
|
|
|
|
|
|
xcc->static_model = true;
|
|
|
|
|
xcc->migration_safe = true;
|
|
|
|
|
xcc->model_description = "base CPU model type with no features enabled";
|
|
|
|
|
xcc->ordering = 8;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const TypeInfo x86_base_cpu_type_info = {
|
|
|
|
|
.name = X86_CPU_TYPE_NAME("base"),
|
|
|
|
|
.parent = TYPE_X86_CPU,
|
|
|
|
|
.class_init = x86_cpu_base_class_init,
|
|
|
|
|
};
|
|
|
|
|
|
2012-04-03 05:20:08 +08:00
|
|
|
static void x86_cpu_register_types(void)
|
|
|
|
|
{
|
2014-02-10 18:21:30 +08:00
|
|
|
int i;
|
|
|
|
|
|
2012-04-03 05:20:08 +08:00
|
|
|
type_register_static(&x86_cpu_type_info);
|
2014-02-10 18:21:30 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
|
|
|
|
|
x86_register_cpudef_type(&builtin_x86_defs[i]);
|
|
|
|
|
}
|
2017-02-23 02:39:17 +08:00
|
|
|
type_register_static(&max_x86_cpu_type_info);
|
i386: Define static "base" CPU model
The query-cpu-model-expand QMP command needs at least one static
model, to allow the "static" expansion mode to be implemented.
Instead of defining static versions of every CPU model, define a
"base" CPU model that has absolutely no feature flag enabled.
Despite having no CPUID data set at all, "-cpu base" is even a
functional CPU:
* It can boot a Slackware Linux 1.01 image with a Linux 0.99.12
kernel[1].
* It is even possible to boot[2] a modern Fedora x86_64 guest by
manually enabling the following CPU features:
-cpu base,+lm,+msr,+pae,+fpu,+cx8,+cmov,+sse,+sse2,+fxsr
[1] http://www.qemu-advent-calendar.org/2014/#day-1
[2] This is what can be seen in the guest:
[root@localhost ~]# cat /proc/cpuinfo
processor : 0
vendor_id : unknown
cpu family : 0
model : 0
model name : 00/00
stepping : 0
physical id : 0
siblings : 1
core id : 0
cpu cores : 1
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu msr pae cx8 cmov fxsr sse sse2 lm nopl
bugs :
bogomips : 5832.70
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
[root@localhost ~]# x86info -v -a
x86info v1.30. Dave Jones 2001-2011
Feedback to <davej@redhat.com>.
No TSC, MHz calculation cannot be performed.
Unknown vendor (0)
MP Table:
Family: 0 Model: 0 Stepping: 0
CPU Model (x86info's best guess):
eax in: 0x00000000, eax = 00000001 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x00000001, eax = 00000000 ebx = 00000800 ecx = 00000000 edx = 07008161
eax in: 0x80000000, eax = 80000001 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 20000000
Feature flags:
fpu Onboard FPU
msr Model-Specific Registers
pae Physical Address Extensions
cx8 CMPXCHG8 instruction
cmov CMOV instruction
fxsr FXSAVE and FXRSTOR instructions
sse SSE support
sse2 SSE2 support
Long NOPs supported: yes
Address sizes : 0 bits physical, 0 bits virtual
0MHz processor (estimate).
running at an estimated 0MHz
[root@localhost ~]#
Message-Id: <20170222190029.17243-2-ehabkost@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Tested-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-02-23 03:00:27 +08:00
|
|
|
type_register_static(&x86_base_cpu_type_info);
|
2017-09-13 17:05:19 +08:00
|
|
|
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
|
2014-02-10 18:21:30 +08:00
|
|
|
type_register_static(&host_x86_cpu_type_info);
|
|
|
|
|
#endif
|
2012-04-03 05:20:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
type_init(x86_cpu_register_types)
|
