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uboot-bcm53xx: bump to 2024.01
Bump the U-Boot version used for BCM53xx to the 2024.01 version that includes all the needed patches upstream, so we can get rid of those in the process. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
Rafał Miłecki
parent
10180295b8
commit
f1a447bdb5
@ -1,7 +1,7 @@
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include $(TOPDIR)/rules.mk
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PKG_VERSION:=2023.04
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PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341
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PKG_VERSION:=2024.01
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PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
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PKG_RELEASE:=$(AUTORELEASE)
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include $(INCLUDE_DIR)/u-boot.mk
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@ -1,199 +0,0 @@
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From 854dc4b790ce1291326d52b8405ebe771bff2edd Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Wed, 8 Mar 2023 22:42:31 +0100
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Subject: [PATCH 1/5] nand: brcmnand: add iproc support
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Add support for the iproc Broadcom NAND controller,
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used in Northstar SoCs for example. Based on the Linux
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driver.
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Cc: Philippe Reynes <philippe.reynes@softathome.com>
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Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
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Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Acked-by: William Zhang <william.zhang@broadcom.com>
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Link: https://lore.kernel.org/all/20230308214231.378013-1-linus.walleij@linaro.org/
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Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
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---
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drivers/mtd/nand/raw/Kconfig | 7 +
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drivers/mtd/nand/raw/brcmnand/Makefile | 1 +
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drivers/mtd/nand/raw/brcmnand/iproc_nand.c | 148 +++++++++++++++++++++
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3 files changed, 156 insertions(+)
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create mode 100644 drivers/mtd/nand/raw/brcmnand/iproc_nand.c
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--- a/drivers/mtd/nand/raw/Kconfig
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+++ b/drivers/mtd/nand/raw/Kconfig
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@@ -156,6 +156,13 @@ config NAND_BRCMNAND_63158
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help
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Enable support for broadcom nand driver on bcm63158.
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+config NAND_BRCMNAND_IPROC
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+ bool "Support Broadcom NAND controller on the iproc family"
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+ depends on NAND_BRCMNAND
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+ help
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+ Enable support for broadcom nand driver on the Broadcom
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+ iproc family such as Northstar (BCM5301x, BCM4708...)
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+
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config NAND_DAVINCI
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bool "Support TI Davinci NAND controller"
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select SYS_NAND_SELF_INIT if TARGET_DA850EVM
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--- a/drivers/mtd/nand/raw/brcmnand/Makefile
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+++ b/drivers/mtd/nand/raw/brcmnand/Makefile
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@@ -6,5 +6,6 @@ obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6
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obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o
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obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o
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obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o
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+obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o
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obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o
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obj-$(CONFIG_NAND_BRCMNAND) += brcmnand_compat.o
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--- /dev/null
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+++ b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c
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@@ -0,0 +1,148 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Code borrowed from the Linux driver
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+ * Copyright (C) 2015 Broadcom Corporation
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+ */
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+
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+#include <common.h>
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+#include <asm/io.h>
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+#include <memalign.h>
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+#include <nand.h>
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+#include <linux/bitops.h>
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+#include <linux/err.h>
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+#include <linux/errno.h>
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+#include <linux/io.h>
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+#include <linux/ioport.h>
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+#include <dm.h>
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+
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+#include "brcmnand.h"
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+
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+struct iproc_nand_soc {
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+ struct brcmnand_soc soc;
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+ void __iomem *idm_base;
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+ void __iomem *ext_base;
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+};
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+
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+#define IPROC_NAND_CTLR_READY_OFFSET 0x10
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+#define IPROC_NAND_CTLR_READY BIT(0)
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+
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+#define IPROC_NAND_IO_CTRL_OFFSET 0x00
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+#define IPROC_NAND_APB_LE_MODE BIT(24)
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+#define IPROC_NAND_INT_CTRL_READ_ENABLE BIT(6)
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+
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+static bool iproc_nand_intc_ack(struct brcmnand_soc *soc)
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+{
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+ struct iproc_nand_soc *priv =
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+ container_of(soc, struct iproc_nand_soc, soc);
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+ void __iomem *mmio = priv->ext_base + IPROC_NAND_CTLR_READY_OFFSET;
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+ u32 val = brcmnand_readl(mmio);
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+
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+ if (val & IPROC_NAND_CTLR_READY) {
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+ brcmnand_writel(IPROC_NAND_CTLR_READY, mmio);
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+ return true;
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+ }
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+
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+ return false;
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+}
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+
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+static void iproc_nand_intc_set(struct brcmnand_soc *soc, bool en)
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+{
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+ struct iproc_nand_soc *priv =
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+ container_of(soc, struct iproc_nand_soc, soc);
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+ void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
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+ u32 val = brcmnand_readl(mmio);
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+
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+ if (en)
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+ val |= IPROC_NAND_INT_CTRL_READ_ENABLE;
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+ else
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+ val &= ~IPROC_NAND_INT_CTRL_READ_ENABLE;
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+
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+ brcmnand_writel(val, mmio);
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+}
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+
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+static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare,
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+ bool is_param)
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+{
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+ struct iproc_nand_soc *priv =
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+ container_of(soc, struct iproc_nand_soc, soc);
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+ void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
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+ u32 val;
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+
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+ val = brcmnand_readl(mmio);
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+
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+ /*
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+ * In the case of BE or when dealing with NAND data, always configure
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+ * the APB bus to LE mode before accessing the FIFO and back to BE mode
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+ * after the access is done
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+ */
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+ if (IS_ENABLED(CONFIG_SYS_BIG_ENDIAN) || !is_param) {
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+ if (prepare)
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+ val |= IPROC_NAND_APB_LE_MODE;
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+ else
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+ val &= ~IPROC_NAND_APB_LE_MODE;
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+ } else { /* when in LE accessing the parameter page, keep APB in BE */
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+ val &= ~IPROC_NAND_APB_LE_MODE;
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+ }
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+
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+ brcmnand_writel(val, mmio);
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+}
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+
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+static int iproc_nand_probe(struct udevice *dev)
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+{
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+ struct udevice *pdev = dev;
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+ struct iproc_nand_soc *priv = dev_get_priv(dev);
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+ struct brcmnand_soc *soc;
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+ struct resource res;
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+ int ret;
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+
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+ soc = &priv->soc;
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+
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+ ret = dev_read_resource_byname(pdev, "iproc-idm", &res);
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+ if (ret)
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+ return ret;
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+
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+ priv->idm_base = devm_ioremap(dev, res.start, resource_size(&res));
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+ if (IS_ERR(priv->idm_base))
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+ return PTR_ERR(priv->idm_base);
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+
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+ ret = dev_read_resource_byname(pdev, "iproc-ext", &res);
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+ if (ret)
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+ return ret;
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+
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+ priv->ext_base = devm_ioremap(dev, res.start, resource_size(&res));
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+ if (IS_ERR(priv->ext_base))
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+ return PTR_ERR(priv->ext_base);
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+
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+ soc->ctlrdy_ack = iproc_nand_intc_ack;
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+ soc->ctlrdy_set_enabled = iproc_nand_intc_set;
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+ soc->prepare_data_bus = iproc_nand_apb_access;
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+
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+ return brcmnand_probe(pdev, soc);
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+}
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+
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+static const struct udevice_id iproc_nand_dt_ids[] = {
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+ {
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+ .compatible = "brcm,nand-iproc",
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+ },
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+ { /* sentinel */ }
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+};
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+
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+U_BOOT_DRIVER(iproc_nand) = {
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+ .name = "iproc-nand",
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+ .id = UCLASS_MTD,
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+ .of_match = iproc_nand_dt_ids,
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+ .probe = iproc_nand_probe,
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+ .priv_auto = sizeof(struct iproc_nand_soc),
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+};
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+
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+void board_nand_init(void)
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+{
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+ struct udevice *dev;
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+ int ret;
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+
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+ ret = uclass_get_device_by_driver(UCLASS_MTD,
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+ DM_DRIVER_GET(iproc_nand), &dev);
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+ if (ret && ret != -ENODEV)
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+ pr_err("Failed to initialize %s. (error %d)\n", dev->name,
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+ ret);
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+}
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@ -1,80 +0,0 @@
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From d75483f8892f3a0dfb8f5aa4147e72c02c8b034c Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Fri, 7 Apr 2023 15:40:05 +0200
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Subject: [PATCH 2/5] mtd: rawnand: nand_base: Handle algorithm selection
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For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
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D-Link DIR-885L and DIR-890L routers, we need to explicitly
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select the ECC like this in the device tree:
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nand-ecc-algo = "bch";
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nand-ecc-strength = <1>;
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nand-ecc-step-size = <512>;
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This is handled by the Linux kernel but U-Boot core does
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not respect this. Fix it up by parsing the algorithm and
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preserve the behaviour using this property to select
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software BCH as far as possible.
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Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
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Acked-by: William Zhang <william.zhang@broadcom.com>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm]
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Link: https://lore.kernel.org/all/20230407134008.1939717-3-linus.walleij@linaro.org/
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Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
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---
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drivers/mtd/nand/raw/nand_base.c | 29 +++++++++++++++++++++++++----
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1 file changed, 25 insertions(+), 4 deletions(-)
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--- a/drivers/mtd/nand/raw/nand_base.c
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+++ b/drivers/mtd/nand/raw/nand_base.c
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@@ -4487,6 +4487,7 @@ EXPORT_SYMBOL(nand_detect);
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static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node)
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{
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int ret, ecc_mode = -1, ecc_strength, ecc_step;
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+ int ecc_algo = NAND_ECC_UNKNOWN;
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const char *str;
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ret = ofnode_read_s32_default(node, "nand-bus-width", -1);
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@@ -4512,10 +4513,22 @@ static int nand_dt_init(struct mtd_info
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ecc_mode = NAND_ECC_SOFT_BCH;
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}
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- if (ecc_mode == NAND_ECC_SOFT) {
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- str = ofnode_read_string(node, "nand-ecc-algo");
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- if (str && !strcmp(str, "bch"))
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- ecc_mode = NAND_ECC_SOFT_BCH;
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+ str = ofnode_read_string(node, "nand-ecc-algo");
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+ if (str) {
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+ /*
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+ * If we are in NAND_ECC_SOFT mode, just alter the
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+ * soft mode to BCH here. No change of algorithm.
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+ */
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+ if (ecc_mode == NAND_ECC_SOFT) {
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+ if (!strcmp(str, "bch"))
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+ ecc_mode = NAND_ECC_SOFT_BCH;
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+ } else {
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+ if (!strcmp(str, "bch")) {
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+ ecc_algo = NAND_ECC_BCH;
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+ } else if (!strcmp(str, "hamming")) {
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+ ecc_algo = NAND_ECC_HAMMING;
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+ }
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+ }
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}
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ecc_strength = ofnode_read_s32_default(node,
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@@ -4529,6 +4542,14 @@ static int nand_dt_init(struct mtd_info
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return -EINVAL;
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}
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+ /*
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+ * Chip drivers may have assigned default algorithms here,
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+ * onlt override it if we have found something explicitly
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+ * specified in the device tree.
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+ */
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+ if (ecc_algo != NAND_ECC_UNKNOWN)
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+ chip->ecc.algo = ecc_algo;
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+
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if (ecc_mode >= 0)
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chip->ecc.mode = ecc_mode;
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@ -1,659 +0,0 @@
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From 3d6098a662b7ff5b80c4b75c54fcd1b2baf9f150 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Mon, 24 Apr 2023 09:38:28 +0200
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Subject: [PATCH 3/5] arm: dts: Import device tree for Broadcom Northstar
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This brings in the main SoC device tree used by the
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Broadcom Northstar chipset, i.e. BCM4709x and BCM5301x.
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This is taken from the v6.3 Linux kernel.
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Cc: Rafał Miłecki <rafal@milecki.pl>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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arch/arm/dts/bcm5301x.dtsi | 581 ++++++++++++++++++++++++++++
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include/dt-bindings/clock/bcm-nsp.h | 51 +++
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2 files changed, 632 insertions(+)
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create mode 100644 arch/arm/dts/bcm5301x.dtsi
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create mode 100644 include/dt-bindings/clock/bcm-nsp.h
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--- /dev/null
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+++ b/arch/arm/dts/bcm5301x.dtsi
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@@ -0,0 +1,581 @@
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+/*
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+ * Broadcom BCM470X / BCM5301X ARM platform code.
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+ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
|
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+ * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
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+ *
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+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include <dt-bindings/clock/bcm-nsp.h>
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/interrupt-controller/irq.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ interrupt-parent = <&gic>;
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+
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+ chipcommon-a-bus@18000000 {
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+ compatible = "simple-bus";
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+ ranges = <0x00000000 0x18000000 0x00001000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ uart0: serial@300 {
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+ compatible = "ns16550";
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+ reg = <0x0300 0x100>;
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+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&iprocslow>;
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+ status = "disabled";
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+ };
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+
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+ uart1: serial@400 {
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+ compatible = "ns16550";
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+ reg = <0x0400 0x100>;
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+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&iprocslow>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinmux_uart1>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ mpcore-bus@19000000 {
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+ compatible = "simple-bus";
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+ ranges = <0x00000000 0x19000000 0x00023000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ a9pll: arm_clk@0 {
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+ #clock-cells = <0>;
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+ compatible = "brcm,nsp-armpll";
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+ clocks = <&osc>;
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+ reg = <0x00000 0x1000>;
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+ };
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+
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+ scu@20000 {
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+ compatible = "arm,cortex-a9-scu";
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+ reg = <0x20000 0x100>;
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+ };
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+
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+ timer@20200 {
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+ compatible = "arm,cortex-a9-global-timer";
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+ reg = <0x20200 0x100>;
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+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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+ clocks = <&periph_clk>;
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+ };
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+
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+ timer@20600 {
|
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+ compatible = "arm,cortex-a9-twd-timer";
|
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+ reg = <0x20600 0x20>;
|
||||
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
+ IRQ_TYPE_EDGE_RISING)>;
|
||||
+ clocks = <&periph_clk>;
|
||||
+ };
|
||||
+
|
||||
+ watchdog@20620 {
|
||||
+ compatible = "arm,cortex-a9-twd-wdt";
|
||||
+ reg = <0x20620 0x20>;
|
||||
+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
+ IRQ_TYPE_EDGE_RISING)>;
|
||||
+ clocks = <&periph_clk>;
|
||||
+ };
|
||||
+
|
||||
+ gic: interrupt-controller@21000 {
|
||||
+ compatible = "arm,cortex-a9-gic";
|
||||
+ #interrupt-cells = <3>;
|
||||
+ #address-cells = <0>;
|
||||
+ interrupt-controller;
|
||||
+ reg = <0x21000 0x1000>,
|
||||
+ <0x20100 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ L2: cache-controller@22000 {
|
||||
+ compatible = "arm,pl310-cache";
|
||||
+ reg = <0x22000 0x1000>;
|
||||
+ cache-unified;
|
||||
+ arm,shared-override;
|
||||
+ prefetch-data = <1>;
|
||||
+ prefetch-instr = <1>;
|
||||
+ cache-level = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmu {
|
||||
+ compatible = "arm,cortex-a9-pmu";
|
||||
+ interrupts =
|
||||
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ clocks {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges;
|
||||
+
|
||||
+ osc: oscillator {
|
||||
+ #clock-cells = <0>;
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <25000000>;
|
||||
+ };
|
||||
+
|
||||
+ iprocmed: iprocmed {
|
||||
+ #clock-cells = <0>;
|
||||
+ compatible = "fixed-factor-clock";
|
||||
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
|
||||
+ clock-div = <2>;
|
||||
+ clock-mult = <1>;
|
||||
+ };
|
||||
+
|
||||
+ iprocslow: iprocslow {
|
||||
+ #clock-cells = <0>;
|
||||
+ compatible = "fixed-factor-clock";
|
||||
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
|
||||
+ clock-div = <4>;
|
||||
+ clock-mult = <1>;
|
||||
+ };
|
||||
+
|
||||
+ periph_clk: periph_clk {
|
||||
+ #clock-cells = <0>;
|
||||
+ compatible = "fixed-factor-clock";
|
||||
+ clocks = <&a9pll>;
|
||||
+ clock-div = <2>;
|
||||
+ clock-mult = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ axi@18000000 {
|
||||
+ compatible = "brcm,bus-axi";
|
||||
+ reg = <0x18000000 0x1000>;
|
||||
+ ranges = <0x00000000 0x18000000 0x00100000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0x000fffff 0xffff>;
|
||||
+ interrupt-map =
|
||||
+ /* ChipCommon */
|
||||
+ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* Switch Register Access Block */
|
||||
+ <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* PCIe Controller 0 */
|
||||
+ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* PCIe Controller 1 */
|
||||
+ <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* PCIe Controller 2 */
|
||||
+ <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* USB 2.0 Controller */
|
||||
+ <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* USB 3.0 Controller */
|
||||
+ <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* Ethernet Controller 0 */
|
||||
+ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* Ethernet Controller 1 */
|
||||
+ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* Ethernet Controller 2 */
|
||||
+ <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* Ethernet Controller 3 */
|
||||
+ <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* NAND Controller */
|
||||
+ <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+
|
||||
+ chipcommon: chipcommon@0 {
|
||||
+ reg = <0x00000000 0x1000>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <2>;
|
||||
+ };
|
||||
+
|
||||
+ pcie0: pcie@12000 {
|
||||
+ reg = <0x00012000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pcie@13000 {
|
||||
+ reg = <0x00013000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ pcie2: pcie@14000 {
|
||||
+ reg = <0x00014000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ usb2: usb2@21000 {
|
||||
+ reg = <0x00021000 0x1000>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges;
|
||||
+
|
||||
+ interrupt-parent = <&gic>;
|
||||
+
|
||||
+ ehci: usb@21000 {
|
||||
+ #usb-cells = <0>;
|
||||
+
|
||||
+ compatible = "generic-ehci";
|
||||
+ reg = <0x00021000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ phys = <&usb2_phy>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ ehci_port1: port@1 {
|
||||
+ reg = <1>;
|
||||
+ #trigger-source-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ ehci_port2: port@2 {
|
||||
+ reg = <2>;
|
||||
+ #trigger-source-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ohci: usb@22000 {
|
||||
+ #usb-cells = <0>;
|
||||
+
|
||||
+ compatible = "generic-ohci";
|
||||
+ reg = <0x00022000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ ohci_port1: port@1 {
|
||||
+ reg = <1>;
|
||||
+ #trigger-source-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ ohci_port2: port@2 {
|
||||
+ reg = <2>;
|
||||
+ #trigger-source-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb3: usb3@23000 {
|
||||
+ reg = <0x00023000 0x1000>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges;
|
||||
+
|
||||
+ interrupt-parent = <&gic>;
|
||||
+
|
||||
+ xhci: usb@23000 {
|
||||
+ #usb-cells = <0>;
|
||||
+
|
||||
+ compatible = "generic-xhci";
|
||||
+ reg = <0x00023000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ phys = <&usb3_phy>;
|
||||
+ phy-names = "usb";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ xhci_port1: port@1 {
|
||||
+ reg = <1>;
|
||||
+ #trigger-source-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gmac0: ethernet@24000 {
|
||||
+ reg = <0x24000 0x800>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1: ethernet@25000 {
|
||||
+ reg = <0x25000 0x800>;
|
||||
+ };
|
||||
+
|
||||
+ gmac2: ethernet@26000 {
|
||||
+ reg = <0x26000 0x800>;
|
||||
+ };
|
||||
+
|
||||
+ gmac3: ethernet@27000 {
|
||||
+ reg = <0x27000 0x800>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pwm: pwm@18002000 {
|
||||
+ compatible = "brcm,iproc-pwm";
|
||||
+ reg = <0x18002000 0x28>;
|
||||
+ clocks = <&osc>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ mdio: mdio@18003000 {
|
||||
+ compatible = "brcm,iproc-mdio";
|
||||
+ reg = <0x18003000 0x8>;
|
||||
+ #size-cells = <0>;
|
||||
+ #address-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ mdio-mux@18003000 {
|
||||
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
+ mdio-parent-bus = <&mdio>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0x18003000 0x4>;
|
||||
+ mux-mask = <0x200>;
|
||||
+
|
||||
+ mdio@0 {
|
||||
+ reg = <0x0>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ usb3_phy: usb3-phy@10 {
|
||||
+ compatible = "brcm,ns-ax-usb3-phy";
|
||||
+ reg = <0x10>;
|
||||
+ usb3-dmp-syscon = <&usb3_dmp>;
|
||||
+ #phy-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb3_dmp: syscon@18105000 {
|
||||
+ reg = <0x18105000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ uart2: serial@18008000 {
|
||||
+ compatible = "ns16550a";
|
||||
+ reg = <0x18008000 0x20>;
|
||||
+ clocks = <&iprocslow>;
|
||||
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg-shift = <2>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ i2c0: i2c@18009000 {
|
||||
+ compatible = "brcm,iproc-i2c";
|
||||
+ reg = <0x18009000 0x50>;
|
||||
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ clock-frequency = <100000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ dmu-bus@1800c000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ ranges = <0 0x1800c000 0x1000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ cru-bus@100 {
|
||||
+ compatible = "brcm,ns-cru", "simple-mfd";
|
||||
+ reg = <0x100 0x1a4>;
|
||||
+ ranges;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ lcpll0: clock-controller@100 {
|
||||
+ #clock-cells = <1>;
|
||||
+ compatible = "brcm,nsp-lcpll0";
|
||||
+ reg = <0x100 0x14>;
|
||||
+ clocks = <&osc>;
|
||||
+ clock-output-names = "lcpll0", "pcie_phy",
|
||||
+ "sdio", "ddr_phy";
|
||||
+ };
|
||||
+
|
||||
+ genpll: clock-controller@140 {
|
||||
+ #clock-cells = <1>;
|
||||
+ compatible = "brcm,nsp-genpll";
|
||||
+ reg = <0x140 0x24>;
|
||||
+ clocks = <&osc>;
|
||||
+ clock-output-names = "genpll", "phy",
|
||||
+ "ethernetclk",
|
||||
+ "usbclk", "iprocfast",
|
||||
+ "sata1", "sata2";
|
||||
+ };
|
||||
+
|
||||
+ usb2_phy: phy@164 {
|
||||
+ compatible = "brcm,ns-usb2-phy";
|
||||
+ reg = <0x164 0x4>;
|
||||
+ brcm,syscon-clkset = <&cru_clkset>;
|
||||
+ clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
|
||||
+ clock-names = "phy-ref-clk";
|
||||
+ #phy-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ cru_clkset: syscon@180 {
|
||||
+ compatible = "brcm,cru-clkset", "syscon";
|
||||
+ reg = <0x180 0x4>;
|
||||
+ };
|
||||
+
|
||||
+ pinctrl: pinctrl@1c0 {
|
||||
+ compatible = "brcm,bcm4708-pinmux";
|
||||
+ reg = <0x1c0 0x24>;
|
||||
+ reg-names = "cru_gpio_control";
|
||||
+
|
||||
+ spi-pins {
|
||||
+ groups = "spi_grp";
|
||||
+ function = "spi";
|
||||
+ };
|
||||
+
|
||||
+ pinmux_i2c: i2c-pins {
|
||||
+ groups = "i2c_grp";
|
||||
+ function = "i2c";
|
||||
+ };
|
||||
+
|
||||
+ pinmux_pwm: pwm-pins {
|
||||
+ groups = "pwm0_grp", "pwm1_grp",
|
||||
+ "pwm2_grp", "pwm3_grp";
|
||||
+ function = "pwm";
|
||||
+ };
|
||||
+
|
||||
+ pinmux_uart1: uart1-pins {
|
||||
+ groups = "uart1_grp";
|
||||
+ function = "uart1";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ thermal: thermal@2c0 {
|
||||
+ compatible = "brcm,ns-thermal";
|
||||
+ reg = <0x2c0 0x10>;
|
||||
+ #thermal-sensor-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ srab: ethernet-switch@18007000 {
|
||||
+ compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
|
||||
+ reg = <0x18007000 0x1000>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ /* ports are defined in board DTS */
|
||||
+ ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rng: rng@18004000 {
|
||||
+ compatible = "brcm,bcm5301x-rng";
|
||||
+ reg = <0x18004000 0x14>;
|
||||
+ };
|
||||
+
|
||||
+ nand_controller: nand-controller@18028000 {
|
||||
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
|
||||
+ reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
|
||||
+ reg-names = "nand", "iproc-idm", "iproc-ext";
|
||||
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ brcm,nand-has-wp;
|
||||
+ };
|
||||
+
|
||||
+ spi@18029200 {
|
||||
+ compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
|
||||
+ reg = <0x18029200 0x184>,
|
||||
+ <0x18029000 0x124>,
|
||||
+ <0x1811b408 0x004>,
|
||||
+ <0x180293a0 0x01c>;
|
||||
+ reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
|
||||
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "mspi_done",
|
||||
+ "mspi_halted",
|
||||
+ "spi_lr_fullness_reached",
|
||||
+ "spi_lr_session_aborted",
|
||||
+ "spi_lr_impatient",
|
||||
+ "spi_lr_session_done",
|
||||
+ "spi_lr_overread";
|
||||
+ clocks = <&iprocmed>;
|
||||
+ clock-names = "iprocmed";
|
||||
+ num-cs = <2>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ spi_nor: flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <20000000>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ partitions {
|
||||
+ compatible = "brcm,bcm947xx-cfe-partitions";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ thermal-zones {
|
||||
+ cpu_thermal: cpu-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <1000>;
|
||||
+ coefficients = <(-556) 418000>;
|
||||
+ thermal-sensors = <&thermal>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-crit {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/clock/bcm-nsp.h
|
||||
@@ -0,0 +1,51 @@
|
||||
+/*
|
||||
+ * BSD LICENSE
|
||||
+ *
|
||||
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
|
||||
+ *
|
||||
+ * Redistribution and use in source and binary forms, with or without
|
||||
+ * modification, are permitted provided that the following conditions
|
||||
+ * are met:
|
||||
+ *
|
||||
+ * * Redistributions of source code must retain the above copyright
|
||||
+ * notice, this list of conditions and the following disclaimer.
|
||||
+ * * Redistributions in binary form must reproduce the above copyright
|
||||
+ * notice, this list of conditions and the following disclaimer in
|
||||
+ * the documentation and/or other materials provided with the
|
||||
+ * distribution.
|
||||
+ * * Neither the name of Broadcom Corporation nor the names of its
|
||||
+ * contributors may be used to endorse or promote products derived
|
||||
+ * from this software without specific prior written permission.
|
||||
+ *
|
||||
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
+ */
|
||||
+
|
||||
+#ifndef _CLOCK_BCM_NSP_H
|
||||
+#define _CLOCK_BCM_NSP_H
|
||||
+
|
||||
+/* GENPLL clock channel ID */
|
||||
+#define BCM_NSP_GENPLL 0
|
||||
+#define BCM_NSP_GENPLL_PHY_CLK 1
|
||||
+#define BCM_NSP_GENPLL_ENET_SW_CLK 2
|
||||
+#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3
|
||||
+#define BCM_NSP_GENPLL_IPROCFAST_CLK 4
|
||||
+#define BCM_NSP_GENPLL_SATA1_CLK 5
|
||||
+#define BCM_NSP_GENPLL_SATA2_CLK 6
|
||||
+
|
||||
+/* LCPLL0 clock channel ID */
|
||||
+#define BCM_NSP_LCPLL0 0
|
||||
+#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1
|
||||
+#define BCM_NSP_LCPLL0_SDIO_CLK 2
|
||||
+#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3
|
||||
+
|
||||
+#endif /* _CLOCK_BCM_NSP_H */
|
||||
@ -1,66 +0,0 @@
|
||||
From b81ea0a64b01ae42e8b41d2a8b9a3fabffe97489 Mon Sep 17 00:00:00 2001
|
||||
From: Linus Walleij <linus.walleij@linaro.org>
|
||||
Date: Mon, 24 Apr 2023 09:38:29 +0200
|
||||
Subject: [PATCH 4/5] arm: Add support for the Broadcom Northstar SoCs
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
The original Northstar is an ARM SoC series that comprise
|
||||
BCM4709x and BCM5301x and uses a dual-core Cortex A9, the
|
||||
global timer and a few other things.
|
||||
|
||||
This series should not be confused with North Star Plus
|
||||
(NSP) which is partly supported by U-Boot already.
|
||||
|
||||
The SoC is well supported by the Linux kernel and OpenWrt
|
||||
as it is used in many routers.
|
||||
|
||||
Since we currently don't need any chip-specific quirks
|
||||
and can get the system up from just the device tree, a
|
||||
mach-* directory doesn't even need to be added, just
|
||||
some small Kconfig fragments.
|
||||
|
||||
Cc: Rafał Miłecki <rafal@milecki.pl>
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
arch/arm/Kconfig | 21 ++++++++++++++++++++-
|
||||
1 file changed, 20 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -357,7 +357,7 @@ config SYS_ARM_ARCH
|
||||
|
||||
choice
|
||||
prompt "Select the ARM data write cache policy"
|
||||
- default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
|
||||
+ default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || TARGET_BCMNS || RZA1
|
||||
default SYS_ARM_CACHE_WRITEBACK
|
||||
|
||||
config SYS_ARM_CACHE_WRITEBACK
|
||||
@@ -670,6 +670,25 @@ config TARGET_BCMCYGNUS
|
||||
imply HASH_VERIFY
|
||||
imply NETDEVICES
|
||||
|
||||
+config TARGET_BCMNS
|
||||
+ bool "Support Broadcom Northstar"
|
||||
+ select CPU_V7A
|
||||
+ select DM
|
||||
+ select DM_GPIO
|
||||
+ select DM_SERIAL
|
||||
+ select OF_CONTROL
|
||||
+ select TIMER
|
||||
+ select SYS_NS16550
|
||||
+ select ARM_GLOBAL_TIMER
|
||||
+ imply SYS_THUMB_BUILD
|
||||
+ imply MTD_RAW_NAND
|
||||
+ imply NAND_BRCMNAND
|
||||
+ imply NAND_BRCMNAND_IPROC
|
||||
+ help
|
||||
+ Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit
|
||||
+ ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
|
||||
+ BCM5301x etc.
|
||||
+
|
||||
config TARGET_BCMNS2
|
||||
bool "Support Broadcom Northstar2"
|
||||
select ARM64
|
||||
@ -1,372 +0,0 @@
|
||||
From 652a6fa45b6c9d52dd9685fc12ad662e54a9092e Mon Sep 17 00:00:00 2001
|
||||
From: Linus Walleij <linus.walleij@linaro.org>
|
||||
Date: Mon, 24 Apr 2023 09:38:30 +0200
|
||||
Subject: [PATCH 5/5] board: Add new Broadcom Northstar board
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
This adds a simple Northstar "BRCMNS" board to be used with
|
||||
the BCM4708x and BCM5301x chips.
|
||||
|
||||
The main intention is to use this with the D-Link DIR-890L
|
||||
and DIR-885L routers for loading the kernel into RAM from
|
||||
NAND memory using the BCH-1 ECC and using the separately
|
||||
submitted SEAMA load command, so we are currently not adding
|
||||
support for things such as networking.
|
||||
|
||||
The DTS file is a multiplatform NorthStar board, designed to
|
||||
be usable with several NorthStar designs by avoiding any
|
||||
particulars not related to the operation of U-Boot.
|
||||
|
||||
If other board need other ECC for example, they need to
|
||||
create a separate DTS file and augment the code, but I don't
|
||||
know if any other users will turn up.
|
||||
|
||||
Cc: Rafał Miłecki <rafal@milecki.pl>
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
arch/arm/Kconfig | 1 +
|
||||
arch/arm/dts/Makefile | 2 ++
|
||||
arch/arm/dts/ns-board.dts | 57 ++++++++++++++++++++++++++++++
|
||||
board/broadcom/bcmns/Kconfig | 12 +++++++
|
||||
board/broadcom/bcmns/MAINTAINERS | 6 ++++
|
||||
board/broadcom/bcmns/Makefile | 2 ++
|
||||
board/broadcom/bcmns/ns.c | 60 ++++++++++++++++++++++++++++++++
|
||||
configs/bcmns_defconfig | 41 ++++++++++++++++++++++
|
||||
doc/board/broadcom/index.rst | 1 +
|
||||
doc/board/broadcom/northstar.rst | 44 +++++++++++++++++++++++
|
||||
include/configs/bcmns.h | 49 ++++++++++++++++++++++++++
|
||||
11 files changed, 275 insertions(+)
|
||||
create mode 100644 arch/arm/dts/ns-board.dts
|
||||
create mode 100644 board/broadcom/bcmns/Kconfig
|
||||
create mode 100644 board/broadcom/bcmns/MAINTAINERS
|
||||
create mode 100644 board/broadcom/bcmns/Makefile
|
||||
create mode 100644 board/broadcom/bcmns/ns.c
|
||||
create mode 100644 configs/bcmns_defconfig
|
||||
create mode 100644 doc/board/broadcom/northstar.rst
|
||||
create mode 100644 include/configs/bcmns.h
|
||||
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -2286,6 +2286,7 @@ source "board/Marvell/octeontx2/Kconfig"
|
||||
source "board/armltd/vexpress/Kconfig"
|
||||
source "board/armltd/vexpress64/Kconfig"
|
||||
source "board/cortina/presidio-asic/Kconfig"
|
||||
+source "board/broadcom/bcmns/Kconfig"
|
||||
source "board/broadcom/bcmns3/Kconfig"
|
||||
source "board/cavium/thunderx/Kconfig"
|
||||
source "board/eets/pdu001/Kconfig"
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -1185,6 +1185,8 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
|
||||
bcm2837-rpi-cm3-io3.dtb \
|
||||
bcm2711-rpi-4-b.dtb
|
||||
|
||||
+dtb-$(CONFIG_TARGET_BCMNS) += ns-board.dtb
|
||||
+
|
||||
dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/ns-board.dts
|
||||
@@ -0,0 +1,57 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "bcm5301x.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ /*
|
||||
+ * The Northstar does not have a proper fallback compatible, but
|
||||
+ * these basic chips will suffice.
|
||||
+ */
|
||||
+ model = "Northstar model";
|
||||
+ compatible = "brcm,bcm47094", "brcm,bcm4708";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+
|
||||
+ memory {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x00000000 0x08000000>,
|
||||
+ <0x88000000 0x08000000>;
|
||||
+ };
|
||||
+
|
||||
+ aliases {
|
||||
+ serial0 = &uart0;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ nand-controller@18028000 {
|
||||
+ nandcs: nand@0 {
|
||||
+ compatible = "brcm,nandcs";
|
||||
+ reg = <0>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ /*
|
||||
+ * Same as using the bcm5301x-nand-cs0-bch1.dtsi
|
||||
+ * include from the Linux kernel.
|
||||
+ */
|
||||
+ nand-ecc-algo = "bch";
|
||||
+ nand-ecc-strength = <1>;
|
||||
+ nand-ecc-step-size = <512>;
|
||||
+
|
||||
+ partitions {
|
||||
+ compatible = "brcm,bcm947xx-cfe-partitions";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ clock-frequency = <125000000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/board/broadcom/bcmns/Kconfig
|
||||
@@ -0,0 +1,12 @@
|
||||
+if TARGET_BCMNS
|
||||
+
|
||||
+config SYS_BOARD
|
||||
+ default "bcmns"
|
||||
+
|
||||
+config SYS_VENDOR
|
||||
+ default "broadcom"
|
||||
+
|
||||
+config SYS_CONFIG_NAME
|
||||
+ default "bcmns"
|
||||
+
|
||||
+endif
|
||||
--- /dev/null
|
||||
+++ b/board/broadcom/bcmns/MAINTAINERS
|
||||
@@ -0,0 +1,6 @@
|
||||
+BCMNS BOARD
|
||||
+M: Linus Walleij <linus.walleij@linaro.org>
|
||||
+S: Maintained
|
||||
+F: board/broadcom/bcmnsp/
|
||||
+F: configs/bcmnsp_defconfig
|
||||
+F: include/configs/bcmnsp.h
|
||||
--- /dev/null
|
||||
+++ b/board/broadcom/bcmns/Makefile
|
||||
@@ -0,0 +1,2 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+obj-y := ns.o
|
||||
--- /dev/null
|
||||
+++ b/board/broadcom/bcmns/ns.c
|
||||
@@ -0,0 +1,60 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * Broadcom Northstar generic board set-up code
|
||||
+ * Copyright (C) 2023 Linus Walleij <linus.walleij@linaro.org>
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <dm.h>
|
||||
+#include <init.h>
|
||||
+#include <log.h>
|
||||
+#include <ram.h>
|
||||
+#include <serial.h>
|
||||
+#include <asm/global_data.h>
|
||||
+#include <asm/io.h>
|
||||
+#include <asm/armv7m.h>
|
||||
+
|
||||
+DECLARE_GLOBAL_DATA_PTR;
|
||||
+
|
||||
+int dram_init(void)
|
||||
+{
|
||||
+ return fdtdec_setup_mem_size_base();
|
||||
+}
|
||||
+
|
||||
+int dram_init_banksize(void)
|
||||
+{
|
||||
+ return fdtdec_setup_memory_banksize();
|
||||
+}
|
||||
+
|
||||
+int board_late_init(void)
|
||||
+{
|
||||
+ /* LEDs etc can be initialized here */
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int board_init(void)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+void reset_cpu(void)
|
||||
+{
|
||||
+}
|
||||
+
|
||||
+int print_cpuinfo(void)
|
||||
+{
|
||||
+ printf("BCMNS Northstar SoC\n");
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int misc_init_r(void)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int ft_board_setup(void *fdt, struct bd_info *bd)
|
||||
+{
|
||||
+ printf("Northstar board setup: DTB at 0x%08lx\n", (ulong)fdt);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
--- /dev/null
|
||||
+++ b/configs/bcmns_defconfig
|
||||
@@ -0,0 +1,41 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_TARGET_BCMNS=y
|
||||
+CONFIG_TEXT_BASE=0x00008000
|
||||
+CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
+CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="ns-board"
|
||||
+CONFIG_IDENT_STRING="Broadcom Northstar"
|
||||
+CONFIG_SYS_LOAD_ADDR=0x00008000
|
||||
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00100000
|
||||
+# CONFIG_BOOTSTD is not set
|
||||
+CONFIG_AUTOBOOT_KEYED=y
|
||||
+CONFIG_AUTOBOOT_PROMPT="Boot Northstar system in %d seconds\n"
|
||||
+CONFIG_BOOTDELAY=1
|
||||
+CONFIG_USE_BOOTCOMMAND=y
|
||||
+CONFIG_BOOTCOMMAND="run bootcmd_dlink_dir8xxl"
|
||||
+CONFIG_SYS_PROMPT="northstar> "
|
||||
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
|
||||
+CONFIG_OF_BOARD_SETUP=y
|
||||
+CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_HUSH_PARSER=y
|
||||
+CONFIG_SYS_MAXARGS=64
|
||||
+CONFIG_CMD_SEAMA=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_CACHE=y
|
||||
+CONFIG_OF_EMBED=y
|
||||
+CONFIG_USE_HOSTNAME=y
|
||||
+CONFIG_HOSTNAME="NS"
|
||||
+CONFIG_CLK=y
|
||||
+CONFIG_MTD=y
|
||||
+CONFIG_DM_MTD=y
|
||||
+CONFIG_MTD_RAW_NAND=y
|
||||
+CONFIG_NAND_BRCMNAND=y
|
||||
+CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
+CONFIG_CMD_NAND=y
|
||||
+CONFIG_DM_SERIAL=y
|
||||
+CONFIG_SYS_NS16550=y
|
||||
+# CONFIG_NET is not set
|
||||
+# CONFIG_EFI_LOADER is not set
|
||||
--- a/doc/board/broadcom/index.rst
|
||||
+++ b/doc/board/broadcom/index.rst
|
||||
@@ -9,3 +9,4 @@ Broadcom
|
||||
|
||||
bcm7xxx
|
||||
raspberrypi
|
||||
+ northstar
|
||||
--- /dev/null
|
||||
+++ b/doc/board/broadcom/northstar.rst
|
||||
@@ -0,0 +1,44 @@
|
||||
+.. SPDX-License-Identifier: GPL-2.0+
|
||||
+.. Copyright (C) 2023 Linus Walleij <linus.walleij@linaro.org>
|
||||
+
|
||||
+Broadcom Northstar Boards
|
||||
+=========================
|
||||
+
|
||||
+This document describes how to use U-Boot on the Broadcom Northstar
|
||||
+boards, comprised of the Cortex A9 ARM-based BCM470x and BCM5301x SoCs. These
|
||||
+were introduced in 2012-2013 and some of them are also called StrataGX.
|
||||
+
|
||||
+Northstar is part of the iProc SoC family.
|
||||
+
|
||||
+A good overview of these boards can be found in Jon Mason's presentation
|
||||
+"Enabling New Hardware in U-Boot" where the difference between Northstar
|
||||
+and Northstar Plus and Northstar 2 (Aarch64) is addressed.
|
||||
+
|
||||
+The ROM in the Northstar SoC will typically look into NOR flash memory
|
||||
+for a boot loader, and the way this works is undocumented. It should be
|
||||
+possible to execute U-Boot as the first binary from the NOR flash but
|
||||
+this usage path is unexplored. Please add information if you know more.
|
||||
+
|
||||
+D-Link Boards
|
||||
+-------------
|
||||
+
|
||||
+When we use U-Boot with D-Link routers, the NOR flash has a boot loader
|
||||
+and web server that can re-flash the bigger NAND flash memory for object
|
||||
+code in the SEAMA format, so on these platforms U-Boot is converted into
|
||||
+a SEAMA binary and installed in the SoC using the flash tool resident in
|
||||
+the NOR flash. Details can be found in the OpenWrt project codebase.
|
||||
+
|
||||
+Configure
|
||||
+---------
|
||||
+
|
||||
+.. code-block:: console
|
||||
+
|
||||
+ $ make CROSS_COMPILE=${CROSS_COMPILE} bcmns_defconfig
|
||||
+
|
||||
+Build
|
||||
+-----
|
||||
+
|
||||
+.. code-block:: console
|
||||
+
|
||||
+ $ make CROSS_COMPILE=${CROSS_COMPILE}
|
||||
+ $ ${CROSS_COMPILE}strip u-boot
|
||||
--- /dev/null
|
||||
+++ b/include/configs/bcmns.h
|
||||
@@ -0,0 +1,49 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
+
|
||||
+#ifndef __BCM_NS_H
|
||||
+#define __BCM_NS_H
|
||||
+
|
||||
+#include <linux/sizes.h>
|
||||
+
|
||||
+/* Physical Memory Map */
|
||||
+#define V2M_BASE 0x00000000
|
||||
+#define PHYS_SDRAM_1 V2M_BASE
|
||||
+
|
||||
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
+
|
||||
+/* Called "periph_clk" in Linux, used by the global timer */
|
||||
+#define CFG_SYS_HZ_CLOCK 500000000
|
||||
+
|
||||
+/* Called "iprocslow" in Linux */
|
||||
+#define CFG_SYS_NS16550_CLK 125000000
|
||||
+
|
||||
+/* console configuration */
|
||||
+#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0"
|
||||
+#define MAX_CPUS "max_cpus=maxcpus=2\0"
|
||||
+#define EXTRA_ARGS "extra_args=earlycon=uart8250,mmio32,0x18000300\0"
|
||||
+
|
||||
+#define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}" \
|
||||
+ " ${max_cpus} ${log_level} ${reserved_mem}"
|
||||
+#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS "\0"
|
||||
+
|
||||
+#define KERNEL_LOADADDR_CFG \
|
||||
+ "loadaddr=0x01000000\0" \
|
||||
+ "dtb_loadaddr=0x02000000\0"
|
||||
+
|
||||
+/*
|
||||
+ * Hardcoded for the only boards we support, if you add more
|
||||
+ * boards, add a more clever bootcmd!
|
||||
+ */
|
||||
+#define NS_BOOTCMD "bootcmd_dlink_dir8xxl=seama 0x00fe0000; go 0x01000000"
|
||||
+
|
||||
+#define ARCH_ENV_SETTINGS \
|
||||
+ CONSOLE_ARGS \
|
||||
+ MAX_CPUS \
|
||||
+ EXTRA_ARGS \
|
||||
+ KERNEL_LOADADDR_CFG \
|
||||
+ NS_BOOTCMD
|
||||
+
|
||||
+#define CFG_EXTRA_ENV_SETTINGS \
|
||||
+ ARCH_ENV_SETTINGS
|
||||
+
|
||||
+#endif /* __BCM_NS_H */
|
||||
Loading…
Reference in New Issue
Block a user