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ipq806x: Add support to configure ipq40xx GPIO_PULL bits
GPIO_PULL bits configurations in TLMM_GPIO_CFG register differs for IPQ40xx from rest of the other qcom SoC's. This change add support to configure the msm_gpio_pull bits for ipq40xx, It is required to fix the proper configurations of gpio-pull bits for nand pins mux. Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
This commit is contained in:
Ram Chandra Jangir
John Crispin
parent
61eb18d3f7
commit
d227bb06df
@ -0,0 +1,260 @@
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From e77af7de404eb464f7da9e0daeb8b362cc66a7ba Mon Sep 17 00:00:00 2001
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From: Ram Chandra Jangir <rjangir@codeaurora.org>
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Date: Tue, 9 May 2017 11:45:00 +0530
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Subject: [PATCH] msm: pinctrl: Add support to configure ipq40xx GPIO_PULL bits
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GPIO_PULL bits configurations in TLMM_GPIO_CFG register
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differs for IPQ40xx from rest of the other qcom SoC's.
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This change add support to configure the msm_gpio_pull
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bits for ipq40xx, It is required to fix the proper
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configurations of gpio-pull bits for nand pins mux.
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IPQ40xx SoC:
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2'b10: Internal pull up enable.
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2'b11: Unsupport
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For other SoC's:
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2'b10: Keeper
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2'b11: Pull-Up
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Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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---
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drivers/pinctrl/qcom/pinctrl-apq8064.c | 1 +
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drivers/pinctrl/qcom/pinctrl-apq8084.c | 1 +
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drivers/pinctrl/qcom/pinctrl-ipq4019.c | 8 ++++++++
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drivers/pinctrl/qcom/pinctrl-ipq8064.c | 1 +
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drivers/pinctrl/qcom/pinctrl-mdm9615.c | 1 +
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drivers/pinctrl/qcom/pinctrl-msm.c | 21 ++++++++-------------
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drivers/pinctrl/qcom/pinctrl-msm.h | 19 +++++++++++++++++++
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drivers/pinctrl/qcom/pinctrl-msm8660.c | 1 +
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drivers/pinctrl/qcom/pinctrl-msm8916.c | 1 +
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drivers/pinctrl/qcom/pinctrl-msm8960.c | 1 +
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drivers/pinctrl/qcom/pinctrl-msm8x74.c | 1 +
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11 files changed, 43 insertions(+), 13 deletions(-)
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diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c
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index cd96699..63e9a7e 100644
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--- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
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+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
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@@ -597,6 +597,7 @@ static const struct msm_pinctrl_soc_data apq8064_pinctrl = {
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.groups = apq8064_groups,
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.ngroups = ARRAY_SIZE(apq8064_groups),
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.ngpios = NUM_GPIO_PINGROUPS,
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+ .gpio_pull = &msm_gpio_pull,
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};
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static int apq8064_pinctrl_probe(struct platform_device *pdev)
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diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c
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index d07e8df..892250e 100644
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--- a/drivers/pinctrl/qcom/pinctrl-apq8084.c
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+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
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@@ -1206,6 +1206,7 @@ static const struct msm_pinctrl_soc_data apq8084_pinctrl = {
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.groups = apq8084_groups,
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.ngroups = ARRAY_SIZE(apq8084_groups),
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.ngpios = NUM_GPIO_PINGROUPS,
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+ .gpio_pull = &msm_gpio_pull,
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};
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static int apq8084_pinctrl_probe(struct platform_device *pdev)
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diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
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index 571eb51..040e03c 100644
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--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
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+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
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@@ -1531,6 +1531,13 @@ static const struct msm_pingroup ipq4019_groups[] = {
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PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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};
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+static const struct msm_pinctrl_gpio_pull ipq4019_gpio_pull = {
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+ .no_pull = 0,
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+ .pull_down = 1,
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+ .keeper = 0,
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+ .pull_up = 2,
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+};
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+
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static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
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.pins = ipq4019_pins,
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.npins = ARRAY_SIZE(ipq4019_pins),
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@@ -1539,6 +1546,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
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.groups = ipq4019_groups,
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.ngroups = ARRAY_SIZE(ipq4019_groups),
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.ngpios = 100,
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+ .gpio_pull = &ipq4019_gpio_pull,
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};
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static int ipq4019_pinctrl_probe(struct platform_device *pdev)
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diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
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index bcb29c0..a927251 100644
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--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
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+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
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@@ -630,6 +630,7 @@ static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
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.groups = ipq8064_groups,
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.ngroups = ARRAY_SIZE(ipq8064_groups),
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.ngpios = NUM_GPIO_PINGROUPS,
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+ .gpio_pull = &msm_gpio_pull,
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};
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static int ipq8064_pinctrl_probe(struct platform_device *pdev)
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diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9615.c b/drivers/pinctrl/qcom/pinctrl-mdm9615.c
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index 2b8f452..67e6b75 100644
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--- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c
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+++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c
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@@ -444,6 +444,7 @@ static const struct msm_pinctrl_soc_data mdm9615_pinctrl = {
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.groups = mdm9615_groups,
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.ngroups = ARRAY_SIZE(mdm9615_groups),
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.ngpios = NUM_GPIO_PINGROUPS,
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+ .gpio_pull = &msm_gpio_pull,
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};
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static int mdm9615_pinctrl_probe(struct platform_device *pdev)
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diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
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index c406b61..ae361a1 100644
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--- a/drivers/pinctrl/qcom/pinctrl-msm.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
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@@ -203,11 +203,6 @@ static int msm_config_reg(struct msm_pinctrl *pctrl,
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return 0;
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}
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-#define MSM_NO_PULL 0
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-#define MSM_PULL_DOWN 1
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-#define MSM_KEEPER 2
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-#define MSM_PULL_UP 3
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-
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static unsigned msm_regval_to_drive(u32 val)
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{
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return (val + 1) * 2;
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@@ -238,16 +233,16 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
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/* Convert register value to pinconf value */
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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- arg = arg == MSM_NO_PULL;
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+ arg = arg == pctrl->soc->gpio_pull->no_pull;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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- arg = arg == MSM_PULL_DOWN;
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+ arg = arg == pctrl->soc->gpio_pull->pull_down;
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break;
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case PIN_CONFIG_BIAS_BUS_HOLD:
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- arg = arg == MSM_KEEPER;
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+ arg = arg == pctrl->soc->gpio_pull->keeper;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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- arg = arg == MSM_PULL_UP;
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+ arg = arg == pctrl->soc->gpio_pull->pull_up;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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arg = msm_regval_to_drive(arg);
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@@ -304,16 +299,16 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
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/* Convert pinconf values to register values */
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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- arg = MSM_NO_PULL;
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+ arg = pctrl->soc->gpio_pull->no_pull;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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- arg = MSM_PULL_DOWN;
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+ arg = pctrl->soc->gpio_pull->pull_down;
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break;
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case PIN_CONFIG_BIAS_BUS_HOLD:
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- arg = MSM_KEEPER;
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+ arg = pctrl->soc->gpio_pull->keeper;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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- arg = MSM_PULL_UP;
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+ arg = pctrl->soc->gpio_pull->pull_up;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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/* Check for invalid values */
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diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
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index 54fdd04..090aed9 100644
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--- a/drivers/pinctrl/qcom/pinctrl-msm.h
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
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@@ -98,6 +98,16 @@ struct msm_pingroup {
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};
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/**
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+ * struct msm_pinctrl_gpio_pull - pinctrl pull value bit field descriptor
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+ */
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+struct msm_pinctrl_gpio_pull {
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+ unsigned no_pull;
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+ unsigned pull_down;
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+ unsigned keeper;
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+ unsigned pull_up;
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+};
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+
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+/**
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* struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
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* @pins: An array describing all pins the pin controller affects.
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* @npins: The number of entries in @pins.
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@@ -106,6 +116,7 @@ struct msm_pingroup {
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* @groups: An array describing all pin groups the pin SoC supports.
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* @ngroups: The numbmer of entries in @groups.
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* @ngpio: The number of pingroups the driver should expose as GPIOs.
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+ * @gpio_pull_val: The pull value bit field descriptor.
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*/
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struct msm_pinctrl_soc_data {
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const struct pinctrl_pin_desc *pins;
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@@ -115,6 +126,14 @@ struct msm_pinctrl_soc_data {
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const struct msm_pingroup *groups;
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unsigned ngroups;
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unsigned ngpios;
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+ const struct msm_pinctrl_gpio_pull *gpio_pull;
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+};
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+
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+static const struct msm_pinctrl_gpio_pull msm_gpio_pull = {
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+ .no_pull = 0,
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+ .pull_down = 1,
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+ .keeper = 2,
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+ .pull_up = 3,
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};
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int msm_pinctrl_probe(struct platform_device *pdev,
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diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c
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index 5591d09..a8899d9 100644
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--- a/drivers/pinctrl/qcom/pinctrl-msm8660.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c
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@@ -979,6 +979,7 @@ static const struct msm_pinctrl_soc_data msm8660_pinctrl = {
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.groups = msm8660_groups,
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.ngroups = ARRAY_SIZE(msm8660_groups),
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.ngpios = NUM_GPIO_PINGROUPS,
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+ .gpio_pull = &msm_gpio_pull,
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};
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static int msm8660_pinctrl_probe(struct platform_device *pdev)
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diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c
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index 20ebf24..c45c2bb 100644
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--- a/drivers/pinctrl/qcom/pinctrl-msm8916.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c
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@@ -967,6 +967,7 @@ static const struct msm_pinctrl_soc_data msm8916_pinctrl = {
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.groups = msm8916_groups,
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.ngroups = ARRAY_SIZE(msm8916_groups),
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.ngpios = NUM_GPIO_PINGROUPS,
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+ .gpio_pull = &msm_gpio_pull,
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};
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static int msm8916_pinctrl_probe(struct platform_device *pdev)
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diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c
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index ed23e36..9411176 100644
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--- a/drivers/pinctrl/qcom/pinctrl-msm8960.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
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@@ -1244,6 +1244,7 @@ static const struct msm_pinctrl_soc_data msm8960_pinctrl = {
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.groups = msm8960_groups,
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.ngroups = ARRAY_SIZE(msm8960_groups),
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.ngpios = NUM_GPIO_PINGROUPS,
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+ .gpio_pull = &msm_gpio_pull,
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};
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static int msm8960_pinctrl_probe(struct platform_device *pdev)
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diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
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index 9eb63d3..7740875 100644
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--- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
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@@ -1069,6 +1069,7 @@ static const struct msm_pinctrl_soc_data msm8x74_pinctrl = {
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.groups = msm8x74_groups,
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.ngroups = ARRAY_SIZE(msm8x74_groups),
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.ngpios = NUM_GPIO_PINGROUPS,
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+ .gpio_pull = &msm_gpio_pull,
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};
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static int msm8x74_pinctrl_probe(struct platform_device *pdev)
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--
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2.7.2
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