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mediatek: mt7622: rtl8367c: source code spell fixes

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Signed-off-by: Paul Donald <newtwen+github@gmail.com>
This commit is contained in:
Paul Donald 2024-04-03 17:07:06 +02:00 committed by Christian Marangi
parent 81e4aabac3
commit ae192c042c
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GPG Key ID: AC001D09ADBFEAD7
4 changed files with 7 additions and 7 deletions
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2
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_cputag.h
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@ -38,7 +38,7 @@ extern ret_t rtl8367c_setAsicCputagInsertMode(rtk_uint32 mode);
extern ret_t rtl8367c_getAsicCputagInsertMode(rtk_uint32 *pMode);
extern ret_t rtl8367c_setAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 newPri);
extern ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNewPri);
extern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion);
extern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 position);
extern ret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion);
extern ret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode);
extern ret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode);

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_reg.h
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@ -20357,8 +20357,8 @@ auto-generated register address and field data
#define RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_MASK 0x2000
#define RTL8367C_REPORT_FORWARD_OFFSET 12
#define RTL8367C_REPORT_FORWARD_MASK 0x1000
#define RTL8367C_ROBURSTNESS_VAR_OFFSET 9
#define RTL8367C_ROBURSTNESS_VAR_MASK 0xE00
#define RTL8367C_ROBUSTNESS_VAR_OFFSET 9
#define RTL8367C_ROBUSTNESS_VAR_MASK 0xE00
#define RTL8367C_LEAVE_SUPPRESSION_OFFSET 8
#define RTL8367C_LEAVE_SUPPRESSION_MASK 0x100
#define RTL8367C_REPORT_SUPPRESSION_OFFSET 7

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_cputag.c
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@ -259,9 +259,9 @@ ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNe
* Note:
* None
*/
ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion)
ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 position)
{
return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, postion);
return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, position);
}
/* Function Name:
* rtl8367c_getAsicCputagPosition

4
target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c
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@ -429,8 +429,8 @@ ret_t rtl8367c_setAsicIGMPRobVar(rtk_uint32 rob_var)
if(rob_var > RTL8367C_MAX_ROB_VAR)
return RT_ERR_OUT_OF_RANGE;
retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, rob_var);
/* Robustness variable */
retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBUSTNESS_VAR_MASK, rob_var);
if(retVal != RT_ERR_OK)
return retVal;
@ -456,8 +456,8 @@ ret_t rtl8367c_getAsicIGMPRobVar(rtk_uint32 *prob_var)
ret_t retVal;
rtk_uint32 value;
retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, &value);
/* Robustness variable */
retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBUSTNESS_VAR_MASK, &value);
if(retVal != RT_ERR_OK)
return retVal;