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lantiq: 4.19: load PCIe driver after PCI driver
In case a PCI device is physical present, the Lantiq PCI driver need to be loaded prior to the Lantiq PCIe driver. Otherwise none of them will work because updating the BAR 0 of a device attached to the PCIe Bus will fail. Till kernel commit 9667bb039bf6 ("MIPS: lantiq: remove unnecessary of_platform_default_populate call"), the Lantiq PCI driver was probed early in the boot process via plat_of_setup(). Since the mentioned commit, both drivers are probed via of_platform_default_populate_init() and they are probed according to their order in the devicetree source file. If the Lantiq PCI driver is enabled in the devicetree, defer the probing og the Lantiq PCIe driver till the Lantiq PCI driver is probed. Use the presence of a PCU bus as indicater for a loaded Lantiq PCI driver. This way we don't need to shuffle the PCI/PCIe nodes in the devicetree source file, as they are already (correctly) ordered based on the unit address. Signed-off-by: Mathias Kresin <dev@kresin.me>
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@ -41,7 +41,7 @@
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static inline int pcie_ltssm_enable(int pcie_port)
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{
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@@ -1045,8 +1065,9 @@ pcie_rc_initialize(int pcie_port)
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@@ -1045,17 +1065,52 @@ pcie_rc_initialize(int pcie_port)
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return 0;
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}
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@ -52,7 +52,32 @@
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void __iomem *io_map_base;
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int pcie_port;
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int startup_port;
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@@ -1055,7 +1076,17 @@ static int __init ifx_pcie_bios_init(voi
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+ struct device_node *np;
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+ struct pci_bus *bus;
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+
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+ /*
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+ * In case a PCI device is physical present, the Lantiq PCI driver need
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+ * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them
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+ * will work.
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+ *
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+ * In case the lantiq PCI driver is enabled in the device tree, check if
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+ * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already
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+ * registered.
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+ *
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+ * It will fail if there is another PCI controller, this controller is
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+ * registered before the Lantiq PCIe driver is probe and the lantiq PCI
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+ */
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+ np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway");
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+
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+ if (of_device_is_available(np)) {
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+ bus = pci_find_next_bus(bus);
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+
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+ if (!bus)
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+ return -EPROBE_DEFER;
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+ }
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+
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/* Enable AHB Master/ Slave */
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pcie_ahb_pmu_setup();
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startup_port = IFX_PCIE_PORT0;
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@ -71,7 +96,7 @@
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for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
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if (pcie_rc_initialize(pcie_port) == 0) {
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IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n",
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@@ -1067,6 +1098,7 @@ static int __init ifx_pcie_bios_init(voi
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@@ -1067,6 +1122,7 @@ static int __init ifx_pcie_bios_init(voi
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return -ENOMEM;
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}
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ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
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@ -79,7 +104,7 @@
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register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
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/* XXX, clear error status */
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@@ -1083,6 +1115,30 @@ static int __init ifx_pcie_bios_init(voi
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@@ -1083,6 +1139,30 @@ static int __init ifx_pcie_bios_init(voi
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return 0;
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}
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