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ath79: add missing clock name strings in SoC dtsi
For all SoC in the ath79 target, the PLL controller provides 3 main clocks "cpu", "ddr" and "ahb" through the input clock "ref". Signed-off-by: Shiji Yang <yangshiji66@qq.com>
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520c90854c
commit
8d4c22a956
@ -28,6 +28,12 @@
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bootargs = "console=ttyATH0,115200";
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};
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ref: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "ref";
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};
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ahb {
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apb {
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ddr_ctrl: memory-controller@18000000 {
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@ -83,7 +89,11 @@
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compatible = "qca,ar9330-pll";
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reg = <0x18050000 0x100>;
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clocks = <&ref>;
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clock-names = "ref";
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#clock-cells = <1>;
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clock-output-names = "cpu", "ddr", "ahb";
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};
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wdt: wdt@18060008 {
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@ -4,9 +4,4 @@
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/ {
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compatible = "qca,ar9331";
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ref: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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@ -104,7 +104,9 @@
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#clock-cells = <1>;
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clock-output-names = "cpu", "ddr", "ahb";
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clocks = <&extosc>;
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clock-names = "ref";
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};
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wdt: wdt@18060008 {
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@ -119,6 +119,7 @@
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clock-output-names = "cpu", "ddr", "ahb";
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clocks = <&extosc>;
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clock-names = "ref";
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};
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wdt: wdt@18060008 {
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@ -95,6 +95,7 @@
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clock-output-names = "cpu", "ddr", "ahb";
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clocks = <&extosc>;
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clock-names = "ref";
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};
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wdt: wdt@18060008 {
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