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mediatek: filogic: add support for hw i2c, pwm and thermal
Add support for hardware I2C and PWM units found in the Filogic SoCs as well as the CPU thermal support. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle
parent
05501304ed
commit
5d921aa72f
@ -9,6 +9,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt7986-resets.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&gic>;
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@ -199,6 +200,20 @@
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status = "okay";
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};
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7986-pwm";
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reg = <0 0x10048000 0 0x1000>;
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#clock-cells = <1>;
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#pwm-cells = <2>;
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_PWM_SEL>,
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<&infracfg CLK_INFRA_PWM_BSEL>,
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<&infracfg CLK_INFRA_PWM1_CK>,
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<&infracfg CLK_INFRA_PWM2_CK>;
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clock-names = "top", "main", "pwm1", "pwm2";
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status = "disabled";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
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@ -240,6 +255,20 @@
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status = "disabled";
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};
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i2c0: i2c@11008000 {
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compatible = "mediatek,mt7986-i2c";
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reg = <0 0x11008000 0 0x90>,
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<0 0x10217080 0 0x80>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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clock-div = <5>;
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clocks = <&infracfg CLK_INFRA_I2C0_CK>,
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<&infracfg CLK_INFRA_AP_DMA_CK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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reg = <0 0x1100a000 0 0x100>;
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@ -264,6 +293,16 @@
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status = "disabled";
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};
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auxadc: adc@1100d000 {
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compatible = "mediatek,mt7986-auxadc",
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"mediatek,mt7622-auxadc";
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reg = <0 0x1100d000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
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<&infracfg CLK_INFRA_ADC_FRC_CK>;
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clock-names = "main", "32k";
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#io-channel-cells = <1>;
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};
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ssusb: usb@11200000 {
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compatible = "mediatek,mt7986-xhci",
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"mediatek,mtk-xhci";
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@ -304,6 +343,21 @@
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status = "disabled";
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};
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thermal: thermal@1100c800 {
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#thermal-sensor-cells = <1>;
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compatible = "mediatek,mt7986-thermal";
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reg = <0 0x1100c800 0 0x800>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_THERM_CK>,
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<&infracfg CLK_INFRA_ADC_26M_CK>,
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<&infracfg CLK_INFRA_ADC_FRC_CK>;
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clock-names = "therm", "auxadc", "adc_32k";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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nvmem-cells = <&thermal_calibration>;
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nvmem-cell-names = "calibration-data";
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};
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pcie: pcie@11280000 {
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compatible = "mediatek,mt7986-pcie",
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"mediatek,mt8192-pcie";
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@ -373,7 +427,6 @@
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};
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};
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efuse: efuse@11d00000 {
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compatible = "mediatek,mt7986-efuse",
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"mediatek,efuse";
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@ -609,4 +662,71 @@
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};
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};
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fan: pwm-fan {
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compatible = "pwm-fan";
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/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
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cooling-levels = <0 128 255>;
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#cooling-cells = <2>;
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status = "disabled";
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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thermal-sensors = <&thermal 0>;
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trips {
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cpu_trip_crit: crit {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu_trip_hot: hot {
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temperature = <120000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu_trip_active_high: active-high {
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temperature = <115000>;
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hysteresis = <2000>;
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type = "active";
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};
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cpu_trip_active_low: active-low {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "active";
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};
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cpu_trip_passive: passive {
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temperature = <40000>;
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hysteresis = <2000>;
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type = "passive";
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};
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};
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cooling-maps {
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cpu-active-high {
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/* active: set fan to cooling level 2 */
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cooling-device = <&fan 2 2>;
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trip = <&cpu_trip_active_high>;
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};
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cpu-active-low {
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/* active: set fan to cooling level 1 */
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cooling-device = <&fan 1 1>;
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trip = <&cpu_trip_active_low>;
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};
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cpu-passive {
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/* passive: set fan to cooling level 0 */
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cooling-device = <&fan 0 0>;
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trip = <&cpu_trip_passive>;
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};
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};
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};
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};
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};
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@ -0,0 +1,66 @@
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--- a/drivers/iio/adc/mt6577_auxadc.c
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+++ b/drivers/iio/adc/mt6577_auxadc.c
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@@ -42,6 +42,7 @@ struct mtk_auxadc_compatible {
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struct mt6577_auxadc_device {
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void __iomem *reg_base;
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struct clk *adc_clk;
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+ struct clk *adc_32k_clk;
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struct mutex lock;
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const struct mtk_auxadc_compatible *dev_comp;
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};
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@@ -222,6 +223,12 @@ static int __maybe_unused mt6577_auxadc_
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return ret;
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}
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+ ret = clk_prepare_enable(adc_dev->adc_32k_clk);
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+ if (ret) {
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+ pr_err("failed to enable auxadc clock\n");
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+ return ret;
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+ }
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+
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
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MT6577_AUXADC_PDN_EN, 0);
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mdelay(MT6577_AUXADC_POWER_READY_MS);
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@@ -236,6 +243,8 @@ static int __maybe_unused mt6577_auxadc_
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
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0, MT6577_AUXADC_PDN_EN);
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+
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+ clk_disable_unprepare(adc_dev->adc_32k_clk);
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clk_disable_unprepare(adc_dev->adc_clk);
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return 0;
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@@ -277,6 +286,17 @@ static int mt6577_auxadc_probe(struct pl
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return ret;
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}
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+ adc_dev->adc_32k_clk = devm_clk_get(&pdev->dev, "32k");
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+ if (IS_ERR(adc_dev->adc_32k_clk)) {
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+ dev_err(&pdev->dev, "failed to get auxadc 32k clock\n");
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+ } else {
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+ ret = clk_prepare_enable(adc_dev->adc_32k_clk);
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+ if (ret) {
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+ dev_err(&pdev->dev, "failed to enable auxadc 32k clock\n");
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+ return ret;
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+ }
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+ }
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+
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adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
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if (!adc_clk_rate) {
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ret = -EINVAL;
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@@ -306,6 +326,7 @@ err_power_off:
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
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0, MT6577_AUXADC_PDN_EN);
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err_disable_clk:
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+ clk_disable_unprepare(adc_dev->adc_32k_clk);
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clk_disable_unprepare(adc_dev->adc_clk);
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return ret;
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}
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@@ -320,6 +341,7 @@ static int mt6577_auxadc_remove(struct p
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
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0, MT6577_AUXADC_PDN_EN);
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+ clk_disable_unprepare(adc_dev->adc_32k_clk);
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clk_disable_unprepare(adc_dev->adc_clk);
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return 0;
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@ -0,0 +1,30 @@
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--- a/drivers/i2c/busses/i2c-mt65xx.c
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+++ b/drivers/i2c/busses/i2c-mt65xx.c
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@@ -365,6 +365,19 @@ static const struct mtk_i2c_compatible m
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.max_dma_support = 32,
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};
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+static const struct mtk_i2c_compatible mt7986_compat = {
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+ .quirks = &mt7622_i2c_quirks,
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+ .regs = mt_i2c_regs_v1,
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+ .pmic_i2c = 0,
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+ .dcm = 1,
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+ .auto_restart = 1,
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+ .aux_len_reg = 1,
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+ .max_dma_support = 32,
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+ .timing_adjust = 0,
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+ .dma_sync = 1,
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+ .ltiming_adjust = 0,
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+};
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+
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static const struct mtk_i2c_compatible mt8173_compat = {
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.regs = mt_i2c_regs_v1,
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.pmic_i2c = 0,
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@@ -411,6 +424,7 @@ static const struct of_device_id mtk_i2c
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{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
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{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
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{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
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+ { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
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{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
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{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
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{ .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
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@ -0,0 +1,23 @@
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--- a/drivers/pwm/pwm-mediatek.c
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+++ b/drivers/pwm/pwm-mediatek.c
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@@ -302,6 +302,12 @@ static const struct pwm_mediatek_of_data
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.has_ck_26m_sel = true,
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};
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+static const struct pwm_mediatek_of_data mt7986_pwm_data = {
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+ .num_pwms = 2,
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+ .pwm45_fixup = false,
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+ .has_ck_26m_sel = false,
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+};
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+
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static const struct pwm_mediatek_of_data mt8516_pwm_data = {
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.num_pwms = 5,
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.pwm45_fixup = false,
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@@ -314,6 +320,7 @@ static const struct of_device_id pwm_med
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{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
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{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
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{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
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+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
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{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
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{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
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{ },
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@ -0,0 +1,284 @@
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From cd47d86ab09f1f3ec5c86441d4fe95e0cf597c06 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 13 Sep 2022 00:56:24 +0100
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Subject: [PATCH] thermal/drivers/mediatek: add support for MT7986 and MT7981
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Add support for V3 generation thermal found in MT7986 and MT7981 SoCs.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/thermal/mtk_thermal.c | 202 +++++++++++++++++++++++++++++++++-
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1 file changed, 198 insertions(+), 4 deletions(-)
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--- a/drivers/thermal/mtk_thermal.c
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+++ b/drivers/thermal/mtk_thermal.c
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@@ -150,6 +150,21 @@
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#define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
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#define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
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+/*
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+ * Layout of the fuses providing the calibration data
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+ * These macros could be used for MT7981 and MT7986.
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+ */
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+#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff)
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+#define CALIB_BUF0_ADC_OE_V3(x) (((x) >> 10) & 0x3ff)
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+#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f)
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+#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f)
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+#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff)
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+#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff)
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+#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff)
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+#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1)
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+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1)
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+#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1)
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+
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enum {
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VTS1,
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VTS2,
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@@ -163,6 +178,7 @@ enum {
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enum mtk_thermal_version {
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MTK_THERMAL_V1 = 1,
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MTK_THERMAL_V2,
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+ MTK_THERMAL_V3,
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};
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/* MT2701 thermal sensors */
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@@ -245,6 +261,27 @@ enum mtk_thermal_version {
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/* The calibration coefficient of sensor */
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#define MT8183_CALIBRATION 153
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+/* AUXADC channel 11 is used for the temperature sensors */
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+#define MT7986_TEMP_AUXADC_CHANNEL 11
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+
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+/* The total number of temperature sensors in the MT7986 */
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+#define MT7986_NUM_SENSORS 1
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+
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+/* The number of banks in the MT7986 */
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+#define MT7986_NUM_ZONES 1
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+
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+/* The number of sensing points per bank */
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+#define MT7986_NUM_SENSORS_PER_ZONE 1
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+
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+/* MT7986 thermal sensors */
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+#define MT7986_TS1 0
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+
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+/* The number of controller in the MT7986 */
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+#define MT7986_NUM_CONTROLLER 1
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+
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+/* The calibration coefficient of sensor */
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+#define MT7986_CALIBRATION 165
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+
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struct mtk_thermal;
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struct thermal_bank_cfg {
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@@ -279,6 +316,7 @@ struct mtk_thermal {
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struct clk *clk_peri_therm;
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struct clk *clk_auxadc;
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+ struct clk *clk_adc_32k;
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/* lock: for getting and putting banks */
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struct mutex lock;
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@@ -386,6 +424,14 @@ static const int mt7622_mux_values[MT762
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static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
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static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
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+/* MT7986 thermal sensor data */
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+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
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+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
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+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
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+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
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+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
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+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
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+
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/*
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* The MT8173 thermal controller has four banks. Each bank can read up to
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* four temperature sensors simultaneously. The MT8173 has a total of 5
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@@ -549,6 +595,30 @@ static const struct mtk_thermal_data mt8
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.version = MTK_THERMAL_V1,
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};
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+/*
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+ * MT7986 uses AUXADC Channel 11 for raw data access.
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+ */
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+static const struct mtk_thermal_data mt7986_thermal_data = {
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+ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
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+ .num_banks = MT7986_NUM_ZONES,
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+ .num_sensors = MT7986_NUM_SENSORS,
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+ .vts_index = mt7986_vts_index,
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+ .cali_val = MT7986_CALIBRATION,
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+ .num_controller = MT7986_NUM_CONTROLLER,
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+ .controller_offset = mt7986_tc_offset,
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+ .need_switch_bank = true,
|
||||
+ .bank_data = {
|
||||
+ {
|
||||
+ .num_sensors = 1,
|
||||
+ .sensors = mt7986_bank_data,
|
||||
+ },
|
||||
+ },
|
||||
+ .msr = mt7986_msr,
|
||||
+ .adcpnp = mt7986_adcpnp,
|
||||
+ .sensor_mux_values = mt7986_mux_values,
|
||||
+ .version = MTK_THERMAL_V3,
|
||||
+};
|
||||
+
|
||||
/**
|
||||
* raw_to_mcelsius - convert a raw ADC value to mcelsius
|
||||
* @mt: The thermal controller
|
||||
@@ -603,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk
|
||||
return (format_2 - tmp) * 100;
|
||||
}
|
||||
|
||||
+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
|
||||
+{
|
||||
+ s32 tmp;
|
||||
+
|
||||
+ if (raw == 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ raw &= 0xfff;
|
||||
+ tmp = 100000 * 15 / 16 * 10000;
|
||||
+ tmp /= 4096 - 512 + mt->adc_ge;
|
||||
+ tmp /= 1490;
|
||||
+ tmp *= raw - mt->vts[sensno] - 2900;
|
||||
+
|
||||
+ return mt->degc_cali * 500 - tmp;
|
||||
+}
|
||||
+
|
||||
/**
|
||||
* mtk_thermal_get_bank - get bank
|
||||
* @bank: The bank
|
||||
@@ -659,9 +745,12 @@ static int mtk_thermal_bank_temperature(
|
||||
if (mt->conf->version == MTK_THERMAL_V1) {
|
||||
temp = raw_to_mcelsius_v1(
|
||||
mt, conf->bank_data[bank->id].sensors[i], raw);
|
||||
- } else {
|
||||
+ } else if (mt->conf->version == MTK_THERMAL_V2) {
|
||||
temp = raw_to_mcelsius_v2(
|
||||
mt, conf->bank_data[bank->id].sensors[i], raw);
|
||||
+ } else {
|
||||
+ temp = raw_to_mcelsius_v3(
|
||||
+ mt, conf->bank_data[bank->id].sensors[i], raw);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -887,6 +976,26 @@ static int mtk_thermal_extract_efuse_v2(
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
|
||||
+{
|
||||
+ if (!CALIB_BUF1_VALID_V3(buf[1]))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ mt->adc_oe = CALIB_BUF0_ADC_OE_V3(buf[0]);
|
||||
+ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
|
||||
+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
|
||||
+ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
|
||||
+ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
|
||||
+ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
|
||||
+ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
|
||||
+ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
|
||||
+
|
||||
+ if (CALIB_BUF1_ID_V3(buf[1]) == 0)
|
||||
+ mt->o_slope = 0;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int mtk_thermal_get_calibration_data(struct device *dev,
|
||||
struct mtk_thermal *mt)
|
||||
{
|
||||
@@ -897,6 +1006,7 @@ static int mtk_thermal_get_calibration_d
|
||||
|
||||
/* Start with default values */
|
||||
mt->adc_ge = 512;
|
||||
+ mt->adc_oe = 512;
|
||||
for (i = 0; i < mt->conf->num_sensors; i++)
|
||||
mt->vts[i] = 260;
|
||||
mt->degc_cali = 40;
|
||||
@@ -924,8 +1034,10 @@ static int mtk_thermal_get_calibration_d
|
||||
|
||||
if (mt->conf->version == MTK_THERMAL_V1)
|
||||
ret = mtk_thermal_extract_efuse_v1(mt, buf);
|
||||
- else
|
||||
+ else if (mt->conf->version == MTK_THERMAL_V2)
|
||||
ret = mtk_thermal_extract_efuse_v2(mt, buf);
|
||||
+ else
|
||||
+ ret = mtk_thermal_extract_efuse_v3(mt, buf);
|
||||
|
||||
if (ret) {
|
||||
dev_info(dev, "Device not calibrated, using default calibration values\n");
|
||||
@@ -956,6 +1068,10 @@ static const struct of_device_id mtk_the
|
||||
.data = (void *)&mt7622_thermal_data,
|
||||
},
|
||||
{
|
||||
+ .compatible = "mediatek,mt7986-thermal",
|
||||
+ .data = (void *)&mt7986_thermal_data,
|
||||
+ },
|
||||
+ {
|
||||
.compatible = "mediatek,mt8183-thermal",
|
||||
.data = (void *)&mt8183_thermal_data,
|
||||
}, {
|
||||
@@ -1009,6 +1125,12 @@ static int mtk_thermal_probe(struct plat
|
||||
if (IS_ERR(mt->clk_auxadc))
|
||||
return PTR_ERR(mt->clk_auxadc);
|
||||
|
||||
+ if (mt->conf->version == MTK_THERMAL_V3) {
|
||||
+ mt->clk_adc_32k = devm_clk_get(&pdev->dev, "adc_32k");
|
||||
+ if (IS_ERR(mt->clk_adc_32k))
|
||||
+ return PTR_ERR(mt->clk_adc_32k);
|
||||
+ }
|
||||
+
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(mt->thermal_base))
|
||||
@@ -1058,10 +1180,18 @@ static int mtk_thermal_probe(struct plat
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
+ if (mt->conf->version == MTK_THERMAL_V3) {
|
||||
+ ret = clk_prepare_enable(mt->clk_adc_32k);
|
||||
+ if (ret) {
|
||||
+ dev_err(&pdev->dev, "Can't enable auxadc 32k clk: %d\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
ret = clk_prepare_enable(mt->clk_auxadc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
|
||||
- return ret;
|
||||
+ goto err_disable_clk_adc_32k;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(mt->clk_peri_therm);
|
||||
@@ -1070,7 +1200,8 @@ static int mtk_thermal_probe(struct plat
|
||||
goto err_disable_clk_auxadc;
|
||||
}
|
||||
|
||||
- if (mt->conf->version == MTK_THERMAL_V2) {
|
||||
+ if (mt->conf->version == MTK_THERMAL_V2 ||
|
||||
+ mt->conf->version == MTK_THERMAL_V3) {
|
||||
mtk_thermal_turn_on_buffer(apmixed_base);
|
||||
mtk_thermal_release_periodic_ts(mt, auxadc_base);
|
||||
}
|
||||
@@ -1099,6 +1230,9 @@ err_disable_clk_peri_therm:
|
||||
clk_disable_unprepare(mt->clk_peri_therm);
|
||||
err_disable_clk_auxadc:
|
||||
clk_disable_unprepare(mt->clk_auxadc);
|
||||
+err_disable_clk_adc_32k:
|
||||
+ if (mt->conf->version == MTK_THERMAL_V3)
|
||||
+ clk_disable_unprepare(mt->clk_adc_32k);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -1110,6 +1244,9 @@ static int mtk_thermal_remove(struct pla
|
||||
clk_disable_unprepare(mt->clk_peri_therm);
|
||||
clk_disable_unprepare(mt->clk_auxadc);
|
||||
|
||||
+ if (mt->conf->version == MTK_THERMAL_V3)
|
||||
+ clk_disable_unprepare(mt->clk_adc_32k);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user