mirrors/openwrt
0
0
Fork 0
mirror of https://github.com/openwrt/openwrt.git synced 2024-11-24 10:25:51 +08:00
Code Issues Packages Projects Releases Wiki Activity

mvebu: switch to kernel 6.6

Browse Source 
Update default kernel version to 6.6 and drop configs and patches for
kernel 6.1. We can also omit the conditional to include DTS dir.

Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/15449
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Stefan Kalscheuer 2024-05-10 18:18:48 +02:00 committed by Robert Marko
parent dc9220f748
commit 4b30c2ff0f
59 changed files with 1 additions and 10749 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
target/linux/mvebu/Makefile
View File

@ -9,8 +9,7 @@ BOARDNAME:=Marvell EBU Armada
FEATURES:=fpu usb pci pcie gpio nand squashfs ramdisk boot-part rootfs-part legacy-sdcard targz
SUBTARGETS:=cortexa9 cortexa53 cortexa72
KERNEL_PATCHVER:=6.1
KERNEL_TESTING_PATCHVER:=6.6
KERNEL_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk

447
target/linux/mvebu/config-6.1
View File

@ -1,447 +0,0 @@
CONFIG_AHCI_MVEBU=y
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_MVEBU=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARMADA_370_CLK=y
CONFIG_ARMADA_370_XP_IRQ=y
CONFIG_ARMADA_370_XP_TIMER=y
# CONFIG_ARMADA_37XX_WATCHDOG is not set
CONFIG_ARMADA_38X_CLK=y
CONFIG_ARMADA_THERMAL=y
CONFIG_ARMADA_XP_CLK=y
CONFIG_ARM_APPENDED_DTB=y
# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
CONFIG_ARM_ATAG_DTB_COMPAT=y
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARM_ERRATA_720789=y
CONFIG_ARM_ERRATA_764369=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GLOBAL_TIMER=y
CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_MVEBU_V7_CPUIDLE=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_ATA=y
CONFIG_ATAGS=y
CONFIG_ATA_LEDS=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NVME=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_FEROCEON_L2 is not set
CONFIG_CACHE_L2X0=y
CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PJ4B=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_AES_ARM_BS=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEV_MARVELL=y
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
CONFIG_CRYPTO_ESSIV=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_ARM=y
CONFIG_CRYPTO_SHA1_ARM_NEON=y
CONFIG_CRYPTO_SHA256_ARM=y
CONFIG_CRYPTO_SHA512_ARM=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_ALIGN_RODATA=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
CONFIG_DEBUG_MVEBU_UART0=y
# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
CONFIG_DEBUG_UART_8250=y
CONFIG_DEBUG_UART_8250_SHIFT=2
CONFIG_DEBUG_UART_PHYS=0xd0012000
CONFIG_DEBUG_UART_VIRT=0xfec12000
CONFIG_DEBUG_USER=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_ENGINE_RAID=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_F2FS_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GLOB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_MVEBU=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GRO_CELLS=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HWBM=y
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
CONFIG_HZ_FIXED=0
CONFIG_HZ_PERIODIC=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_PXA is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_IWMMXT is not set
CONFIG_JBD2=y
CONFIG_KMAP_LOCAL=y
CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PCA963X=y
CONFIG_LEDS_TLC591XX=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MACH_ARMADA_370=y
# CONFIG_MACH_ARMADA_375 is not set
CONFIG_MACH_ARMADA_38X=y
# CONFIG_MACH_ARMADA_39X is not set
CONFIG_MACH_ARMADA_XP=y
# CONFIG_MACH_DOVE is not set
CONFIG_MACH_MVEBU_ANY=y
CONFIG_MACH_MVEBU_V7=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MANGLE_BOOTARGS=y
CONFIG_MARVELL_PHY=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_I2C=y
CONFIG_MEMFD_CREATE=y
CONFIG_MEMORY=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_MVSDIO=y
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_PXAV3=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_MVEBU_CLK_COMMON=y
CONFIG_MVEBU_CLK_COREDIV=y
CONFIG_MVEBU_CLK_CPU=y
CONFIG_MVEBU_DEVBUS=y
CONFIG_MVEBU_MBUS=y
CONFIG_MVMDIO=y
CONFIG_MVNETA=y
CONFIG_MVNETA_BM=y
CONFIG_MVNETA_BM_ENABLE=y
# CONFIG_MVPP2 is not set
CONFIG_MV_XOR=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MV88E6XXX=y
CONFIG_NET_DSA_TAG_DSA=y
CONFIG_NET_DSA_TAG_DSA_COMMON=y
CONFIG_NET_DSA_TAG_EDSA=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVME_CORE=y
# CONFIG_NVME_HWMON is not set
# CONFIG_NVME_MULTIPATH is not set
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_ORION_WATCHDOG=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PCI=y
CONFIG_PCI_BRIDGE_EMUL=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_MVEBU=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
# CONFIG_PHY_MVEBU_A3700_COMPHY is not set
# CONFIG_PHY_MVEBU_A3700_UTMI is not set
# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_370=y
CONFIG_PINCTRL_ARMADA_38X=y
CONFIG_PINCTRL_ARMADA_XP=y
CONFIG_PINCTRL_MVEBU=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PJ4B_ERRATA_4742=y
CONFIG_PL310_ERRATA_753970=y
CONFIG_PLAT_ORION=y
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_ARMADA38X=y
# CONFIG_RTC_DRV_MV is not set
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_SATA_HOST=y
CONFIG_SATA_MV=y
CONFIG_SATA_PMP=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
CONFIG_SENSORS_PWM_FAN=y
CONFIG_SENSORS_TMP421=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MVEBU_CONSOLE=y
CONFIG_SERIAL_MVEBU_UART=y
CONFIG_SFP=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
# CONFIG_SPI_ARMADA_3700 is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_ORION=y
CONFIG_SRAM=y
CONFIG_SRAM_EXEC=y
CONFIG_SRCU=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_ORION=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_LEDS_TRIGGER_USBPORT=y
CONFIG_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MVEBU=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

92
target/linux/mvebu/cortexa53/config-6.1
View File

@ -1,92 +0,0 @@
CONFIG_64BIT=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
CONFIG_ARMADA_37XX_CLK=y
CONFIG_ARMADA_37XX_RWTM_MBOX=y
CONFIG_ARMADA_37XX_WATCHDOG=y
CONFIG_ARMADA_AP806_SYSCON=y
CONFIG_ARMADA_AP_CP_HELPER=y
CONFIG_ARMADA_CP110_SYSCON=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_ARM_MHU_V2 is not set
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_ARM_PSCI_FW=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_FRAME_POINTER=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_PINCONF=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_MAILBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_MFD_SYSCON=y
# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MVEBU_GICP=y
CONFIG_MVEBU_ICU=y
CONFIG_MVEBU_ODMI=y
CONFIG_MVEBU_PIC=y
CONFIG_MVEBU_SEI=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI_AARDVARK=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PHY_MVEBU_A3700_COMPHY=y
CONFIG_PHY_MVEBU_A3700_UTMI=y
CONFIG_PINCTRL_AC5=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_PINCTRL_ARMADA_AP806=y
CONFIG_PINCTRL_ARMADA_CP110=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POWER_SUPPLY=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_REGULATOR_GPIO=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPI_ARMADA_3700=y
CONFIG_SWIOTLB=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_TURRIS_MOX_RWTM=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_VMAP_STACK=y
CONFIG_ZONE_DMA32=y

111
target/linux/mvebu/cortexa72/config-6.1
View File

@ -1,111 +0,0 @@
CONFIG_64BIT=y
CONFIG_AQUANTIA_PHY=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_SVE=y
# CONFIG_ARM64_TAGGED_ADDR_ABI is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
CONFIG_ARMADA_37XX_CLK=y
CONFIG_ARMADA_AP806_SYSCON=y
CONFIG_ARMADA_AP_CPU_CLK=y
CONFIG_ARMADA_AP_CP_HELPER=y
CONFIG_ARMADA_CP110_SYSCON=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
CONFIG_ARM_ARMADA_8K_CPUFREQ=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_ARM_PSCI_FW=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CRC_CCITT=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_EEPROM_AT24=y
CONFIG_FRAME_POINTER=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_PINCONF=y
CONFIG_HW_RANDOM_OMAP=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LEDS_IEI_WT61P803_PUZZLE=y
CONFIG_LEDS_IS31FL319X=y
CONFIG_MARVELL_10G_PHY=y
CONFIG_MFD_CORE=y
CONFIG_MFD_IEI_WT61P803_PUZZLE=y
CONFIG_MFD_SYSCON=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MVEBU_GICP=y
CONFIG_MVEBU_ICU=y
CONFIG_MVEBU_ODMI=y
CONFIG_MVEBU_PIC=y
CONFIG_MVEBU_SEI=y
CONFIG_MVPP2=y
CONFIG_MV_XOR_V2=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_NVMEM_LAYOUT_ONIE_TLV=y
CONFIG_NVMEM_SYSFS=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_ARMADA_8K=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCI_AARDVARK is not set
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PHY_MVEBU_CP110_COMPHY=y
CONFIG_PHY_MVEBU_CP110_UTMI=y
CONFIG_PINCTRL_AC5=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_PINCTRL_ARMADA_AP806=y
CONFIG_PINCTRL_ARMADA_CP110=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POWER_SUPPLY=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RAS=y
# CONFIG_RAVE_SP_CORE is not set
CONFIG_REGULATOR_GPIO=y
# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SWIOTLB=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_VMAP_STACK=y
CONFIG_ZONE_DMA32=y

12
target/linux/mvebu/cortexa9/config-6.1
View File

@ -1,12 +0,0 @@
CONFIG_ARM_HAS_GROUP_RELOCS=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
CONFIG_IRQSTACKS=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_MTD_SPLIT_SEIL_FW=y
CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_MTD_VIRT_CONCAT=y
CONFIG_PHY_MVEBU_A38X_COMPHY=y
CONFIG_POWER_RESET_QNAP=y
CONFIG_RTC_DRV_MV=y
CONFIG_THREAD_INFO_IN_TASK=y

376
target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls220de.dts
View File

@ -1,376 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Device Tree file for Buffalo LinkStation LS220DE
*
* Copyright (C) 2023 Daniel González Cabanelas <dgcbueu@gmail.com>
*/
/dts-v1/;
#include "armada-370.dtsi"
#include "mvebu-linkstation-fan.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/thermal/thermal.h>
/ {
model = "Buffalo LinkStation LS220DE";
compatible = "buffalo,ls220de", "marvell,armada370", "marvell,armada-370-xp";
aliases {
led-boot = &led_boot;
led-failsafe = &led_failsafe;
led-running = &led_power;
led-upgrade = &led_upgrade;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
append-rootblock = "nullparameter="; /* override the bootloader args */
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
};
system_fan: gpio_fan {
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH
&gpio0 14 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
#cooling-cells = <2>;
};
thermal-zones {
hdd-thermal {
polling-delay = <20000>;
polling-delay-passive = <2000>;
thermal-sensors = <&hdd0_temp>; /* only one drivetemp sensor is supported */
trips {
hdd_alert1: trip1 {
temperature = <34000>;
hysteresis = <2000>;
type = "active";
};
hdd_alert2: trip2 {
temperature = <40000>;
hysteresis = <2000>;
type = "active";
};
hdd_alert3: trip3 {
temperature = <45000>;
hysteresis = <2000>;
type = "passive";
};
hdd_hot {
temperature = <50000>;
hysteresis = <2000>;
type = "hot";
};
hdd_crit {
temperature = <60000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map1 {
trip = <&hdd_alert1>;
cooling-device = <&system_fan THERMAL_NO_LIMIT 1>;
};
map2 {
trip = <&hdd_alert2>;
cooling-device = <&system_fan 2 2>;
};
map3 {
trip = <&hdd_alert3>;
cooling-device = <&system_fan 3 THERMAL_NO_LIMIT>;
};
};
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&pmx_buttons>;
pinctrl-names = "default";
power {
label = "Power Switch";
linux,code = <KEY_POWER>;
linux,input-type = <EV_SW>;
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
};
function {
label = "Function Button";
linux,code = <KEY_CONFIG>;
gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
};
};
gpio_leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
indicator_red {
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
led_power: power_white {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_failsafe: power_red {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
};
led_upgrade: power_orange {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_AMBER>;
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
};
led_boot: indicator_white {
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_WHITE>;
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
};
hdd1_red {
function = LED_FUNCTION_DISK;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "ata1";
function-enumerator = <1>;
};
hdd2_red {
function = LED_FUNCTION_DISK;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "ata2";
function-enumerator = <2>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_power_hdd1 &pmx_power_hdd2>;
pinctrl-names = "default";
sata1_power: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "HDD1";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
startup-delay-us = <2000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
};
sata2_power: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "HDD2";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
startup-delay-us = <4000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
};
};
};
&coherencyfab {
broken-idle;
};
&eth1 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy-handle = <&ethphy0>;
phy-connection-type = "rgmii-id";
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
marvell,reg-init = <0x3 0x10 0xf000 0x091A>, /* LED function */
<0x3 0x11 0x0000 0x4401>, /* LED polarity */
<0x3 0x12 0x0000 0x4905>; /* LED timer */
#thermal-sensor-cells = <0>;
};
};
&nand_controller {
status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ubi_kernel";
reg = <0x00000000 0x02000000>; /* 32 MiB */
};
partition@2000000 {
label = "ubi";
reg = <0x02000000 0x1df00000>; /* 479 MiB */
};
};
};
};
&sata {
nr-ports = <2>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
hdd0_temp: sata-port@0 {
reg = <0>;
#thermal-sensor-cells = <0>;
};
hdd1_temp: sata-port@1 {
reg = <1>;
#thermal-sensor-cells = <0>;
};
};
&spi0 {
status = "okay";
pinctrl-0 = <&spi0_pins2>;
pinctrl-names = "default";
spi-flash@0 {
compatible = "mxicy,mx25l8005", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000 0xf0000>; /* 960 KiB*/
label = "u-boot";
read-only;
};
partition@f0000 {
reg = <0xf0000 0x10000>; /* 64 KiB */
label = "u-boot-env";
};
};
};
};
&pmsu {
pinctrl-0 = <&pmx_power_cpu>;
pinctrl-names = "default";
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
};
&pinctrl {
pmx_power_hdd2: pmx-power-hdd2 {
marvell,pins = "mpp2";
marvell,function = "gpio";
};
pmx_power_cpu: pmx-power-cpu {
marvell,pins = "mpp4";
marvell,function = "vdd";
};
pmx_power_hdd1: pmx-power-hdd1 {
marvell,pins = "mpp8";
marvell,function = "gpio";
};
pmx_fan_lock: pmx-fan-lock {
marvell,pins = "mpp10";
marvell,function = "gpio";
};
pmx_hdd_present: pmx-hdd-present {
marvell,pins = "mpp11", "mpp12";
marvell,function = "gpio";
};
pmx_fan_high: pmx-fan-high {
marvell,pins = "mpp13";
marvell,function = "gpio";
};
pmx_fan_low: pmx-fan-low {
marvell,pins = "mpp14";
marvell,function = "gpio";
};
pmx_buttons: pmx-buttons {
marvell,pins = "mpp15", "mpp16";
marvell,function = "gpio";
};
pmx_leds1: pmx-leds {
marvell,pins = "mpp7", "mpp54", "mpp59", "mpp61";
marvell,function = "gpo";
};
pmx_leds2: pmx-leds {
marvell,pins = "mpp55", "mpp57", "mpp62";
marvell,function = "gpio";
};
};

448
target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls421de.dts
View File

@ -1,448 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Device Tree file for Buffalo LinkStation LS421DE
*
* Copyright (C) 2020 Daniel González Cabanelas <dgcbueu@gmail.com>
*/
/dts-v1/;
#include "armada-370.dtsi"
#include "mvebu-linkstation-fan.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
/ {
model = "Buffalo LinkStation LS421DE";
compatible = "buffalo,ls421de", "marvell,armada370", "marvell,armada-370-xp";
aliases {
led-boot = &led_boot;
led-failsafe = &led_failsafe;
led-running = &led_power;
led-upgrade = &led_upgrade;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
append-rootblock = "nullparameter="; /* override the bootloader args */
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
};
system_fan: gpio_fan {
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH
&gpio0 14 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
#cooling-cells = <2>;
};
thermal-zones {
hdd-thermal {
polling-delay = <20000>;
polling-delay-passive = <2000>;
thermal-sensors = <&hdd0_temp>; /* only one drivetemp sensor is supported */
trips {
hdd_alert1: trip1 {
temperature = <36000>;
hysteresis = <2000>;
type = "active";
};
hdd_alert2: trip2 {
temperature = <44000>;
hysteresis = <2000>;
type = "active";
};
hdd_alert3: trip3 {
temperature = <52000>;
hysteresis = <2000>;
type = "passive";
};
hdd_crit: trip4 {
temperature = <60000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map1 {
trip = <&hdd_alert1>;
cooling-device = <&system_fan THERMAL_NO_LIMIT 1>;
};
map2 {
trip = <&hdd_alert2>;
cooling-device = <&system_fan 2 2>;
};
map3 {
trip = <&hdd_alert3>;
cooling-device = <&system_fan 3 THERMAL_NO_LIMIT>;
};
};
};
ethphy-thermal {
polling-delay = <20000>;
polling-delay-passive = <2000>;
thermal-sensors = <&ethphy0>;
trips {
ethphy_alert1: trip1 {
temperature = <65000>;
hysteresis = <4000>;
type = "passive";
};
ethphy_crit: trip2 {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map1 {
trip = <&ethphy_alert1>;
cooling-device = <&system_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&pmx_buttons>;
pinctrl-names = "default";
power {
label = "Power Switch";
linux,code = <KEY_POWER>;
linux,input-type = <EV_SW>;
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
};
function {
label = "Function Button";
linux,code = <KEY_CONFIG>;
gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
};
};
gpio_leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
system_red {
label = "ls421de:red:system";
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
led_power: power_white {
label = "ls421de:white:power";
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_failsafe: power_red {
label = "ls421de:red:power";
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
};
led_upgrade: power_orange {
label = "ls421de:orange:power";
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
};
led_boot: system_white {
label = "ls421de:white:system";
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
};
hdd1_red {
label = "ls421de:red:hdd1";
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "ata1";
};
hdd2_red {
label = "ls421de:red:hdd2";
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "ata2";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_power_usb &pmx_power_hdd1 &pmx_power_hdd2>;
pinctrl-names = "default";
usb_power: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "USB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
};
sata1_power: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "HDD1";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
startup-delay-us = <2000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
};
sata2_power: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "HDD2";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
startup-delay-us = <4000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};
};
};
&coherencyfab {
broken-idle;
};
&eth1 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy-handle = <&ethphy0>;
phy-connection-type = "rgmii-id";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <100000>;
status = "okay";
rs5c372a: rs5c372a@32 {
compatible = "ricoh,rs5c372a";
reg = <0x32>;
wakeup-source;
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
ethphy0: ethernet-phy@0 { /* Marvell 88E1518 */
reg = <0>;
marvell,reg-init = <0x2 0x10 0xffff 0x0006>, /* disable CLK125 */
<0x3 0x10 0x0000 0x1991>, /* LED function */
<0x3 0x11 0x0000 0x4401>, /* LED polarity */
<0x3 0x12 0x0000 0x4905>; /* LED timer */
#thermal-sensor-cells = <0>;
};
};
&pciec {
status = "okay";
pinctrl-0 = <&pmx_pcie>;
pinctrl-names = "default";
/* Connected to uPD720202 USB 3.0 Host */
pcie@1,0 {
status = "okay";
};
};
&pmsu {
pinctrl-0 = <&pmx_power_cpu>;
pinctrl-names = "default";
};
&rtc {
status = "disabled";
};
&sata {
nr-ports = <2>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
hdd0_temp: sata-port@0 {
reg = <0>;
#thermal-sensor-cells = <0>;
};
hdd1_temp: sata-port@1 {
reg = <1>;
#thermal-sensor-cells = <0>;
};
};
&sdio {
pinctrl-0 = <&sdio_pins2>;
pinctrl-names = "default";
status = "okay";
/* No CD or WP GPIOs */
broken-cd;
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
};
&nand_controller {
status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x00000000 0x02000000>; /* 32 MiB */
};
partition@2000000 {
label = "ubi";
reg = <0x02000000 0x1e000000>; /* 480 MiB */
};
};
};
};
&spi0 {
status = "okay";
pinctrl-0 = <&spi0_pins2>;
pinctrl-names = "default";
spi-flash@0 {
compatible = "mxicy,mx25l8005", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000 0xf0000>; /* 960 KiB*/
label = "u-boot";
read-only;
};
partition@f0000 {
reg = <0xf0000 0x10000>; /* 64 KiB */
label = "u-boot-env";
};
};
};
};
&pinctrl {
pmx_power_cpu: pmx-power-cpu {
marvell,pins = "mpp4";
marvell,function = "vdd";
};
pmx_power_usb: pmx-power-usb {
marvell,pins = "mpp5";
marvell,function = "gpo";
};
pmx_power_hdd1: pmx-power-hdd1 {
marvell,pins = "mpp8";
marvell,function = "gpio";
};
pmx_power_hdd2: pmx-power-hdd2 {
marvell,pins = "mpp9";
marvell,function = "gpo";
};
pmx_fan_lock: pmx-fan-lock {
marvell,pins = "mpp10";
marvell,function = "gpio";
};
pmx_hdd_present: pmx-hdd-present {
marvell,pins = "mpp11", "mpp12";
marvell,function = "gpio";
};
pmx_fan_high: pmx-fan-high {
marvell,pins = "mpp13";
marvell,function = "gpio";
};
pmx_fan_low: pmx-fan-low {
marvell,pins = "mpp14";
marvell,function = "gpio";
};
pmx_buttons: pmx-buttons {
marvell,pins = "mpp15", "mpp16";
marvell,function = "gpio";
};
pmx_leds1: pmx-leds {
marvell,pins = "mpp7", "mpp54", "mpp59", "mpp61";
marvell,function = "gpo";
};
pmx_leds2: pmx-leds {
marvell,pins = "mpp55", "mpp57", "mpp62";
marvell,function = "gpio";
};
pmx_pcie: pmx-pcie {
marvell,pins = "mpp56", "mpp60";
marvell,function = "pcie";
};
};

424
target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-c200-v2.dts
View File

@ -1,424 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Device Tree file for Ctera C200-V2
*
* Copyright (C) 2021 Pawel Dembicki <paweldembicki@gmail.com>
*/
/dts-v1/;
#include "armada-370.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Ctera C200 V2";
compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp";
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_red;
led-running = &led_status_green;
led-upgrade = &led_status_red;
};
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1024 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
};
thermal-zones {
ethphy-thermal {
polling-delay = <20000>;
polling-delay-passive = <2000>;
thermal-sensors = <&ethphy0>;
trips {
ethphy_alert1: trip1 {
temperature = <65000>;
hysteresis = <4000>;
type = "passive";
};
ethphy_crit: trip2 {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&pmx_buttons>;
pinctrl-names = "default";
power {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
};
reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
usb1 {
label = "USB1 Button";
linux,code = <BTN_0>;
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
};
usb2 {
label = "USB2 Button";
linux,code = <BTN_1>;
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
pinctrl-0 = <&pmx_poweroff>;
pinctrl-names = "default";
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
pinctrl-names = "default";
led-0 {
function = LED_FUNCTION_USB;
function-enumerator = <2>;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
};
led-1 {
function = LED_FUNCTION_USB;
function-enumerator = <2>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "usbport";
trigger-sources = <&usb1_port 1>, <&usb2_port 1>;
};
led-2 {
function = LED_FUNCTION_USB;
function-enumerator = <1>;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
};
led-3 {
function = LED_FUNCTION_USB;
function-enumerator = <1>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
linux,default-trigger = "usbport";
trigger-sources = <&usb1_port 2>, <&usb2_port 2>;
};
led-4 {
function = LED_FUNCTION_DISK;
function-enumerator = <2>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "ata2";
};
led-5 {
function = LED_FUNCTION_DISK;
function-enumerator = <1>;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
};
led-6 {
function = LED_FUNCTION_DISK;
function-enumerator = <2>;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
};
led-7 {
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
};
led-8 {
function = LED_FUNCTION_DISK_ERR;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
};
led-9 {
function = LED_FUNCTION_DISK_ERR;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
};
led_status_red: led-10 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
};
led-11 {
function = LED_FUNCTION_DISK;
function-enumerator = <1>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
linux,default-trigger = "ata1";
};
led_status_green: led-12 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
};
};
};
&coherencyfab {
broken-idle;
};
&eth1 {
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy-handle = <&ethphy0>;
phy-connection-type = "rgmii-id";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <100000>;
status = "okay";
hwmon@2a {
compatible = "nuvoton,nct7802";
reg = <0x2a>;
};
rtc@30 {
compatible = "sii,s35390a";
reg = <0x30>;
};
};
&mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
#thermal-sensor-cells = <0>;
};
};
&nand_controller {
status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "uboot";
reg = <0x0000000 0x200000>;
read-only;
};
partition@200000 {
label = "certificate";
reg = <0x0200000 0x100000>;
read-only;
};
partition@300000 {
label = "preset_cfg";
reg = <0x0300000 0x100000>;
read-only;
};
partition@400000 {
label = "dev_params";
reg = <0x0400000 0x100000>;
read-only;
};
partition@500000 {
label = "active_bank";
reg = <0x0500000 0x0100000>;
};
partition@600000 {
label = "magic";
reg = <0x0600000 0x0100000>;
read-only;
};
partition@700000 {
label = "bank1";
reg = <0x0700000 0x2800000>;
};
partition@2f00000 {
label = "bank2";
reg = <0x2f00000 0x2800000>;
};
/* 0x5700000-0x5a00000 undefined in vendor firmware */
partition@5a00000 {
label = "reserved";
reg = <0x5a00000 0x2000000>;
};
partition@7a00000 {
label = "ubi";
reg = <0x7a00000 0x8600000>;
};
};
};
};
&pciec {
status = "okay";
pcie@1,0 {
pinctrl-0 = <&pmx_pcie>;
pinctrl-names = "default";
status = "okay";
reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
/* -[0000:00]---01.0-[01]----00.0 */
/* usbport trigger won't work */
bridge@0,1 {
compatible = "pci11ab,6710";
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
usb@1,0 {
/* Renesas uPD720202 */
compatible = "pci1912,0015";
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
usb1_port: port@1 {
reg = <1>;
#trigger-source-cells = <1>;
};
usb2_port: port@2 {
reg = <2>;
#trigger-source-cells = <1>;
};
};
};
};
};
&pinctrl {
pmx_poweroff: pmx-poweroff {
marvell,pins = "mpp7";
marvell,function = "gpo";
};
pmx_power_cpu: pmx-power-cpu {
marvell,pins = "mpp4";
marvell,function = "vdd";
};
pmx_buttons: pmx-buttons {
marvell,pins = "mpp6", "mpp10", "mpp14", "mpp32";
marvell,function = "gpio";
};
pmx_leds1: pmx-leds1 {
marvell,pins = "mpp47";
marvell,function = "gpo";
};
pmx_leds2: pmx-leds2 {
marvell,pins = "mpp12", "mpp13", "mpp15", "mpp16", "mpp50", "mpp51",
"mpp52", "mpp53", "mpp55", "mpp56", "mpp57", "mpp58";
marvell,function = "gpio";
};
pmx_pcie: pmx-pcie {
marvell,pins = "mpp59";
marvell,function = "gpio";
};
/* this gpio is connected to the pin of buzzer
* leave it as is due lack of proper driver
*/
pmx_buzzer: pmx-buzzer {
marvell,pins = "mpp63";
marvell,function = "gpio";
};
};
&pmsu {
pinctrl-0 = <&pmx_power_cpu>;
pinctrl-names = "default";
};
&rtc {
status = "disabled";
};
&sata {
nr-ports = <2>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
hdd0_temp: sata-port@0 {
reg = <0>;
#thermal-sensor-cells = <0>;
};
hdd1_temp: sata-port@1 {
reg = <1>;
#thermal-sensor-cells = <0>;
};
};
&uart0 {
status = "okay";
};

389
target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-380-iij-sa-w2.dts
View File

@ -1,389 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "armada-380.dtsi"
/ {
model = "IIJ SA-W2";
compatible = "iij,sa-w2", "marvell,armada380";
aliases {
led-boot = &led_power_green;
led-failsafe = &led_power_red;
led-running = &led_power_green;
led-upgrade = &led_power_green;
label-mac-device = &ge0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
pcie {
status = "okay";
pcie@1,0 {
status = "okay";
};
pcie@3,0 {
status = "okay";
};
};
};
keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pmx_keys_pins>;
button-init {
label = "init";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pmx_leds_pins>;
led-0 {
gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN_5GHZ;
linux,default-trigger = "phy0tpt";
};
led-1 {
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_WLAN_5GHZ;
};
led-2 {
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
};
led-3 {
gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
};
led-4 {
gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_MOBILE;
};
led-5 {
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_MOBILE;
};
led-6 {
gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN_2GHZ;
linux,default-trigger = "phy1tpt";
};
led-7 {
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_WLAN_2GHZ;
};
led_power_green: led-8 {
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
};
led_power_red: led-9 {
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
};
led-10 {
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_USB;
function-enumerator = <1>;
linux,default-trigger = "usbport";
trigger-sources = <&hub_port2>;
};
led-11 {
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_USB;
function-enumerator = <0>;
linux,default-trigger = "usbport";
trigger-sources = <&hub_port1>;
};
};
regulator-vbus-usb0 {
compatible = "regulator-fixed";
regulator-name = "vbus-usb0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
regulator-vbus-usb1 {
compatible = "regulator-fixed";
regulator-name = "vbus-usb1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 21 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&pinctrl {
pmx_usb_pins: usb-pins {
marvell,pins = "mpp2", /* smsc usb2514b reset */
"mpp48", "mpp49", /* port over current */
"mpp52", "mpp53"; /* port vbus */
marvell,function = "gpio";
};
pmx_keys_pins: keys-pins {
marvell,pins = "mpp18";
marvell,function = "gpio";
};
pmx_leds_pins: leds-pins {
marvell,pins = "mpp19", "mpp20", "mpp33", "mpp34", "mpp35",
"mpp36", "mpp44", "mpp45", "mpp46", "mpp47",
"mpp54", "mpp55";
marvell,function = "gpio";
};
};
&gpio0 {
usb-hub-reset {
gpio-hog;
gpios = <2 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&pmx_usb_pins>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
/* SMSC USB2514B on PCB */
hub@1 {
compatible = "usb424,2514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
hub_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
hub_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
&bm {
status = "okay";
};
&bm_bppi {
status = "okay";
};
&eth1 {
pinctrl-names = "default";
pinctrl-0 = <&ge1_rgmii_pins>;
status = "okay";
phy-connection-type = "rgmii-id";
buffer-manager = <&bm>;
bm,pool-long = <2>;
bm,pool-short = <3>;
nvmem-cells = <&macaddr_bdinfo_6 1>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
/* Marvell 88E6172 */
switch@0 {
compatible = "marvell,mv88e6085";
reg = <0x0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "ge1_0";
};
port@1 {
reg = <1>;
label = "ge1_1";
};
port@2 {
reg = <2>;
label = "ge1_2";
};
port@3 {
reg = <3>;
label = "ge1_3";
};
ge0: port@4 {
reg = <4>;
label = "ge0";
nvmem-cells = <&macaddr_bdinfo_6 0>;
nvmem-cell-names = "mac-address";
};
/*
* eth0 is connected to port5 for WAN connection
* on port4 ("GE0")
*/
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&eth1>;
phy-connection-type = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
&rtc {
status = "disabled";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x100000>;
label = "bootloader";
read-only;
};
partition@100000 {
reg = <0x100000 0x10000>;
label = "bootloader-env";
read-only;
};
partition@110000 {
reg = <0x110000 0xf0000>;
label = "board_info";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_bdinfo_6: macaddr@6 {
compatible = "mac-base";
reg = <0x6 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@200000 {
compatible = "iij,seil-firmware";
reg = <0x200000 0xf00000>;
label = "firmware";
iij,bootdev-name = "flash";
iij,seil-id = <0x5345494c 0x32303135>;
};
partition@1100000 {
compatible = "iij,seil-firmware";
reg = <0x1100000 0xf00000>;
label = "rescue";
iij,bootdev-name = "rescue";
iij,seil-id = <0x5345494c 0x32303135>;
};
};
};
};

99
target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-30e.dts
View File

@ -1,99 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "armada-385-fortinet-fg-x0e.dtsi"
/ {
model = "Fortinet FortiGate 30E";
compatible = "fortinet,fg-30e", "marvell,armada385", "marvell,armada380";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1GB */
};
};
&gpio_leds {
led-14 {
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_SPEED_WAN;
linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
};
led-15 {
gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_SPEED_WAN;
linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
};
};
&pinctrl {
pmx_switch_pins: switch-pins {
marvell,pins = "mpp19";
marvell,function = "gpio";
};
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>, <&pmx_switch_pins>;
/* Marvell 88E6176 */
switch@2 {
compatible = "marvell,mv88e6085";
reg = <0x2>;
reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
nvmem-cells = <&macaddr_bdinfo_d880 1>;
nvmem-cell-names = "mac-address";
};
port@1 {
reg = <1>;
label = "lan4";
nvmem-cells = <&macaddr_bdinfo_d880 5>;
nvmem-cell-names = "mac-address";
};
port@2 {
reg = <2>;
label = "lan3";
nvmem-cells = <&macaddr_bdinfo_d880 4>;
nvmem-cell-names = "mac-address";
};
port@3 {
reg = <3>;
label = "lan2";
nvmem-cells = <&macaddr_bdinfo_d880 3>;
nvmem-cell-names = "mac-address";
};
port@4 {
reg = <4>;
label = "lan1";
nvmem-cells = <&macaddr_bdinfo_d880 2>;
nvmem-cell-names = "mac-address";
};
port@6 {
reg = <6>;
ethernet = <&eth0>;
phy-connection-type = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};

175
target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts
View File

@ -1,175 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "armada-385-fortinet-fg-x0e.dtsi"
/ {
model = "Fortinet FortiGate 50E";
compatible = "fortinet,fg-50e", "marvell,armada385", "marvell,armada380";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2GB */
};
};
&gpio_leds {
led-14 {
gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_SPEED_WAN;
function-enumerator = <1>;
linux,default-trigger = "f1072004.mdio-mii:00:1Gbps";
};
led-15 {
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_SPEED_WAN;
function-enumerator = <2>;
linux,default-trigger = "f1072004.mdio-mii:01:1Gbps";
};
led-16 {
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_SPEED_LAN;
function-enumerator = <5>;
linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
};
led-17 {
gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_SPEED_LAN;
function-enumerator = <5>;
linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
};
};
&pinctrl {
pmx_phy_switch_pins: phy-switch-pins {
marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41";
marvell,function = "gpio";
};
};
&eth1 {
status = "okay";
phy-handle = <&ethphy0>;
phy-connection-type = "sgmii";
buffer-manager = <&bm>;
bm,pool-long = <2>;
nvmem-cells = <&macaddr_bdinfo_d880 1>;
nvmem-cell-names = "mac-address";
};
&eth2 {
status = "okay";
phy-handle = <&ethphy1>;
phy-connection-type = "sgmii";
buffer-manager = <&bm>;
bm,pool-long = <3>;
nvmem-cells = <&macaddr_bdinfo_d880 2>;
nvmem-cell-names = "mac-address";
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>;
/* Marvell 88E1512 */
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0141,0dd1",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio0>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
/*
* LINK/ACT (Green): LED[0], Active Low
* SPEED 100M (Amber): LED[1], Active High
*/
marvell,reg-init = <3 16 0 0x71>,
<3 17 0 0x4>;
};
/* Marvell 88E1512 */
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0141,0dd1",
"ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
/*
* LINK/ACT (Green): LED[0], Active Low
* SPEED 100M (Amber): LED[1], Active High
*/
marvell,reg-init = <3 16 0 0x71>,
<3 17 0 0x4>;
};
/* Marvell 88E6176 */
switch@2 {
compatible = "marvell,mv88e6085";
reg = <0x2>;
reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan5";
nvmem-cells = <&macaddr_bdinfo_d880 7>;
nvmem-cell-names = "mac-address";
};
port@1 {
reg = <1>;
label = "lan4";
nvmem-cells = <&macaddr_bdinfo_d880 6>;
nvmem-cell-names = "mac-address";
};
port@2 {
reg = <2>;
label = "lan3";
nvmem-cells = <&macaddr_bdinfo_d880 5>;
nvmem-cell-names = "mac-address";
};
port@3 {
reg = <3>;
label = "lan2";
nvmem-cells = <&macaddr_bdinfo_d880 4>;
nvmem-cell-names = "mac-address";
};
port@4 {
reg = <4>;
label = "lan1";
nvmem-cells = <&macaddr_bdinfo_d880 3>;
nvmem-cell-names = "mac-address";
};
port@6 {
reg = <6>;
ethernet = <&eth0>;
phy-connection-type = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};

346
target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-x0e.dtsi
View File

@ -1,346 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "armada-385.dtsi"
/ {
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_red;
led-running = &led_status_green;
led-upgrade = &led_status_green;
label-mac-device = &eth0;
};
chosen {
stdout-path = "serial0:9600n8";
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pmx_gpio_keys_pins>;
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
};
};
gpio_leds: gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pmx_gpio_leds_pins>;
led-0 {
gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_ALARM;
};
led-1 {
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_RED>;
function = "ha";
};
led_status_green: led-2 {
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
};
led-3 {
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = "ha";
};
led-4 {
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_ALARM;
};
led_status_red: led-5 {
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
};
led-6 {
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_SPEED_LAN;
function-enumerator = <4>;
linux,default-trigger = "mv88e6xxx-1:01:1Gbps";
};
led-7 {
gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_SPEED_LAN;
function-enumerator = <4>;
linux,default-trigger = "mv88e6xxx-1:01:100Mbps";
};
led-8 {
gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_SPEED_LAN;
function-enumerator = <3>;
linux,default-trigger = "mv88e6xxx-1:02:100Mbps";
};
led-9 {
gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_SPEED_LAN;
function-enumerator = <3>;
linux,default-trigger = "mv88e6xxx-1:02:1Gbps";
};
led-10 {
gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_SPEED_LAN;
function-enumerator = <1>;
linux,default-trigger = "mv88e6xxx-1:04:1Gbps";
};
led-11 {
gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_SPEED_LAN;
function-enumerator = <1>;
linux,default-trigger = "mv88e6xxx-1:04:100Mbps";
};
led-12 {
gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_SPEED_LAN;
function-enumerator = <2>;
linux,default-trigger = "mv88e6xxx-1:03:1Gbps";
};
led-13 {
gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_SPEED_LAN;
function-enumerator = <2>;
linux,default-trigger = "mv88e6xxx-1:03:100Mbps";
};
};
reg_usb_vbus: regulator-usb-vbus {
compatible = "fixed-regulator";
regulator-name = "usb-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
regulator-always-on;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
gpio2: gpio@24 {
compatible = "nxp,pca9555";
reg = <0x24>;
gpio-controller;
#gpio-cells = <0x2>;
};
hwmon@28 {
compatible = "nuvoton,nct7802";
reg = <0x28>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&pinctrl {
pmx_gpio_leds_pins: gpio-leds-pins {
marvell,pins = "mpp30", "mpp32", "mpp33", "mpp35",
"mpp45", "mpp47";
marvell,function = "gpio";
};
pmx_usb_pins: usb-pins {
marvell,pins = "mpp53";
marvell,function = "gpio";
};
pmx_gpio_keys_pins: gpio-keys-pins {
marvell,pins = "mpp54";
marvell,function = "gpio";
};
};
&bm {
status = "okay";
};
&bm_bppi {
status = "okay";
};
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&ge0_rgmii_pins>;
status = "okay";
phy-connection-type = "rgmii-id";
buffer-manager = <&bm>;
bm,pool-long = <0>;
bm,pool-short = <1>;
nvmem-cells = <&macaddr_bdinfo_d880 0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&usb3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pmx_usb_pins>;
status = "okay";
vbus-supply = <&reg_usb_vbus>;
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x1c0000>;
label = "u-boot";
read-only;
};
partition@1c0000 {
reg = <0x1c0000 0x10000>;
label = "firmware-info";
/*
* 0x10 - 0x2f : image name (image1)
* 0x30 - 0x4f : image name (image2)
* 0x170 (1byte): active image (0x0/0x1)
* 0x184 - 0x185: kernel block count (image1)
* 0x18c - 0x18d: rootfs block count (image1)
* 0x194 - 0x195: kernel block count (image2)
* 0x19c - 0x19d: rootfs block count (image2)
* 0x1be (1byte): bit7 -> active flag (image1)?
* 0x1ce (1byte): bit7 -> active flag (image2)?
*
* Note: block size --> 0x200 (512 bytes)
*/
};
partition@1d0000 {
reg = <0x1d0000 0x10000>;
label = "dtb";
read-only;
};
partition@1e0000 {
reg = <0x1e0000 0x10000>;
label = "u-boot-env";
read-only;
};
partition@1f0000 {
reg = <0x1f0000 0x10000>;
label = "board-info";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_bdinfo_d880: macaddr@d880 {
compatible = "mac-base";
reg = <0xd880 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@200000 {
reg = <0x200000 0x600000>;
label = "kernel";
};
partition@800000 {
reg = <0x800000 0x1800000>;
label = "rootfs";
};
partition@2000000 {
reg = <0x2000000 0x600000>;
label = "kn2";
read-only;
};
partition@2600000 {
reg = <0x2600000 0x1800000>;
label = "rfs2";
read-only;
};
partition@3e00000 {
reg = <0x3e00000 0x1200000>;
label = "part1";
read-only;
};
partition@5000000 {
reg = <0x5000000 0x1200000>;
label = "part2";
read-only;
};
partition@6200000 {
reg = <0x6200000 0x1e00000>;
label = "config";
read-only;
};
};
};
};

213
target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-linksys-venom.dts
View File

@ -1,213 +0,0 @@
/*
* Device Tree file for the Linksys WRT32X (Venom)
*
* Copyright (C) 2017 Imre Kaloz <kaloz@openwrt.org>
*
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-385-linksys.dtsi"
/ {
model = "Linksys WRT32X";
compatible = "linksys,wrt32x", "linksys,venom", "linksys,armada385",
"marvell,armada385", "marvell,armada380";
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = "serial0:115200n8";
append-rootblock = "root=/dev/mtdblock";
};
};
&expander0 {
wan_amber@0 {
label = "venom:amber:wan";
reg = <0x0>;
};
wan_blue@1 {
label = "venom:blue:wan";
reg = <0x1>;
};
usb2@5 {
label = "venom:blue:usb2";
reg = <0x5>;
};
usb3_1@6 {
label = "venom:blue:usb3_1";
reg = <0x6>;
};
usb3_2@7 {
label = "venom:blue:usb3_2";
reg = <0x7>;
};
wps_blue@8 {
label = "venom:blue:wps";
reg = <0x8>;
};
wps_amber@9 {
label = "venom:amber:wps";
reg = <0x9>;
};
};
&gpio_leds {
power {
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
label = "venom:blue:power";
};
sata {
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
label = "venom:blue:sata";
};
wlan_2g {
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
label = "venom:blue:wlan_2g";
};
wlan_5g {
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
label = "venom:blue:wlan_5g";
};
};
&gpio_leds_pins {
marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56";
};
&nand {
/* Spansion S34ML02G2 256MiB, OEM Layout */
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x200000>; /* 2MB */
read-only;
};
partition@200000 {
label = "u_env";
reg = <0x200000 0x20000>; /* 128KB */
};
partition@220000 {
label = "s_env";
reg = <0x220000 0x40000>; /* 256KB */
};
partition@180000 {
label = "unused_area";
reg = <0x260000 0x5c0000>; /* 5.75MB */
};
partition@7e0000 {
label = "devinfo";
reg = <0x7e0000 0x40000>; /* 256KB */
read-only;
};
/* kernel1 overlaps with rootfs1 by design */
partition@900000 {
label = "kernel1";
reg = <0x900000 0x7b00000>; /* 123MB */
};
partition@f00000 {
label = "rootfs1";
reg = <0xf00000 0x7500000>; /* 117MB */
};
/* kernel2 overlaps with rootfs2 by design */
partition@8400000 {
label = "kernel2";
reg = <0x8400000 0x7b00000>; /* 123MB */
};
partition@8a00000 {
label = "rootfs2";
reg = <0x8a00000 0x7500000>; /* 117MB */
};
/* last MB is for the BBT, not writable */
partition@ff00000 {
label = "BBT";
reg = <0xff00000 0x100000>;
};
};
};
&pcie1 {
mwlwifi {
marvell,chainmask = <4 4>;
};
};
&pcie2 {
mwlwifi {
marvell,chainmask = <4 4>;
};
};
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
no-1-8-v;
non-removable;
wp-inverted;
bus-width = <8>;
status = "okay";
};
&usb3_1_vbus {
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
&usb3_1_vbus_pins {
marvell,pins = "mpp44";
};

322
target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-nas1dual.dts
View File

@ -1,322 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
* Device Tree file for ipTIME NAS1dual
*
* Copyright (C) 2020 Sungbo Eo <mans0n@gorani.run>
*
* Based on armada-385-linksys.dtsi
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "armada-385.dtsi"
/ {
model = "ipTIME NAS1dual";
compatible = "iptime,nas1dual", "marvell,armada385", "marvell,armada380";
aliases {
led-boot = &led_ready;
led-failsafe = &led_ready;
led-running = &led_ready;
led-upgrade = &led_ready;
label-mac-device = &eth0;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pins>;
power {
label = "Power Button";
linux,input-type = <EV_SW>;
linux,code = <KEY_POWER>;
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
};
reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
};
copy {
label = "USB Copy Button";
linux,code = <KEY_COPY>;
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&gpio_leds_pins>;
led_ready: ready {
label = "blue:ready";
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
};
hdd {
label = "blue:hdd";
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
linux,default-trigger = "disk-activity";
};
usb {
function = LED_FUNCTION_USB;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
trigger-sources = <&usb3_0_port1 &usb3_0_port2>;
linux,default-trigger = "usbport";
};
};
gpio-fan {
compatible = "gpio-fan";
pinctrl-names = "default";
pinctrl-0 = <&gpio_fan_pins>;
gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>,
<&gpio1 18 GPIO_ACTIVE_HIGH>;
/* We don't know the exact rpm, just use dummy values here. */
gpio-fan,speed-map = <0 0>, <1 1>, <2 2>;
#cooling-cells = <2>;
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&pca9536 1 GPIO_ACTIVE_LOW>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&sata_power_pins>;
reg_sata_power: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "sata-power";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&gpio1 20 GPIO_ACTIVE_LOW>;
regulator-always-on;
};
};
};
&ahci0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
sata-port@0 {
reg = <0>;
target-supply = <&reg_sata_power>;
#thermal-sensor-cells = <0>;
};
};
&bm {
status = "okay";
};
&bm_bppi {
status = "okay";
};
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&ge0_rgmii_pins>;
status = "okay";
phy-handle = <&ethphy1>;
phy-connection-type = "rgmii-id";
buffer-manager = <&bm>;
bm,pool-long = <0>;
bm,pool-short = <1>;
nvmem-cells = <&macaddr_uboot_fffa8>;
nvmem-cell-names = "mac-address";
};
&eth1 {
pinctrl-names = "default";
pinctrl-0 = <&ge1_rgmii_pins>;
status = "okay";
phy-handle = <&ethphy0>;
phy-connection-type = "rgmii-id";
buffer-manager = <&bm>;
bm,pool-long = <2>;
bm,pool-short = <3>;
nvmem-cells = <&macaddr_uboot_fffa8>;
nvmem-cell-names = "mac-address";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
pca9536: gpio@41 {
compatible = "nxp,pca9536";
reg = <0x41>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "power-led", "power-board";
};
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
/* LED1: On - Link, Blink - Activity, Off - No Link */
ethphy0: ethernet-phy@0 {
reg = <0>;
marvell,reg-init = <3 16 0 0x1017>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
marvell,reg-init = <3 16 0 0x1017>;
};
};
&pinctrl {
gpio_keys_pins: gpio-keys-pins {
marvell,pins = "mpp24", "mpp26", "mpp48";
marvell,function = "gpio";
};
gpio_leds_pins: gpio-leds-pins {
marvell,pins = "mpp18", "mpp20", "mpp51";
marvell,function = "gpio";
};
gpio_fan_pins: gpio-fan-pins {
marvell,pins = "mpp25", "mpp50";
marvell,function = "gpio";
};
sata_power_pins: sata-power-pins {
marvell,pins = "mpp52";
marvell,function = "gpio";
};
uart1_pins_alt: uart-pins-1-alt {
marvell,pins = "mpp45", "mpp46";
marvell,function = "ua1";
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000000 0x00100000>;
label = "u-boot";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_uboot_fffa8: macaddr@fffa8 {
reg = <0xfffa8 0x6>;
};
};
};
partition@100000 {
reg = <0x00100000 0x03ec0000>;
label = "firmware";
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000000 0x00600000>;
label = "kernel";
};
partition@600000 {
reg = <0x00600000 0x038c0000>;
label = "rootfs";
};
};
partition@3fc0000 {
reg = <0x03fc0000 0x00040000>;
label = "config";
read-only;
};
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_alt>;
status = "okay";
};
&usb3_0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
usb3_0_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_0_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};

66
target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts
View File

@ -1,66 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "armada-3720-uDPU.dtsi"
/ {
model = "Methode eDPU Board";
compatible = "methode,edpu", "marvell,armada3720", "marvell,armada3710";
};
/* PHY mode is set to 1000Base-X despite Maxlinear IC being capable of
* 2500Base-X since until 5.15 support for mvebu is available trying to
* use 2500Base-X will cause buffer overruns for which the fix is not
* easily backportable.
*/
&eth0 {
phy-mode = "1000base-x";
};
/*
* External MV88E6361 switch is only available on v2 of the board.
* U-Boot will enable the MDIO bus and switch nodes.
*/
&mdio {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&smi_pins>;
/* Actual device is MV88E6361 */
switch: switch@0 {
compatible = "marvell,mv88e6190";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
phy-mode = "2500base-x";
managed = "in-band-status";
ethernet = <&eth0>;
};
port@9 {
reg = <9>;
label = "downlink";
phy-mode = "2500base-x";
managed = "in-band-status";
};
port@a {
reg = <10>;
label = "uplink";
phy-mode = "2500base-x";
managed = "in-band-status";
sfp = <&sfp_eth1>;
};
};
};
};

240
target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
View File

@ -1,240 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for ESPRESSObin-Ultra
* Copyright (C) 2019 Globalscale technologies, Inc.
*
* Jason Hung <jhung@globalscaletechnologies.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Ultra Board";
compatible = "globalscale,espressobin-ultra", "marvell,armada3720",
"marvell,armada3710";
aliases {
/* for dsa slave device */
ethernet1 = &switch0port1;
ethernet2 = &switch0port2;
ethernet3 = &switch0port3;
ethernet4 = &switch0port4;
ethernet5 = &switch0port5;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
reg_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>;
};
usb3_phy: usb3-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&reg_usb3_vbus>;
};
leds {
pinctrl-names = "default";
compatible = "gpio-leds";
/* No assigned functions to the LEDs by default */
led1 {
label = "ebin-ultra:blue:led1";
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
};
led2 {
label = "ebin-ultra:green:led2";
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
};
led3 {
label = "ebin-ultra:red:led3";
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
};
led4 {
label = "ebin-ultra:yellow:led4";
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
};
};
};
&pcie0 {
status = "okay";
};
&sata {
status = "okay";
};
&sdhci0 {
status = "okay";
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,pad-type = "fixed-1-8v";
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "firmware";
reg = <0x0 0x3e0000>;
};
partition@3e0000 {
label = "hw-info";
reg = <0x3e0000 0x10000>;
read-only;
};
partition@3f0000 {
label = "u-boot-env";
reg = <0x3f0000 0x10000>;
};
};
};
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <100000>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&usb3 {
status = "okay";
usb-phy = <&usb3_phy>;
};
&usb2 {
status = "okay";
};
&eth0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&mdio {
status = "okay";
extphy: ethernet-phy@0 {
reg = <1>;
};
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
switch0port0: port@0 {
reg = <0>;
ethernet = <&eth0>;
};
switch0port1: port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&switch0phy1>;
};
switch0port2: port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy2>;
};
switch0port3: port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&switch0phy3>;
};
switch0port4: port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy4>;
};
switch0port5: port@5 {
reg = <5>;
label = "wan";
phy-handle = <&extphy>;
phy-mode = "sgmii";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1: switch0phy1@11 {
reg = <0x11>;
};
switch0phy2: switch0phy2@12 {
reg = <0x12>;
};
switch0phy3: switch0phy3@13 {
reg = <0x13>;
};
switch0phy4: switch0phy4@14 {
reg = <0x14>;
};
};
};
};

250
target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
View File

@ -1,250 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "armada-372x.dtsi"
/ {
model = "GL.iNet GL-MV1000";
compatible = "glinet,gl-mv1000", "marvell,armada3720";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
vcc_sd_reg1: regulator {
compatible = "regulator-gpio";
regulator-name = "vcc_sd1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
gpios-states = <0>;
states = <1800000 0x1
3300000 0x0>;
enable-active-high;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
};
switch {
label = "switch";
linux,code = <BTN_0>;
gpios = <&gpiosb 22 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
vpn {
label = "green:vpn";
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
};
wan {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
};
led_power: power {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
};
&spi0 {
status = "okay";
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0 0xf0000>;
read-only;
};
partition@f0000 {
label = "u-boot-env";
reg = <0xf0000 0x8000>;
read-only;
};
factory: partition@f8000 {
label = "factory";
reg = <0xf8000 0x8000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_factory_6: macaddr@6 {
reg = <0x6 0x6>;
};
};
};
partition@100000 {
label = "gl-firmware-dtb";
reg = <0x100000 0x10000>;
read-only;
};
partition@110000 {
label = "gl-firmware";
reg = <0x110000 0xef0000>;
read-only;
};
partition@ef0000 {
label = "gl-firmware-jffs2";
reg = <0xef0000 0x110000>;
read-only;
};
};
};
};
&sdhci1 {
wp-inverted;
bus-width = <4>;
cd-gpios = <&gpionb 17 GPIO_ACTIVE_LOW>;
marvell,pad-type = "sd";
no-1-8-v;
vqmmc-supply = <&vcc_sd_reg1>;
status = "okay";
};
&sdhci0 {
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
non-removable;
no-sd;
no-sdio;
marvell,pad-type = "fixed-1-8v";
status = "okay";
};
&usb3 {
status = "okay";
};
&usb2 {
status = "okay";
};
&uart0 {
status = "okay";
};
&mdio {
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
ports: ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ethernet = <&eth0>;
};
port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
nvmem-cells = <&macaddr_factory_6>;
nvmem-cell-names = "mac-address";
};
port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
nvmem-cells = <&macaddr_factory_6>;
nvmem-cell-names = "mac-address";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
};
};
};
&eth0 {
nvmem-cells = <&macaddr_factory_0>;
nvmem-cell-names = "mac-address";
phy-mode = "rgmii-id";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};

46
target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
View File

@ -1,46 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "armada-3720-uDPU.dtsi"
/ {
model = "Methode uDPU Board";
compatible = "methode,udpu", "marvell,armada3720", "marvell,armada3710";
sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&i2c0>;
los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
};
&pinctrl_nb {
i2c1_recovery_pins: i2c1-recovery-pins {
groups = "i2c1";
function = "gpio";
};
};
&i2c0 {
status = "okay";
pinctrl-names = "default", "recovery";
pinctrl-0 = <&i2c1_pins>;
pinctrl-1 = <&i2c1_recovery_pins>;
/delete-property/mrvl,i2c-fast-mode;
scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&eth0 {
phy-mode = "2500base-x";
sfp = <&sfp_eth0>;
};
&eth1 {
phy-mode = "2500base-x";
};

165
target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi
View File

@ -1,165 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device tree for the uDPU board.
* Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
* Copyright (C) 2016 Marvell
* Copyright (C) 2019 Methode Electronics
* Copyright (C) 2019 Telus
*
* Vladimir Vid <vladimir.vid@sartura.hr>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
};
leds {
compatible = "gpio-leds";
led-power1 {
label = "udpu:green:power";
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
};
led-power2 {
label = "udpu:red:power";
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
};
led-network1 {
label = "udpu:green:network";
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
};
led-network2 {
label = "udpu:red:network";
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
};
led-alarm1 {
label = "udpu:green:alarm";
gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
};
led-alarm2 {
label = "udpu:red:alarm";
gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
};
};
sfp_eth1: sfp-eth1 {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
};
&sdhci0 {
status = "okay";
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,pad-type = "fixed-1-8v";
non-removable;
no-sd;
no-sdio;
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <54000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "firmware";
reg = <0x0 0x180000>;
};
partition@180000 {
label = "u-boot-env";
reg = <0x180000 0x10000>;
};
};
};
};
&pinctrl_nb {
i2c2_recovery_pins: i2c2-recovery-pins {
groups = "i2c2";
function = "gpio";
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default", "recovery";
pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&i2c2_recovery_pins>;
/delete-property/mrvl,i2c-fast-mode;
scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
temp-sensor@48 {
compatible = "ti,tmp75c";
reg = <0x48>;
};
temp-sensor@49 {
compatible = "ti,tmp75c";
reg = <0x49>;
};
};
&eth0 {
status = "okay";
managed = "in-band-status";
phys = <&comphy1 0>;
};
&eth1 {
phy-mode = "sgmii";
status = "okay";
managed = "in-band-status";
phys = <&comphy0 1>;
sfp = <&sfp_eth1>;
};
&usb3 {
status = "okay";
phys = <&usb2_utmi_otg_phy>;
phy-names = "usb2-utmi-otg-phy";
};
&uart0 {
status = "okay";
};

448
target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
View File

@ -1,448 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree file for Globalscale MOCHAbin
* Copyright (C) 2019 Globalscale technologies, Inc.
* Copyright (C) 2021 Sartura Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-7040.dtsi"
/ {
model = "Globalscale MOCHAbin";
compatible = "globalscale,mochabin", "marvell,armada7040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
ethernet3 = &swport1;
ethernet4 = &swport2;
ethernet5 = &swport3;
ethernet6 = &swport4;
};
/* SFP+ 10G */
sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
};
/* SFP 1G */
sfp_eth2: sfp-eth2 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c0>;
los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
};
};
/* microUSB UART console */
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
/* eMMC */
&ap_sdhci0 {
status = "okay";
bus-width = <4>;
non-removable;
/delete-property/ marvell,xenon-phy-slow-mode;
no-1-8-v;
};
&cp0_pinctrl {
cp0_uart0_pins: cp0-uart0-pins {
marvell,pins = "mpp6", "mpp7";
marvell,function = "uart0";
};
cp0_spi0_pins: cp0-spi0-pins {
marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
marvell,function = "spi0";
};
cp0_spi1_pins: cp0-spi1-pins {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp0_i2c0_pins: cp0-i2c0-pins {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c1-pins {
marvell,pins = "mpp2", "mpp3";
marvell,function = "i2c1";
};
pca9554_int_pins: pca9554-int-pins {
marvell,pins = "mpp27";
marvell,function = "gpio";
};
cp0_rgmii1_pins: cp0-rgmii1-pins {
marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
is31_sdb_pins: is31-sdb-pins {
marvell,pins = "mpp30";
marvell,function = "gpio";
};
cp0_pcie_reset_pins: cp0-pcie-reset-pins {
marvell,pins = "mpp9";
marvell,function = "gpio";
};
cp0_switch_pins: cp0-switch-pins {
marvell,pins = "mpp0", "mpp1";
marvell,function = "gpio";
};
cp0_phy_pins: cp0-phy-pins {
marvell,pins = "mpp12";
marvell,function = "gpio";
};
};
/* mikroBUS UART */
&cp0_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_uart0_pins>;
};
/* mikroBUS SPI */
&cp0_spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
};
/* SPI-NOR */
&cp0_spi1{
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi1_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x3e0000>;
read-only;
};
partition@3e0000 {
label = "hw-info";
reg = <0x3e0000 0x10000>;
read-only;
};
partition@3f0000 {
label = "u-boot-env";
reg = <0x3f0000 0x10000>;
};
};
};
};
/* mikroBUS, 1G SFP and GPIO expander */
&cp0_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
clock-frequency = <100000>;
sfp_gpio: pca9554@39 {
compatible = "nxp,pca9554";
pinctrl-names = "default";
pinctrl-0 = <&pca9554_int_pins>;
reg = <0x39>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
/*
* IO0_0: SFP+_TX_FAULT
* IO0_1: SFP+_TX_DISABLE
* IO0_2: SFP+_PRSNT
* IO0_3: SFP+_LOSS
* IO0_4: SFP_TX_FAULT
* IO0_5: SFP_TX_DISABLE
* IO0_6: SFP_PRSNT
* IO0_7: SFP_LOSS
*/
};
};
/* IS31FL3199, mini-PCIe and 10G SFP+ */
&cp0_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c1_pins>;
clock-frequency = <100000>;
leds@64 {
compatible = "issi,is31fl3199";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&is31_sdb_pins>;
shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
reg = <0x64>;
led1_red: led@1 {
label = "red:led1";
reg = <1>;
led-max-microamp = <20000>;
};
led1_green: led@2 {
label = "green:led1";
reg = <2>;
};
led1_blue: led@3 {
label = "blue:led1";
reg = <3>;
};
led2_red: led@4 {
label = "red:led2";
reg = <4>;
};
led2_green: led@5 {
label = "green:led2";
reg = <5>;
};
led2_blue: led@6 {
label = "blue:led2";
reg = <6>;
};
led3_red: led@7 {
label = "red:led3";
reg = <7>;
};
led3_green: led@8 {
label = "green:led3";
reg = <8>;
};
led3_blue: led@9 {
label = "blue:led3";
reg = <9>;
};
};
};
&cp0_mdio {
status = "okay";
/* 88E1512 PHY */
eth2phy: ethernet-phy@1 {
reg = <1>;
sfp = <&sfp_eth2>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_phy_pins>;
reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
};
/* 88E6141 Topaz switch */
switch: switch@3 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_switch_pins>;
reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
swport1: port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&swphy1>;
};
swport2: port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&swphy2>;
};
swport3: port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&swphy3>;
};
swport4: port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&swphy4>;
};
port@5 {
reg = <5>;
ethernet = <&cp0_eth1>;
phy-mode = "2500base-x";
managed = "in-band-status";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
swphy1: swphy1@17 {
reg = <17>;
};
swphy2: swphy2@18 {
reg = <18>;
};
swphy3: swphy3@19 {
reg = <19>;
};
swphy4: swphy4@20 {
reg = <20>;
};
};
};
};
&cp0_ethernet {
status = "okay";
};
/* 10G SFP+ */
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-r";
phys = <&cp0_comphy4 0>;
managed = "in-band-status";
sfp = <&sfp_eth0>;
};
/* Topaz switch uplink */
&cp0_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy0 1>;
fixed-link {
speed = <2500>;
full-duplex;
};
};
/* 1G SFP or 1G RJ45 */
&cp0_eth2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_rgmii1_pins>;
phy = <&eth2phy>;
phy-mode = "rgmii-id";
};
/* SMSC USB5434B hub */
&cp0_usb3_0 {
status = "okay";
phys = <&cp0_comphy1 0>;
phy-names = "cp0-usb3h0-comphy";
};
/* miniPCI-E USB */
&cp0_usb3_1 {
status = "okay";
};
&cp0_sata0 {
status = "okay";
/* 7 + 12 SATA connector (J24) */
sata-port@0 {
phys = <&cp0_comphy2 0>;
phy-names = "cp0-sata0-0-phy";
};
/* M.2-2250 B-key (J39) */
sata-port@1 {
phys = <&cp0_comphy3 1>;
phy-names = "cp0-sata0-1-phy";
};
};
/* miniPCI-E (J5) */
&cp0_pcie2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_pcie_reset_pins>;
phys = <&cp0_comphy5 2>;
phy-names = "cp0-pcie2-x1-phy";
reset-gpio = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000>;
};

513
target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9130-clearfog-pro.dts
View File

@ -1,513 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright SolidRun Ltd.
* Copyright (C) 2024 Tobias Schramm <tobias@t-sys.eu>
*
* Device tree for the CN9130-based ClearFog Pro
*/
#include "cn9130.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "SolidRun ClearFog Pro";
compatible = "solidrun,clearfog-pro", "marvell,armada-ap807-quad",
"marvell,armada-ap807";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
i2c0 = &cp0_i2c0;
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
spi1 = &cp0_spi1;
};
memory@00000000 {
reg = <0x0 0x0 0x1 0x0>;
device_type = "memory";
};
/* Virtual regulator, root of power tree */
vin: regulator-vin {
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-always-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
/* Regulators supplied by vin */
v_5v0: regulator-v_5v0 {
compatible = "regulator-fixed";
regulator-name = "v_5v0";
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vin>;
};
v_3v3: regulator-v_3v3 {
compatible = "regulator-fixed";
regulator-name = "v_3v3";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vin>;
};
/* Regulators supplied by v_5v0 */
v_1v8: regulator-v_1v8 {
compatible = "regulator-fixed";
regulator-name = "v_1v8";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&v_5v0>;
};
v_5v0_usb3_hst_vbus: regulator-v_5v0_usb3_hst_vbus {
compatible = "regulator-fixed";
regulator-name = "v_5v0_usb3_hst_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&expander0 6 GPIO_ACTIVE_LOW>;
vin-supply = <&v_5v0>;
};
/* Regulators internal to SOM */
vqmmc: regulator-vqmmc {
compatible = "regulator-fixed";
regulator-name = "vqmmc";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&v_5v0>;
};
cp0_usb3_0_phy1: cp0_usb3_phy@1 {
compatible = "usb-nop-xceiv";
vbus-supply = <&v_5v0_usb3_hst_vbus>;
};
cp0_sfp_eth0: sfp-eth@0 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <2000>;
};
keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&cp0_button_pin>;
reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
};
};
};
&uart0 {
status = "okay";
};
/* on-board eMMC */
&ap_sdhci0 {
bus-width = <8>;
pinctrl-names = "default";
vqmmc-supply = <&vqmmc>;
status = "okay";
};
&cp0_crypto {
status = "okay";
};
&cp0_ethernet {
status = "okay";
};
&cp0_gpio1 {
status = "okay";
};
&cp0_gpio2 {
status = "okay";
};
&cp0_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
clock-frequency = <100000>;
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-CON3 CLKREQ#
* 1-CON3 PERST#
* 2-CON2 PERST#
* 3-CON3 W_DISABLE
* 4-CON2 CLKREQ#
* 5-USB3 overcurrent
* 6-USB3 power
* 7-CON2 W_DISABLE
* 8-JP4 P1
* 9-JP4 P4
* 10-JP4 P5
* 11-m.2 DEVSLP
* 12-SFP_LOS
* 13-SFP_TX_FAULT
* 14-SFP_TX_DISABLE
* 15-SFP_MOD_DEF0
*/
expander0: gpio-expander@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_expander0_pins>;
vcc-supply = <&v_3v3>;
pcie1_0_clkreq {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie1.0-clkreq";
};
pcie1_0_w_disable {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie1.0-w-disable";
};
pcie2_0_clkreq {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie2.0-clkreq";
};
pcie2_0_w_disable {
gpio-hog;
gpios = <7 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie2.0-w-disable";
};
usb3_ilimit {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
input;
line-name = "usb3-current-limit";
};
m2_devslp {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "m.2 devslp";
};
};
/* ADC only for mikroBUS connector */
mcp3021@4c {
compatible = "microchip,mcp3021";
reg = <0x4c>;
};
/* EEPROM on the SOM */
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
read-only;
nvmem-layout {
compatible = "onie,tlv-layout";
onie_tlv_macaddr: mac-address {
#nvmem-cell-cells = <1>;
};
};
};
};
/* SMBUS on mini PCIe sockets */
&cp0_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c1_pins>;
clock-frequency = <100000>;
};
&cp0_mdio {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
/* Green led blinks on activity, orange LED on link */
marvell,reg-init = <3 16 0 0x0064>;
};
switch@4 {
compatible = "marvell,mv88e6085";
reg = <4>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_dsa0_pins>;
reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>;
mdio-external {
compatible = "marvell,mv88e6xxx-mdio-external";
#address-cells = <1>;
#size-cells = <0>;
/* 88E1512 PHY */
port6_phy: ethernet-phy@1 {
reg = <1>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan5";
};
port@1 {
reg = <1>;
label = "lan4";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan1";
};
port@5 {
reg = <5>;
ethernet = <&cp0_eth1>;
label = "cpu";
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@6 {
/* 88E1512 external phy */
reg = <6>;
label = "lan6";
phy-handle = <&port6_phy>;
phy-mode = "rgmii-id";
};
};
};
};
/* SRDS #0 - SATA on bottom M.2 B-Key connector */
&cp0_sata0 {
status = "okay";
sata-port@0 {
status = "disabled";
};
sata-port@1 {
phys = <&cp0_comphy0 1>;
target-supply = <&v_3v3>;
};
};
&cp0_utmi {
status = "okay";
};
/* mini PCIe slot far from SOM, USB 2.0 only, SS lanes unused */
&cp0_usb3_0 {
status = "okay";
phys = <&cp0_utmi0>;
phy-names = "utmi";
dr_mode = "host";
};
/* SRDS #1 - USB-A 3.0 host port */
&cp0_usb3_1 {
status = "okay";
phys = <&cp0_utmi1>, <&cp0_comphy1 0>;
phy-names = "utmi", "usb";
usb-phy = <&cp0_usb3_0_phy1>;
dr_mode = "host";
};
/* SRDS #2 - SFP+ 10GE */
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-r";
phys = <&cp0_comphy2 0>;
managed = "in-band-status";
nvmem-cells = <&onie_tlv_macaddr 0>;
nvmem-cell-names = "mac-address";
sfp = <&cp0_sfp_eth0>;
};
/* SRDS #3 - SGMII 1GE to L2 switch */
&cp0_eth1 {
status = "okay";
phys = <&cp0_comphy3 1>;
phy-mode = "sgmii";
nvmem-cells = <&onie_tlv_macaddr 1>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
/* SRDS #4 - mini PCIe slot near SOM */
&cp0_pcie1 {
status = "okay";
phys = <&cp0_comphy4 1>;
num-lanes = <1>;
reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
};
/* SRDS #5 - mini PCIe slot far from SOM */
&cp0_pcie2 {
status = "okay";
phys = <&cp0_comphy5 2>;
num-lanes = <1>;
reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
};
/* GE PHY RGMII */
&cp0_eth2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_ge2_rgmii_pins>;
phy = <&phy0>;
phy-mode = "rgmii-id";
nvmem-cells = <&onie_tlv_macaddr 2>;
nvmem-cell-names = "mac-address";
};
/* micro SD card slot */
&cp0_sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_sdhci_pins &cp0_sdhci_cd_pins>;
bus-width = <4>;
cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
no-1-8-v;
vqmmc-supply = <&v_3v3>;
vmmc-supply = <&v_3v3>;
};
&cp0_spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi1_pins>;
spi-flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
#address-cells = <0x1>;
#size-cells = <0x1>;
spi-max-frequency = <10000000>;
};
};
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp0_i2c0_pins: cp0-i2c0-pins {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c1-pins {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_ge2_rgmii_pins: cp0-ge2-rgmii-pins {
marvell,pins = "mpp44", "mpp45", "mpp46",
"mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52",
"mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
cp0_sdhci_cd_pins: cp0-sdhci-cd-pins {
marvell,pins = "mpp43";
marvell,function = "sdio";
};
cp0_sdhci_pins: cp0-sdhci-pins {
marvell,pins = "mpp56", "mpp57", "mpp58",
"mpp59", "mpp60", "mpp61";
marvell,function = "sdio";
};
cp0_spi1_pins: cp0-spi1-pins {
marvell,pins = "mpp12", "mpp13", "mpp14",
"mpp15", "mpp16";
marvell,function = "spi1";
};
cp0_dsa0_pins: cp0-dsa0-pins {
marvell,pins = "mpp27", "mpp29";
marvell,function = "gpio";
};
cp0_button_pin: cp0-button-pin {
marvell,pins = "mpp32";
marvell,function = "gpio";
};
cp0_expander0_pins: cp0-expander0-pins {
marvell,pins = "mpp4";
marvell,function = "gpio";
};
};
};

410
target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
View File

@ -1,410 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* Device tree for the CN9131-DB board.
*/
#include "cn9130.dtsi"
#include "puzzle-thermal.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "iEi Puzzle-M901";
compatible = "iei,puzzle-m901",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
i2c0 = &cp1_i2c0;
i2c1 = &cp0_i2c0;
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
ethernet3 = &cp1_eth0;
ethernet4 = &cp1_eth1;
ethernet5 = &cp1_eth2;
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
gpio3 = &cp1_gpio1;
gpio4 = &cp1_gpio2;
led-boot = &led_power;
led-failsafe = &led_info;
led-running = &led_power;
led-upgrade = &led_info;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
gpio_keys {
compatible = "gpio-keys";
reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
};
};
};
&uart0 {
status = "okay";
};
&cp0_uart0 {
status = "okay";
puzzle-mcu {
compatible = "iei,wt61p803-puzzle";
#address-cells = <1>;
#size-cells = <1>;
current-speed = <115200>;
enable-beep;
status = "okay";
leds {
compatible = "iei,wt61p803-puzzle-leds";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
led@0 {
reg = <0>;
label = "white:network";
active-low;
};
led@1 {
reg = <1>;
label = "green:cloud";
active-low;
};
led_info: led@2 {
reg = <2>;
label = "orange:info";
active-low;
};
led_power: led@3 {
reg = <3>;
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_YELLOW>;
active-low;
default-state = "on";
};
};
hwmon {
compatible = "iei,wt61p803-puzzle-hwmon";
#address-cells = <1>;
#size-cells = <0>;
chassis_fan_group0: fan-group@0 {
#cooling-cells = <2>;
reg = <0x00>;
cooling-levels = <0 159 195 211 223 241 255>;
};
};
};
};
&ap_thermal_ic {
PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
};
&cp0_thermal_ic {
PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
};
/* on-board eMMC - U9 */
&ap_sdhci0 {
pinctrl-names = "default";
bus-width = <8>;
status = "okay";
mmc-ddr-1_8v;
mmc-hs400-1_8v;
};
&cp0_crypto {
status = "okay";
};
&cp0_xmdio {
status = "okay";
cp0_nbaset_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp0_nbaset_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp0_nbaset_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp0_ethernet {
status = "okay";
};
/* SLM-1521-V2, CON9 */
&cp0_eth0 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy2 0>;
phy = <&cp0_nbaset_phy0>;
};
&cp0_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy4 1>;
phy = <&cp0_nbaset_phy1>;
};
&cp0_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy5 2>;
phy = <&cp0_nbaset_phy2>;
};
&cp0_gpio1 {
status = "okay";
};
&cp0_gpio2 {
status = "okay";
};
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
rtc@32 {
compatible = "epson,rx8130";
reg = <0x32>;
wakeup-source;
};
};
/* SLM-1521-V2, CON6 */
&cp0_pcie0 {
status = "okay";
num-lanes = <2>;
num-viewport = <8>;
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
};
/* U55 */
&cp0_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>; /* CS0 */
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x1f0000>;
};
partition@1f0000 {
label = "U-Boot ENV Factory";
reg = <0x1f0000 0x10000>;
};
partition@200000 {
label = "Reserved";
reg = <0x200000 0x1f0000>;
};
partition@3f0000 {
label = "U-Boot ENV";
reg = <0x3f0000 0x10000>;
};
};
};
};
&cp0_rtc {
status = "disabled";
};
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp0_i2c0_pins: cp0-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c-pins-1 {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3", "mpp4", "mpp5",
"mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11";
marvell,function = "ge0";
};
cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
marvell,pins = "mpp44", "mpp45", "mpp46",
"mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52",
"mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
cp0_spi0_pins: cp0-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
};
};
/*
* Instantiate the first connected CP115
*/
#define CP11X_NAME cp1
#define CP11X_BASE f6000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f6600000
#define CP11X_PCIE1_BASE f6620000
#define CP11X_PCIE2_BASE f6640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp1_crypto {
status = "okay";
};
&cp1_xmdio {
status = "okay";
cp1_nbaset_phy0: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp1_nbaset_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp1_nbaset_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp1_ethernet {
status = "okay";
};
/* CON50 */
&cp1_eth0 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy2 0>;
phy = <&cp1_nbaset_phy0>;
};
&cp1_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy4 1>;
phy = <&cp1_nbaset_phy1>;
};
&cp1_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy5 2>;
phy = <&cp1_nbaset_phy2>;
};
&cp1_sata0 {
status = "okay";
sata-port@1 {
status = "okay";
phys = <&cp1_comphy0 1>;
};
};
&cp1_gpio1 {
status = "okay";
};
&cp1_gpio2 {
status = "okay";
};
&cp1_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_i2c0_pins>;
clock-frequency = <100000>;
};
&cp1_rtc {
status = "disabled";
};
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp1_i2c0_pins: cp1-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp1_spi0_pins: cp1-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
marvell,pins = "mpp3";
marvell,function = "gpio";
};
cp1_sfp_pins: sfp-pins {
marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
marvell,function = "gpio";
};
};
};
&cp1_thermal_ic {
PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
};
&cp1_usb3_1 {
status = "okay";
phys = <&cp1_comphy3 1>;
phy-names = "usb";
};

580
target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
View File

@ -1,580 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2019 Marvell International Ltd.
*
* Device tree for the CN9132-DB board.
*/
#include "cn9130.dtsi"
#include "puzzle-thermal.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "iEi Puzzle-M902";
compatible = "iei,puzzle-m902",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
i2c0 = &cp1_i2c0;
i2c1 = &cp0_i2c0;
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
gpio3 = &cp1_gpio1;
gpio4 = &cp1_gpio2;
gpio5 = &cp2_gpio1;
gpio6 = &cp2_gpio2;
ethernet0 = &cp0_eth0;
ethernet1 = &cp0_eth1;
ethernet2 = &cp0_eth2;
ethernet3 = &cp1_eth0;
ethernet4 = &cp1_eth1;
ethernet5 = &cp1_eth2;
ethernet6 = &cp2_eth0;
ethernet7 = &cp2_eth1;
ethernet8 = &cp2_eth2;
spi1 = &cp0_spi0;
spi2 = &cp0_spi1;
led-boot = &led_power;
led-failsafe = &led_info;
led-running = &led_power;
led-upgrade = &led_info;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
gpio_keys {
compatible = "gpio-keys";
reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
};
};
cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
compatible = "regulator-fixed";
regulator-name = "cp2-xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
};
cp2_usb3_0_phy0: cp2_usb3_phy0 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp2_reg_usb3_vbus0>;
};
cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
compatible = "regulator-fixed";
regulator-name = "cp2-xhci1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
};
cp2_usb3_0_phy1: cp2_usb3_phy1 {
compatible = "usb-nop-xceiv";
vcc-supply = <&cp2_reg_usb3_vbus1>;
};
cp2_sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp2_sfpp0_i2c>;
los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
};
&uart0 {
status = "okay";
};
&cp0_uart0 {
status = "okay";
puzzle-mcu {
compatible = "iei,wt61p803-puzzle";
#address-cells = <1>;
#size-cells = <1>;
current-speed = <115200>;
enable-beep;
status = "okay";
leds {
compatible = "iei,wt61p803-puzzle-leds";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
led@0 {
reg = <0>;
label = "white:network";
active-low;
};
led@1 {
reg = <1>;
label = "green:cloud";
active-low;
};
led_info: led@2 {
reg = <2>;
label = "orange:info";
active-low;
};
led_power: led@3 {
reg = <3>;
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_YELLOW>;
active-low;
default-state = "on";
};
};
hwmon {
compatible = "iei,wt61p803-puzzle-hwmon";
#address-cells = <1>;
#size-cells = <0>;
chassis_fan_group0: fan-group@0 {
#cooling-cells = <2>;
reg = <0x00>;
cooling-levels = <0 159 195 211 223 241 255>;
};
};
};
};
&ap_thermal_ic {
PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
};
&cp0_thermal_ic {
PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
};
/* on-board eMMC - U9 */
&ap_sdhci0 {
pinctrl-names = "default";
bus-width = <8>;
status = "okay";
mmc-ddr-1_8v;
mmc-hs400-1_8v;
};
&cp0_crypto {
status = "okay";
};
&cp0_xmdio {
status = "okay";
cp0_nbaset_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp0_nbaset_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp0_nbaset_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp0_ethernet {
status = "okay";
};
/* SLM-1521-V2, CON9 */
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phys = <&cp0_comphy2 0>;
phy = <&cp0_nbaset_phy0>;
};
&cp0_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy4 1>;
phy = <&cp0_nbaset_phy1>;
};
&cp0_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp0_comphy1 2>;
phy = <&cp0_nbaset_phy2>;
};
&cp0_gpio1 {
status = "okay";
};
&cp0_gpio2 {
status = "okay";
};
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
rtc@32 {
compatible = "epson,rx8130";
reg = <0x32>;
wakeup-source;
};
};
&cp0_i2c1 {
clock-frequency = <100000>;
};
/* SLM-1521-V2, CON6 */
&cp0_sata0 {
status = "okay";
sata-port@1 {
status = "okay";
phys = <&cp0_comphy0 1>;
};
};
&cp0_pcie2 {
status = "okay";
num-lanes = <1>;
num-viewport = <8>;
phys = <&cp0_comphy5 2>;
};
/* U55 */
&cp0_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>; /* CS0 */
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x1f0000>;
};
partition@1f0000 {
label = "U-Boot ENV Factory";
reg = <0x1f0000 0x10000>;
};
partition@200000 {
label = "Reserved";
reg = <0x200000 0x1f0000>;
};
partition@3f0000 {
label = "U-Boot ENV";
reg = <0x3f0000 0x10000>;
};
};
};
};
&cp0_rtc {
status = "disabled";
};
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp0_i2c0_pins: cp0-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_i2c1_pins: cp0-i2c-pins-1 {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3", "mpp4", "mpp5",
"mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11";
marvell,function = "ge0";
};
cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
marvell,pins = "mpp44", "mpp45", "mpp46",
"mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52",
"mpp53", "mpp54", "mpp55";
marvell,function = "ge1";
};
cp0_spi0_pins: cp0-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
};
};
&cp0_usb3_1 {
status = "okay";
phys = <&cp0_comphy3 1>;
phy-names = "usb";
};
/*
* Instantiate the first connected CP115
*/
#define CP11X_NAME cp1
#define CP11X_BASE f4000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f4600000
#define CP11X_PCIE1_BASE f4620000
#define CP11X_PCIE2_BASE f4640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp1_crypto {
status = "okay";
};
&cp1_xmdio {
status = "okay";
cp1_nbaset_phy0: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp1_nbaset_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp1_nbaset_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&cp1_ethernet {
status = "okay";
};
/* CON50 */
&cp1_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phys = <&cp1_comphy2 0>;
phy = <&cp1_nbaset_phy0>;
};
&cp1_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy4 1>;
phy = <&cp1_nbaset_phy1>;
};
&cp1_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy1 2>;
phy = <&cp1_nbaset_phy2>;
};
&cp1_gpio1 {
status = "okay";
};
&cp1_gpio2 {
status = "okay";
};
&cp1_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp1_i2c0_pins>;
clock-frequency = <100000>;
};
&cp1_rtc {
status = "disabled";
};
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp1_i2c0_pins: cp1-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp1_spi0_pins: cp1-spi-pins-0 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
marvell,pins = "mpp3";
marvell,function = "gpio";
};
};
};
&cp1_thermal_ic {
PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
};
/*
* Instantiate the second connected CP115
*/
#define CP11X_NAME cp2
#define CP11X_BASE f6000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f6600000
#define CP11X_PCIE1_BASE f6620000
#define CP11X_PCIE2_BASE f6640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
&cp2_crypto {
status = "okay";
};
&cp2_ethernet {
status = "okay";
};
&cp2_xmdio {
status = "okay";
cp2_nbaset_phy0: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
};
cp2_nbaset_phy1: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cp2_nbaset_phy2: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
/* SLM-1521-V2, CON9 */
&cp2_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phys = <&cp2_comphy2 0>;
phy = <&cp2_nbaset_phy0>;
};
&cp2_eth1 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp2_comphy4 1>;
phy = <&cp2_nbaset_phy1>;
};
&cp2_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp2_comphy1 2>;
phy = <&cp2_nbaset_phy2>;
};
&cp2_gpio1 {
status = "okay";
};
&cp2_gpio2 {
status = "okay";
};
&cp2_i2c0 {
clock-frequency = <100000>;
/* SLM-1521-V2 - U3 */
i2c-mux@72 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72>;
cp2_sfpp0_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/* U12 */
cp2_module_expander1: pca9555@21 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
reg = <0x21>;
};
};
};
};
&cp2_rtc {
status = "disabled";
};
&cp2_syscon0 {
cp2_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
cp2_i2c0_pins: cp2-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
};
};
&cp2_thermal_ic {
PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0);
};

68
target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/puzzle-thermal.dtsi
View File

@ -1,68 +0,0 @@
#define PUZZLE_FAN_THERMAL(_cname, _fan) \
polling-delay-passive = <500>; \
polling-delay = <1000>; \
\
trips { \
cpu-hot { \
temperature = <75000>; \
hysteresis = <5000>; \
type = "hot"; \
}; \
_cname##_active_full: cpu-active-full { \
temperature = <70000>; \
hysteresis = <5000>; \
type = "active"; \
}; \
_cname##_active_high: cpu-active-high { \
temperature = <65000>; \
hysteresis = <5000>; \
type = "active"; \
}; \
_cname##_active_med: cpu-active-med { \
temperature = <62500>; \
hysteresis = <3000>; \
type = "active"; \
}; \
_cname##_active_low: cpu-active-low { \
temperature = <60000>; \
hysteresis = <3000>; \
type = "active"; \
}; \
_cname##_active_min: cpu-active-min { \
temperature = <55000>; \
hysteresis = <5000>; \
type = "active"; \
}; \
_cname##_active_idle: cpu-active-idle { \
temperature = <50000>; \
hysteresis = <5000>; \
type = "active"; \
}; \
}; \
cooling-maps { \
cpu-active-full { \
trip = <&_cname##_active_full>; \
cooling-device = <_fan THERMAL_NO_LIMIT \
THERMAL_NO_LIMIT>; \
}; \
cpu-active-high { \
trip = <&_cname##_active_high>; \
cooling-device = <_fan 4 5>; \
}; \
cpu-active-med { \
trip = <&_cname##_active_med>; \
cooling-device = <_fan 3 4>; \
}; \
cpu-active-low { \
trip = <&_cname##_active_low>; \
cooling-device = <_fan 2 3>; \
}; \
cpu-active-min { \
trip = <&_cname##_active_min>; \
cooling-device = <_fan 1 2>; \
}; \
cpu-active-idle { \
trip = <&_cname##_active_idle>; \
cooling-device = <_fan 0 0>; \
}; \
}

2
target/linux/mvebu/image/cortexa9.mk
View File

@ -3,9 +3,7 @@
# Copyright (C) 2012-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-project.org
ifneq ($(KERNEL),6.1)
DTS_DIR := $(DTS_DIR)/marvell
endif
define Build/fortigate-header
( \

59
target/linux/mvebu/patches-6.1/000-cpufreq-armada-8k-add-ap807-support.patch
View File

@ -1,59 +0,0 @@
From 8eec6e740b564ec5e1da59ab7070b89aa23c9973 Mon Sep 17 00:00:00 2001
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
Date: Fri, 16 Jun 2023 12:41:30 +0100
Subject: [PATCH] cpufreq: armada-8k: add ap807 support
Add support for the Armada AP807 die to armada-8k. This uses a
different compatible for the CPU clock which needs to be added to
the cpufreq driver.
This commit takes a different approach to the WindRiver patch
"cpufreq: armada: enable ap807-cpu-clk" in that rather than calling
of_find_compatible_node() for each compatible, we use a table of
IDs instead.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/cpufreq/armada-8k-cpufreq.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
--- a/drivers/cpufreq/armada-8k-cpufreq.c
+++ b/drivers/cpufreq/armada-8k-cpufreq.c
@@ -21,6 +21,13 @@
#include <linux/pm_opp.h>
#include <linux/slab.h>
+static const struct of_device_id __maybe_unused armada_8k_cpufreq_of_match[] = {
+ { .compatible = "marvell,ap806-cpu-clock" },
+ { .compatible = "marvell,ap807-cpu-clock" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, armada_8k_cpufreq_of_match);
+
/*
* Setup the opps list with the divider for the max frequency, that
* will be filled at runtime.
@@ -127,7 +134,8 @@ static int __init armada_8k_cpufreq_init
struct device_node *node;
struct cpumask cpus;
- node = of_find_compatible_node(NULL, NULL, "marvell,ap806-cpu-clock");
+ node = of_find_matching_node_and_match(NULL, armada_8k_cpufreq_of_match,
+ NULL);
if (!node || !of_device_is_available(node)) {
of_node_put(node);
return -ENODEV;
@@ -204,12 +212,6 @@ static void __exit armada_8k_cpufreq_exi
}
module_exit(armada_8k_cpufreq_exit);
-static const struct of_device_id __maybe_unused armada_8k_cpufreq_of_match[] = {
- { .compatible = "marvell,ap806-cpu-clock" },
- { },
-};
-MODULE_DEVICE_TABLE(of, armada_8k_cpufreq_of_match);
-
MODULE_AUTHOR("Gregory Clement <gregory.clement@bootlin.com>");
MODULE_DESCRIPTION("Armada 8K cpufreq driver");
MODULE_LICENSE("GPL");

81
target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch
View File

@ -1,81 +0,0 @@
Subject: [PATCH v2] PCI: aardvark: Implement workaround for PCIe Completion Timeout
Date: Tue, 2 Aug 2022 14:38:16 +0200
Message-Id: <20220802123816.21817-1-pali@kernel.org>
X-Mailer: git-send-email 2.20.1
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Precedence: bulk
List-ID: <linux-pci.vger.kernel.org>
X-Mailing-List: linux-pci@vger.kernel.org
Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions
document describes in erratum 3.12 PCIe Completion Timeout (Ref #: 251),
that PCIe IP does not support a strong-ordered model for inbound posted vs.
outbound completion.
As a workaround for this erratum, DIS_ORD_CHK flag in Debug Mux Control
register must be set. It disables the ordering check in the core between
Completions and Posted requests received from the link.
Marvell also suggests to do full memory barrier at the beginning of
aardvark summary interrupt handler before calling interrupt handlers of
endpoint drivers in order to minimize the risk for the race condition
documented in the Erratum between the DMA done status reading and the
completion of writing to the host memory.
More details about this issue and suggested workarounds are in discussion:
https://lore.kernel.org/linux-pci/BN9PR18MB425154FE5019DCAF2028A1D5DB8D9@BN9PR18MB4251.namprd18.prod.outlook.com/t/#u
It was reported that enabling this workaround fixes instability issues and
"Unhandled fault" errors when using 60 GHz WiFi 802.11ad card with Qualcomm
QCA6335 chip under significant load which were caused by interrupt status
stuck in the outbound CMPLT queue traced back to this erratum.
This workaround fixes also kernel panic triggered after some minutes of
usage 5 GHz WiFi 802.11ax card with Mediatek MT7915 chip:
Internal error: synchronous external abort: 96000210 [#1] SMP
Kernel panic - not syncing: Fatal exception in interrupt
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc: stable@vger.kernel.org
---
drivers/pci/controller/pci-aardvark.c | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -212,6 +212,8 @@ enum {
};
#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
+#define DEBUG_MUX_CTRL_REG (LMI_BASE_ADDR + 0x208)
+#define DIS_ORD_CHK BIT(30)
/* PCIe core controller registers */
#define CTRL_CORE_BASE_ADDR 0x18000
@@ -560,6 +562,11 @@ static void advk_pcie_setup_hw(struct ad
PCIE_CORE_CTRL2_TD_ENABLE;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+ /* Disable ordering checks, workaround for erratum 3.12 "PCIe completion timeout" */
+ reg = advk_readl(pcie, DEBUG_MUX_CTRL_REG);
+ reg |= DIS_ORD_CHK;
+ advk_writel(pcie, reg, DEBUG_MUX_CTRL_REG);
+
/* Set lane X1 */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg &= ~LANE_CNT_MSK;
@@ -1661,6 +1668,9 @@ static irqreturn_t advk_pcie_irq_handler
struct advk_pcie *pcie = arg;
u32 status;
+ /* Full memory barrier (ARM dsb sy), workaround for erratum 3.12 "PCIe completion timeout" */
+ mb();
+
status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
if (!(status & PCIE_IRQ_CORE_INT))
return IRQ_NONE;

15
target/linux/mvebu/patches-6.1/105-power-reset-linkstation-poweroff-add-ls220de.patch
View File

@ -1,15 +0,0 @@
--- a/drivers/power/reset/linkstation-poweroff.c
+++ b/drivers/power/reset/linkstation-poweroff.c
@@ -142,6 +142,12 @@ static void linkstation_poweroff(void)
}
static const struct of_device_id ls_poweroff_of_match[] = {
+ { .compatible = "buffalo,ls220d",
+ .data = &linkstation_power_off_cfg,
+ },
+ { .compatible = "buffalo,ls220de",
+ .data = &linkstation_power_off_cfg,
+ },
{ .compatible = "buffalo,ls421d",
.data = &linkstation_power_off_cfg,
},

279
target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
View File

@ -1,279 +0,0 @@
From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
From: Adrian Panella <ianchi74@outlook.com>
Date: Thu, 9 Mar 2017 09:37:17 +0100
Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
The command-line arguments provided by the boot loader will be
appended to a new device tree property: bootloader-args.
If there is a property "append-rootblock" in DT under /chosen
and a root= option in bootloaders command line it will be parsed
and added to DT bootargs with the form: <append-rootblock>XX.
Only command line ATAG will be processed, the rest of the ATAGs
sent by bootloader will be ignored.
This is usefull in dual boot systems, to get the current root partition
without afecting the rest of the system.
Signed-off-by: Adrian Panella <ianchi74@outlook.com>
This patch has been modified to be mvebu specific. The original patch
did not pass the bootloader cmdline on if no append-rootblock stanza
was found, resulting in blank cmdline and failure to boot.
Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
---
arch/arm/Kconfig | 11 ++++
arch/arm/boot/compressed/atags_to_fdt.c | 85 ++++++++++++++++++++++++-
init/main.c | 16 +++++
3 files changed, 111 insertions(+), 1 deletion(-)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1587,6 +1587,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
The command-line arguments provided by the boot loader will be
appended to the the device tree bootargs property.
+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
+ bool "Append rootblock parsing bootloader's kernel arguments"
+ help
+ The command-line arguments provided by the boot loader will be
+ appended to a new device tree property: bootloader-args.
+ If there is a property "append-rootblock" in DT under /chosen
+ and a root= option in bootloaders command line it will be parsed
+ and added to DT bootargs with the form: <append-rootblock>XX.
+ Only command line ATAG will be processed, the rest of the ATAGs
+ sent by bootloader will be ignored.
+
endchoice
config CMDLINE
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -5,6 +5,8 @@
#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
#define do_extend_cmdline 1
+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+#define do_extend_cmdline 1
#else
#define do_extend_cmdline 0
#endif
@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const
return offset;
}
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
static int setprop(void *fdt, const char *node_path, const char *property,
void *val_array, int size)
{
@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char
return offset;
return fdt_setprop(fdt, offset, property, val_array, size);
}
+#endif
static int setprop_string(void *fdt, const char *node_path,
const char *property, const char *string)
@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con
return fdt_setprop_string(fdt, offset, property, string);
}
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
static int setprop_cell(void *fdt, const char *node_path,
const char *property, uint32_t val)
{
@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const
return offset;
return fdt_setprop_cell(fdt, offset, property, val);
}
+#endif
static const void *getprop(const void *fdt, const char *node_path,
const char *property, int *len)
@@ -58,6 +64,7 @@ static const void *getprop(const void *f
return fdt_getprop(fdt, offset, property, len);
}
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
static uint32_t get_cell_size(const void *fdt)
{
int len;
@@ -69,6 +76,74 @@ static uint32_t get_cell_size(const void
return cell_size;
}
+#endif
+
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+
+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
+{
+ const char *ptr, *end;
+ const char *root="root=";
+ int i, l;
+ const char *rootblock;
+
+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
+ ptr = str - 1;
+
+ do {
+ //first find an 'r' at the begining or after a space
+ do {
+ ptr++;
+ ptr = strchr(ptr, 'r');
+ if (!ptr)
+ goto no_append;
+
+ } while (ptr != str && *(ptr-1) != ' ');
+
+ //then check for the rest
+ for(i = 1; i <= 4; i++)
+ if(*(ptr+i) != *(root+i)) break;
+
+ } while (i != 5);
+
+ end = strchr(ptr, ' ');
+ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
+
+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
+ ptr = end + 1;
+
+ /* if append-rootblock property is set use it to append to command line */
+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
+ if (rootblock == NULL)
+ goto no_append;
+
+ if (*dest != ' ') {
+ *dest = ' ';
+ dest++;
+ len++;
+ }
+
+ if (len + l + i <= COMMAND_LINE_SIZE) {
+ memcpy(dest, rootblock, l);
+ dest += l - 1;
+ memcpy(dest, ptr, i);
+ dest += i;
+ }
+
+ return dest;
+
+no_append:
+ len = strlen(str);
+ if (len + 1 < COMMAND_LINE_SIZE) {
+ memcpy(dest, str, len);
+ dest += len;
+ }
+
+ return dest;
+}
+#endif
+
static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
{
char cmdline[COMMAND_LINE_SIZE];
@@ -88,18 +163,28 @@ static void merge_fdt_bootargs(void *fdt
/* and append the ATAG_CMDLINE */
if (fdt_cmdline) {
+
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+ //save original bootloader args
+ //and append ubi.mtd with root partition number to current cmdline
+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
+
+#else
len = strlen(fdt_cmdline);
if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
*ptr++ = ' ';
memcpy(ptr, fdt_cmdline, len);
ptr += len;
}
+#endif
}
*ptr = '\0';
setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
static void hex_str(char *out, uint32_t value)
{
uint32_t digit;
@@ -117,6 +202,7 @@ static void hex_str(char *out, uint32_t
}
*out = '\0';
}
+#endif
/*
* Convert and fold provided ATAGs into the provided FDT.
@@ -131,9 +217,11 @@ int atags_to_fdt(void *atag_list, void *
struct tag *atag = atag_list;
/* In the case of 64 bits memory size, need to reserve 2 cells for
* address and size for each bank */
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
__be32 mem_reg_property[2 * 2 * NR_BANKS];
- int memcount = 0;
- int ret, memsize;
+ int memsize, memcount = 0;
+#endif
+ int ret;
/* make sure we've got an aligned pointer */
if ((u32)atag_list & 0x3)
@@ -168,7 +256,9 @@ int atags_to_fdt(void *atag_list, void *
else
setprop_string(fdt, "/chosen", "bootargs",
atag->u.cmdline.cmdline);
- } else if (atag->hdr.tag == ATAG_MEM) {
+ }
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
+ else if (atag->hdr.tag == ATAG_MEM) {
if (memcount >= sizeof(mem_reg_property)/4)
continue;
if (!atag->u.mem.size)
@@ -212,6 +302,10 @@ int atags_to_fdt(void *atag_list, void *
setprop(fdt, "/memory", "reg", mem_reg_property,
4 * memcount * memsize);
}
+#else
+
+ }
+#endif
return fdt_pack(fdt);
}
--- a/init/main.c
+++ b/init/main.c
@@ -113,6 +113,10 @@
#include <kunit/test.h>
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+#include <linux/of.h>
+#endif
+
static int kernel_init(void *);
extern void init_IRQ(void);
@@ -996,6 +1000,18 @@ asmlinkage __visible void __init __no_sa
page_alloc_init();
pr_notice("Kernel command line: %s\n", saved_command_line);
+
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+ //Show bootloader's original command line for reference
+ if(of_chosen) {
+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
+ if(prop)
+ pr_notice("Bootloader command line (ignored): %s\n", prop);
+ else
+ pr_notice("Bootloader command line not present\n");
+ }
+#endif
+
/* parameters may set static keys */
jump_label_init();
parse_early_param();

10
target/linux/mvebu/patches-6.1/301-mvebu-armada-38x-enable-libata-leds.patch
View File

@ -1,10 +0,0 @@
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -66,6 +66,7 @@ config MACH_ARMADA_38X
select HAVE_ARM_TWD if SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_38X
+ select ARCH_WANT_LIBATA_LEDS
help
Say 'Y' here if you want your kernel to support boards based
on the Marvell Armada 380/385 SoC with device tree.

770
target/linux/mvebu/patches-6.1/302-add_powertables.patch
View File

@ -1,770 +0,0 @@
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -214,11 +214,19 @@
&pcie1 {
/* Marvell 88W8864, 5GHz-only */
status = "okay";
+
+ mwlwifi {
+ marvell,2ghz = <0>;
+ };
};
&pcie2 {
/* Marvell 88W8864, 2GHz-only */
status = "okay";
+
+ mwlwifi {
+ marvell,5ghz = <0>;
+ };
};
&pinctrl {
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
@@ -142,3 +142,205 @@
};
};
};
+
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <2 2>;
+ marvell,powertable {
+ AU =
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;
+ CA =
+ <36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
+ CN =
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;
+ ETSI =
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>;
+ FCC =
+ <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
+ };
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <2 2>;
+ marvell,powertable {
+ AU =
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
+ CA =
+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,
+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;
+ CN =
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
+ ETSI =
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
+ FCC =
+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
+};
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
@@ -142,3 +142,205 @@
};
};
};
+
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
+ CA =
+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ CN =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
+ ETSI =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
+ FCC =
+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ };
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ CA =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ CN =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ ETSI =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ FCC =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
+};
--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
@@ -142,3 +142,205 @@
};
};
};
+
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
+ CA =
+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ CN =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
+ ETSI =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
+ FCC =
+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ };
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ CA =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ CN =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ ETSI =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ FCC =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
+};
--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
@@ -157,6 +157,18 @@
};
};
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ };
+};
+
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -223,12 +223,100 @@
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
+
+ mwlwifi {
+ marvell,5ghz = <0>;
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ FCC =
+ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;
+
+ ETSI =
+ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
};
/* Second mini-PCIe port */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
+
+ mwlwifi {
+ marvell,2ghz = <0>;
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ FCC =
+ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;
+
+ ETSI =
+ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;
+ };
+ };
};
};

15
target/linux/mvebu/patches-6.1/304-revert_i2c_delay.patch
View File

@ -1,15 +0,0 @@
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -237,12 +237,10 @@
};
&i2c0 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
&i2c1 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};

19
target/linux/mvebu/patches-6.1/305-armada-385-rd-mtd-partitions.patch
View File

@ -1,19 +0,0 @@
--- a/arch/arm/boot/dts/armada-388-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -103,6 +103,16 @@
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0 0x400000>;
+ };
+
+ partition@1 {
+ label = "firmware";
+ reg = <0x400000 0xc00000>;
+ };
};
};

35
target/linux/mvebu/patches-6.1/306-ARM-mvebu-385-ap-Add-partitions.patch
View File

@ -1,35 +0,0 @@
From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Tue, 13 Jan 2015 11:14:09 +0100
Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/armada-385-db-ap.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -218,19 +218,19 @@
#size-cells = <1>;
partition@0 {
- label = "U-Boot";
+ label = "u-boot";
reg = <0x00000000 0x00800000>;
read-only;
};
partition@800000 {
- label = "uImage";
+ label = "kernel";
reg = <0x00800000 0x00400000>;
read-only;
};
partition@c00000 {
- label = "Root";
+ label = "ubi";
reg = <0x00c00000 0x3f400000>;
};
};

10
target/linux/mvebu/patches-6.1/307-armada-xp-linksys-mamba-broken-idle.patch
View File

@ -1,10 +0,0 @@
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -483,3 +483,7 @@
};
};
};
+
+&coherencyfab {
+ broken-idle;
+};

11
target/linux/mvebu/patches-6.1/308-armada-xp-linksys-mamba-wan.patch
View File

@ -1,11 +0,0 @@
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -385,7 +385,7 @@
port@4 {
reg = <4>;
- label = "internet";
+ label = "wan";
};
port@5 {

50
target/linux/mvebu/patches-6.1/309-linksys-status-led.patch
View File

@ -1,50 +0,0 @@
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -14,6 +14,13 @@
compatible = "linksys,armada385", "marvell,armada385",
"marvell,armada380";
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -71,7 +78,7 @@
pinctrl-0 = <&gpio_leds_pins>;
pinctrl-names = "default";
- power {
+ led_power: power {
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -26,6 +26,13 @@
compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
"marvell,armadaxp", "marvell,armada-370-xp";
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
@@ -195,7 +202,7 @@
pinctrl-0 = <&power_led_pin>;
pinctrl-names = "default";
- power {
+ led_power: power {
label = "mamba:white:power";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
default-state = "on";

25
target/linux/mvebu/patches-6.1/310-linksys-use-eth0-as-cpu-port.patch
View File

@ -1,25 +0,0 @@
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -116,7 +116,7 @@
};
&eth2 {
- status = "okay";
+ status = "disabled";
phy-mode = "sgmii";
buffer-manager = <&bm>;
bm,pool-long = <2>;
@@ -200,10 +200,10 @@
label = "wan";
};
- port@5 {
- reg = <5>;
+ port@6 {
+ reg = <6>;
label = "cpu";
- ethernet = <&eth2>;
+ ethernet = <&eth0>;
fixed-link {
speed = <1000>;

68
target/linux/mvebu/patches-6.1/311-adjust-compatible-for-linksys.patch
View File

@ -1,68 +0,0 @@
--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
@@ -12,8 +12,8 @@
/ {
model = "Linksys WRT3200ACM";
- compatible = "linksys,rango", "linksys,armada385", "marvell,armada385",
- "marvell,armada380";
+ compatible = "linksys,wrt3200acm", "linksys,rango", "linksys,armada385",
+ "marvell,armada385", "marvell,armada380";
};
&expander0 {
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -22,9 +22,10 @@
#include "armada-xp-mv78230.dtsi"
/ {
- model = "Linksys WRT1900AC";
- compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
- "marvell,armadaxp", "marvell,armada-370-xp";
+ model = "Linksys WRT1900AC v1";
+ compatible = "linksys,wrt1900ac-v1", "linksys,mamba",
+ "marvell,armadaxp-mv78230", "marvell,armadaxp",
+ "marvell,armada-370-xp";
aliases {
led-boot = &led_power;
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
@@ -9,8 +9,9 @@
#include "armada-385-linksys.dtsi"
/ {
- model = "Linksys WRT1900ACv2";
- compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
+ model = "Linksys WRT1900AC v2";
+ compatible = "linksys,wrt1900ac-v2", "linksys,cobra",
+ "linksys,armada385", "marvell,armada385",
"marvell,armada380";
};
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
@@ -10,8 +10,8 @@
/ {
model = "Linksys WRT1200AC";
- compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
- "marvell,armada380";
+ compatible = "linksys,wrt1200ac", "linksys,caiman", "linksys,armada385",
+ "marvell,armada385", "marvell,armada380";
};
&expander0 {
--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
@@ -10,7 +10,8 @@
/ {
model = "Linksys WRT1900ACS";
- compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
+ compatible = "linksys,wrt1900acs", "linksys,shelby",
+ "linksys,armada385", "marvell,armada385",
"marvell,armada380";
};

87
target/linux/mvebu/patches-6.1/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
View File

@ -1,87 +0,0 @@
From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Tue, 29 Nov 2016 10:15:45 +0000
Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
.../arm/boot/dts/armada-388-clearfog-base.dts | 1 +
.../armada-38x-solidrun-microsom-emmc.dtsi | 62 +++++++++++++++++++
2 files changed, 63 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "armada-388-clearfog.dtsi"
+#include "armada-38x-solidrun-microsom-emmc.dtsi"
/ {
model = "SolidRun Clearfog Base A1";
--- /dev/null
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
+ *
+ * Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board. Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/ {
+ soc {
+ internal-regs {
+ sdhci@d8000 {
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ pinctrl-0 = <&microsom_sdhci_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ wp-inverted;
+ };
+ };
+ };
+};

28
target/linux/mvebu/patches-6.1/313-helios4-dts-status-led-alias.patch
View File

@ -1,28 +0,0 @@
--- a/arch/arm/boot/dts/armada-388-helios4.dts
+++ b/arch/arm/boot/dts/armada-388-helios4.dts
@@ -15,6 +15,13 @@
model = "Helios4";
compatible = "kobol,helios4", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
+
+ aliases {
+ led-boot = &led_status;
+ led-failsafe = &led_status;
+ led-running = &led_status;
+ led-upgrade = &led_status;
+ };
memory {
device_type = "memory";
@@ -73,10 +80,9 @@
pinctrl-names = "default";
pinctrl-0 = <&helios_system_led_pins>;
- status-led {
+ led_status: status-led {
label = "helios4:green:status";
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
default-state = "on";
};

22
target/linux/mvebu/patches-6.1/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch
View File

@ -1,22 +0,0 @@
From: Tomasz Maciej Nowak <tmn505@gmail.com>
Date: Fri, 7 Jul 2023 19:06:05 +0200
Subject: [PATCH] arm64: dts: marvell: enable heartbeat LED by default
Some boards could be placed in an enclosure, so enable LED18 by default,
since that'll be the only visible indicator that the board is operating.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
---
arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
@@ -25,6 +25,7 @@
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_GREEN>;
linux,default-trigger = "heartbeat";
+ default-state = "on";
};
};
};

37
target/linux/mvebu/patches-6.1/315-armada-xp-linksys-mamba-resize-kernel.patch
View File

@ -1,37 +0,0 @@
From 258233f00bcd013050efee00c5d9128ef8cd62dd Mon Sep 17 00:00:00 2001
From: Tad <tad@spotco.us>
Date: Fri, 5 Feb 2021 22:32:11 -0500
Subject: [PATCH] ARM: dts: armada-xp-linksys-mamba: Increase kernel
partition to 4MB
Signed-off-by: Tad Davanzo <tad@spotco.us>
---
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -454,9 +454,9 @@
reg = <0xa00000 0x2800000>; /* 40MB */
};
- partition@d00000 {
+ partition@e00000 {
label = "rootfs1";
- reg = <0xd00000 0x2500000>; /* 37MB */
+ reg = <0xe00000 0x2400000>; /* 36MB */
};
/* kernel2 overlaps with rootfs2 by design */
@@ -465,9 +465,9 @@
reg = <0x3200000 0x2800000>; /* 40MB */
};
- partition@3500000 {
+ partition@3600000 {
label = "rootfs2";
- reg = <0x3500000 0x2500000>; /* 37MB */
+ reg = <0x3600000 0x2400000>; /* 36MB */
};
/*

29
target/linux/mvebu/patches-6.1/316-armada-370-dts-fix-crypto-engine.patch
View File

@ -1,29 +0,0 @@
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -254,7 +254,7 @@
clocks = <&gateclk 23>;
clock-names = "cesa0";
marvell,crypto-srams = <&crypto_sram>;
- marvell,crypto-sram-size = <0x7e0>;
+ marvell,crypto-sram-size = <0x800>;
};
};
@@ -275,12 +275,17 @@
* cpuidle workaround.
*/
idle-sram@0 {
+ status = "disabled";
reg = <0x0 0x20>;
};
};
};
};
+&coherencyfab {
+ broken-idle;
+};
+
/*
* Default UART pinctrl setting without RTS/CTS, can be overwritten on
* board level if a different configuration is used.

134
target/linux/mvebu/patches-6.1/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch
View File

@ -1,134 +0,0 @@
--- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -31,6 +31,7 @@
chosen {
stdout-path = "serial0:115200n8";
+ append-rootblock = "nullparameter="; /* override the bootloader args */
};
memory@0 {
@@ -94,6 +95,8 @@
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
+ nvmem-cells = <&macaddr_vendor_0>;
+ nvmem-cell-names = "mac-address";
};
sata@a0000 {
@@ -175,6 +178,24 @@
gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
};
};
+
+ virtual_flash {
+ compatible = "mtd-concat";
+
+ devices = <&mtd_kernel &mtd_gap &mtd_gap2>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ compatible = "openwrt,uimage", "denx,uimage";
+ label = "firmware";
+ reg = <0x0 0x0>;
+ };
+ };
+ };
};
&mdio {
@@ -265,48 +286,52 @@
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
- /*
- * Warning!
- *
- * Synology u-boot uses its compiled-in environment
- * and it seems Synology did not care to change u-boot
- * default configuration in order to allow saving a
- * modified environment at a sensible location. So,
- * if you do a 'saveenv' under u-boot, your modified
- * environment will be saved at 1MB after the start
- * of the flash, i.e. in the middle of the uImage.
- * For that reason, it is strongly advised not to
- * change the default environment, unless you know
- * what you are doing.
- */
- partition@0 { /* u-boot */
- label = "RedBoot";
- reg = <0x00000000 0x000c0000>; /* 768KB */
- };
+ partitions {
+ compatible = "fixed-partitions";
- partition@c0000 { /* uImage */
- label = "zImage";
- reg = <0x000c0000 0x002d0000>; /* 2880KB */
- };
+ partition@0 { /* u-boot */
+ label = "u-boot";
+ reg = <0x00000000 0x000c0000>; /* 768KB */
+ read-only;
+ };
- partition@390000 { /* uInitramfs */
- label = "rd.gz";
- reg = <0x00390000 0x00440000>; /* 4250KB */
- };
+ mtd_gap: partition@c0000 { /* gap */
+ label = "gap";
+ reg = <0x000c0000 0x00040000>; /* 256KB */
+ };
- partition@7d0000 { /* MAC address and serial number */
- label = "vendor";
- reg = <0x007d0000 0x00010000>; /* 64KB */
- };
+ partition@100000 { /* u-boot-env */
+ label = "u-boot-env";
+ reg = <0x00100000 0x00010000>; /* 64KB */
+ };
- partition@7e0000 {
- label = "RedBoot config";
- reg = <0x007e0000 0x00010000>; /* 64KB */
- };
+ mtd_kernel: partition@110000 {
+ label = "kernel";
+ reg = <0x00110000 0x006c0000>; /* 6912KB */
+ };
- partition@7f0000 {
- label = "FIS directory";
- reg = <0x007f0000 0x00010000>; /* 64KB */
+ partition@7d0000 { /* MAC address and serial number */
+ reg = <0x007d0000 0x00010000>; /* 64KB */
+ label = "vendor";
+ read-only;
+
+ compatible = "nvmem-cells";
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_vendor_0: macaddr@0 {
+ reg = <0x0 0x6>;
+ };
+ };
+ };
+
+ mtd_gap2: partition@7e0000 {
+ label = "gap2";
+ reg = <0x007e0000 0x00020000>; /* 128KB */
+ };
};
};
};

60
target/linux/mvebu/patches-6.1/400-find_active_root.patch
View File

@ -1,60 +0,0 @@
The WRT1900AC among other Linksys routers uses a dual-firmware layout.
Dynamically rename the active partition to "ubi".
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
--- a/drivers/mtd/parsers/ofpart_core.c
+++ b/drivers/mtd/parsers/ofpart_core.c
@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d
return of_get_property(pp, "compatible", NULL);
}
+static int mangled_rootblock;
+
static int parse_fixed_partitions(struct mtd_info *master,
const struct mtd_partition **pparts,
struct mtd_part_parser_data *data)
@@ -48,6 +50,7 @@ static int parse_fixed_partitions(struct
struct device_node *mtd_node;
struct device_node *ofpart_node;
const char *partname;
+ const char *owrtpart = "ubi";
struct device_node *pp;
int nr_parts, i, ret = 0;
bool dedicated = true;
@@ -152,9 +155,13 @@ static int parse_fixed_partitions(struct
parts[i].size = of_read_number(reg + a_cells, s_cells);
parts[i].of_node = pp;
- partname = of_get_property(pp, "label", &len);
- if (!partname)
- partname = of_get_property(pp, "name", &len);
+ if (mangled_rootblock && (i == mangled_rootblock)) {
+ partname = owrtpart;
+ } else {
+ partname = of_get_property(pp, "label", &len);
+ if (!partname)
+ partname = of_get_property(pp, "name", &len);
+ }
parts[i].name = partname;
if (of_get_property(pp, "read-only", &len))
@@ -271,6 +278,18 @@ static int __init ofpart_parser_init(voi
return 0;
}
+static int __init active_root(char *str)
+{
+ get_option(&str, &mangled_rootblock);
+
+ if (!mangled_rootblock)
+ return 1;
+
+ return 1;
+}
+
+__setup("mangled_rootblock=", active_root);
+
static void __exit ofpart_parser_exit(void)
{
deregister_mtd_parser(&ofpart_parser);

43
target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch
View File

@ -1,43 +0,0 @@
From: Felix Fietkau <nbd@nbd.name>
Subject: mvneta: tx queue workaround
The hardware queue scheduling is apparently configured with fixed
priorities, which creates a nasty fairness issue where traffic from one
CPU can starve traffic from all other CPUs.
Work around this issue by forcing all tx packets to go through one CPU,
until this issue is fixed properly.
Ref: https://github.com/openwrt/openwrt/issues/5411
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -5233,6 +5233,16 @@ static int mvneta_setup_tc(struct net_de
}
}
+#ifndef CONFIG_ARM64
+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
+ struct net_device *sb_dev)
+{
+ /* XXX: hardware queue scheduling is broken,
+ * use only one queue until it is fixed */
+ return 0;
+}
+#endif
+
static const struct net_device_ops mvneta_netdev_ops = {
.ndo_open = mvneta_open,
.ndo_stop = mvneta_stop,
@@ -5243,6 +5253,9 @@ static const struct net_device_ops mvnet
.ndo_fix_features = mvneta_fix_features,
.ndo_get_stats64 = mvneta_get_stats64,
.ndo_eth_ioctl = mvneta_ioctl,
+#ifndef CONFIG_ARM64
+ .ndo_select_queue = mvneta_select_queue,
+#endif
.ndo_bpf = mvneta_xdp,
.ndo_xdp_xmit = mvneta_xdp_xmit,
.ndo_setup_tc = mvneta_setup_tc,

27
target/linux/mvebu/patches-6.1/701-mvpp2-read-mac-address-from-nvmem.patch
View File

@ -1,27 +0,0 @@
From: Tobias Schramm <tobias@t-sys.eu>
Subject: mvpp2: support fetching mac address from nvmem
The mvpp2 driver did not query nvmem for hardware mac addresses. This
patch adds querying of mac addresses stored in nvmem cells as a further
fallback option before assigning a random address.
Purposely added separately to fwnode_get_mac_address() above to maintain
existing behaviour with builtin adapter mac address still taking
precedence.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
---
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -6134,6 +6134,12 @@ static void mvpp2_port_copy_mac_addr(str
}
}
+ if (!of_get_mac_address(to_of_node(fwnode), hw_mac_addr)) {
+ *mac_from = "nvmem cell";
+ eth_hw_addr_set(dev, hw_mac_addr);
+ return;
+ }
+
*mac_from = "random";
eth_hw_addr_random(dev);
}

40
target/linux/mvebu/patches-6.1/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
View File

@ -1,40 +0,0 @@
From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Sat, 3 Oct 2015 09:13:05 +0100
Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states
The cpuidle ->enter method expects the return value to be the sleep
state we entered. Returning negative numbers or other codes is not
permissible since coupled CPU idle was merged.
At least some of the mvebu_v7_cpu_suspend() implementations return the
value from cpu_suspend(), which returns zero if the CPU vectors back
into the kernel via cpu_resume() (the success case), or the non-zero
return value of the suspend actor, or one (failure cases).
We do not want to be returning the failure case value back to CPU idle
as that indicates that we successfully entered one of the deeper idle
states. Always return zero instead, indicating that we slept for the
shortest amount of time.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
--- a/drivers/cpuidle/cpuidle-mvebu-v7.c
+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp
ret = mvebu_v7_cpu_suspend(deepidle);
cpu_pm_exit();
+ /*
+ * If we failed to enter the desired state, indicate that we
+ * slept lightly.
+ */
if (ret)
- return ret;
+ return 0;
return index;
}

60
target/linux/mvebu/patches-6.1/801-pci-mvebu-time-out-reset-on-link-up.patch
View File

@ -1,60 +0,0 @@
From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Sat, 9 Jul 2016 10:58:16 +0100
Subject: pci: mvebu: time out reset on link up
If the port reports that the link is up while we are resetting, there's
little point in waiting for the full duration.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -1414,6 +1414,7 @@ static int mvebu_pcie_powerup(struct mve
if (port->reset_gpio) {
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
+ unsigned int i;
of_property_read_u32(port->dn, "reset-delay-us",
&reset_udelay);
@@ -1421,7 +1422,13 @@ static int mvebu_pcie_powerup(struct mve
udelay(100);
gpiod_set_value_cansleep(port->reset_gpio, 0);
- msleep(reset_udelay / 1000);
+ for (i = 0; i < reset_udelay; i += 1000) {
+ if (mvebu_pcie_link_up(port))
+ break;
+ msleep(1);
+ }
+
+ printk("%s: reset completed in %dus\n", port->name, i);
}
return 0;
@@ -1538,15 +1545,16 @@ static int mvebu_pcie_probe(struct platf
if (!child)
continue;
- ret = mvebu_pcie_powerup(port);
- if (ret < 0)
- continue;
-
port->base = mvebu_pcie_map_registers(pdev, child, port);
if (IS_ERR(port->base)) {
dev_err(dev, "%s: cannot map registers\n", port->name);
port->base = NULL;
- mvebu_pcie_powerdown(port);
+ continue;
+ }
+
+ ret = mvebu_pcie_powerup(port);
+ if (ret < 0) {
+ port->base = NULL;
continue;
}

218
target/linux/mvebu/patches-6.1/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch
View File

@ -1,218 +0,0 @@
From aa4a0ccc41997f2da172165c92803abace43bd1c Mon Sep 17 00:00:00 2001
From: Luka Kovacic <luka.kovacic () sartura ! hr>
Date: Tue, 24 Aug 2021 12:44:32 +0000
Subject: [PATCH 1/7] dt-bindings: Add IEI vendor prefix and IEI WT61P803
PUZZLE driver bindings
Add the IEI WT61P803 PUZZLE Device Tree bindings for MFD, HWMON and LED
drivers. A new vendor prefix is also added accordingly for
IEI Integration Corp.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Robert Marko <robert.marko@sartura.hr>
---
.../hwmon/iei,wt61p803-puzzle-hwmon.yaml | 53 ++++++++++++
.../leds/iei,wt61p803-puzzle-leds.yaml | 39 +++++++++
.../bindings/mfd/iei,wt61p803-puzzle.yaml | 82 +++++++++++++++++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
4 files changed, 176 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
create mode 100644 Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
create mode 100644 Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IEI WT61P803 PUZZLE MCU HWMON module from IEI Integration Corp.
+
+maintainers:
+ - Luka Kovacic <luka.kovacic@sartura.hr>
+
+description: |
+ This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
+ see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
+
+ The HWMON module is a sub-node of the MCU node in the Device Tree.
+
+properties:
+ compatible:
+ const: iei,wt61p803-puzzle-hwmon
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^fan-group@[0-1]$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 1
+ description:
+ Fan group ID
+
+ cooling-levels:
+ minItems: 1
+ maxItems: 255
+ description:
+ Cooling levels for the fans (PWM value mapping)
+ description: |
+ Properties for each fan group.
+ required:
+ - reg
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/iei,wt61p803-puzzle-leds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IEI WT61P803 PUZZLE MCU LED module from IEI Integration Corp.
+
+maintainers:
+ - Luka Kovacic <luka.kovacic@sartura.hr>
+
+description: |
+ This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
+ see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
+
+ The LED module is a sub-node of the MCU node in the Device Tree.
+
+properties:
+ compatible:
+ const: iei,wt61p803-puzzle-leds
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ led@0:
+ type: object
+ $ref: common.yaml
+ description: |
+ Properties for a single LED.
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/iei,wt61p803-puzzle.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IEI WT61P803 PUZZLE MCU from IEI Integration Corp.
+
+maintainers:
+ - Luka Kovacic <luka.kovacic@sartura.hr>
+
+description: |
+ IEI WT61P803 PUZZLE MCU is embedded in some IEI Puzzle series boards.
+ It's used for controlling system power states, fans, LEDs and temperature
+ sensors.
+
+ For Device Tree bindings of other sub-modules (HWMON, LEDs) refer to the
+ binding documents under the respective subsystem directories.
+
+properties:
+ compatible:
+ const: iei,wt61p803-puzzle
+
+ current-speed:
+ description:
+ Serial bus speed in bps
+ maxItems: 1
+
+ enable-beep: true
+
+ hwmon:
+ $ref: /schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml
+
+ leds:
+ $ref: /schemas/leds/iei,wt61p803-puzzle-leds.yaml
+
+required:
+ - compatible
+ - current-speed
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+ serial {
+ mcu {
+ compatible = "iei,wt61p803-puzzle";
+ current-speed = <115200>;
+ enable-beep;
+
+ leds {
+ compatible = "iei,wt61p803-puzzle-leds";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+
+ hwmon {
+ compatible = "iei,wt61p803-puzzle-hwmon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan-group@0 {
+ #cooling-cells = <2>;
+ reg = <0x00>;
+ cooling-levels = <64 102 170 230 250>;
+ };
+
+ fan-group@1 {
+ #cooling-cells = <2>;
+ reg = <0x01>;
+ cooling-levels = <64 102 170 230 250>;
+ };
+ };
+ };
+ };
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -579,6 +579,8 @@ patternProperties:
description: IC Plus Corp.
"^idt,.*":
description: Integrated Device Technologies, Inc.
+ "^iei,.*":
+ description: IEI Integration Corp.
"^ifi,.*":
description: Ingenieurburo Fur Ic-Technologie (I/F/I)
"^ilitek,.*":

1034
target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch
View File

File diff suppressed because it is too large Load Diff

501
target/linux/mvebu/patches-6.1/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch
View File

@ -1,501 +0,0 @@
From e3310a638cd310bfd93dbbc6d2732ab6aea18dd2 Mon Sep 17 00:00:00 2001
From: Luka Kovacic <luka.kovacic () sartura ! hr>
Date: Tue, 24 Aug 2021 12:44:34 +0000
Subject: [PATCH 3/7] drivers: hwmon: Add the IEI WT61P803 PUZZLE HWMON driver
Add the IEI WT61P803 PUZZLE HWMON driver, that handles the fan speed
control via PWM, reading fan speed and reading on-board temperature
sensors.
The driver registers a HWMON device and a simple thermal cooling device to
enable in-kernel fan management.
This driver depends on the IEI WT61P803 PUZZLE MFD driver.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Robert Marko <robert.marko@sartura.hr>
---
drivers/hwmon/Kconfig | 8 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 445 ++++++++++++++++++++++
3 files changed, 454 insertions(+)
create mode 100644 drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -755,6 +755,14 @@ config SENSORS_IBMPOWERNV
This driver can also be built as a module. If so, the module
will be called ibmpowernv.
+config SENSORS_IEI_WT61P803_PUZZLE_HWMON
+ tristate "IEI WT61P803 PUZZLE MFD HWMON Driver"
+ depends on MFD_IEI_WT61P803_PUZZLE
+ help
+ The IEI WT61P803 PUZZLE MFD HWMON Driver handles reading fan speed
+ and writing fan PWM values. It also supports reading on-board
+ temperature sensors.
+
config SENSORS_IIO_HWMON
tristate "Hwmon driver that uses channels specified via iio maps"
depends on IIO
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_SENSORS_HIH6130) += hih6130
obj-$(CONFIG_SENSORS_ULTRA45) += ultra45_env.o
obj-$(CONFIG_SENSORS_I5500) += i5500_temp.o
obj-$(CONFIG_SENSORS_I5K_AMB) += i5k_amb.o
+obj-$(CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON) += iei-wt61p803-puzzle-hwmon.o
obj-$(CONFIG_SENSORS_IBMAEM) += ibmaem.o
obj-$(CONFIG_SENSORS_IBMPEX) += ibmpex.o
obj-$(CONFIG_SENSORS_IBMPOWERNV)+= ibmpowernv.o
--- /dev/null
+++ b/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
@@ -0,0 +1,445 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* IEI WT61P803 PUZZLE MCU HWMON Driver
+ *
+ * Copyright (C) 2020 Sartura Ltd.
+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
+ */
+
+#include <linux/err.h>
+#include <linux/hwmon.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/math64.h>
+#include <linux/mfd/iei-wt61p803-puzzle.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/slab.h>
+#include <linux/thermal.h>
+
+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM 2
+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL 255
+
+/**
+ * struct iei_wt61p803_puzzle_thermal_cooling_device - Thermal cooling device instance
+ * @mcu_hwmon: Parent driver struct pointer
+ * @tcdev: Thermal cooling device pointer
+ * @name: Thermal cooling device name
+ * @pwm_channel: Controlled PWM channel (0 or 1)
+ * @cooling_levels: Thermal cooling device cooling levels (DT)
+ * @cur_level: Current cooling level
+ * @num_levels: Number of cooling levels
+ */
+struct iei_wt61p803_puzzle_thermal_cooling_device {
+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon;
+ struct thermal_cooling_device *tcdev;
+ char name[THERMAL_NAME_LENGTH];
+ int pwm_channel;
+ u32 *cooling_levels;
+ int cur_level;
+ u8 num_levels;
+};
+
+/**
+ * struct iei_wt61p803_puzzle_hwmon - MCU HWMON Driver
+ * @mcu: MCU struct pointer
+ * @response_buffer Global MCU response buffer
+ * @thermal_cooling_dev_present: Per-channel thermal cooling device control indicator
+ * @cdev: Per-channel thermal cooling device private structure
+ */
+struct iei_wt61p803_puzzle_hwmon {
+ struct iei_wt61p803_puzzle *mcu;
+ unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
+ bool thermal_cooling_dev_present[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];
+ struct iei_wt61p803_puzzle_thermal_cooling_device
+ *cdev[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];
+ struct mutex lock; /* mutex to protect response_buffer array */
+};
+
+#define raw_temp_to_milidegree_celsius(x) (((x) - 0x80) * 1000)
+static int iei_wt61p803_puzzle_read_temp_sensor(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
+ int channel, long *value)
+{
+ unsigned char *resp_buf = mcu_hwmon->response_buffer;
+ unsigned char temp_sensor_ntc_cmd[4] = {
+ IEI_WT61P803_PUZZLE_CMD_HEADER_START,
+ IEI_WT61P803_PUZZLE_CMD_TEMP,
+ IEI_WT61P803_PUZZLE_CMD_TEMP_ALL,
+ };
+ size_t reply_size;
+ int ret;
+
+ mutex_lock(&mcu_hwmon->lock);
+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, temp_sensor_ntc_cmd,
+ sizeof(temp_sensor_ntc_cmd), resp_buf,
+ &reply_size);
+ if (ret)
+ goto exit;
+
+ if (reply_size != 7) {
+ ret = -EIO;
+ goto exit;
+ }
+
+ /* Check the number of NTC values */
+ if (resp_buf[3] != '2') {
+ ret = -EIO;
+ goto exit;
+ }
+
+ *value = raw_temp_to_milidegree_celsius(resp_buf[4 + channel]);
+exit:
+ mutex_unlock(&mcu_hwmon->lock);
+ return ret;
+}
+
+#define raw_fan_val_to_rpm(x, y) ((((x) << 8 | (y)) / 2) * 60)
+static int iei_wt61p803_puzzle_read_fan_speed(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
+ int channel, long *value)
+{
+ unsigned char *resp_buf = mcu_hwmon->response_buffer;
+ unsigned char fan_speed_cmd[4] = {};
+ size_t reply_size;
+ int ret;
+
+ fan_speed_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
+ fan_speed_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
+ fan_speed_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_RPM(channel);
+
+ mutex_lock(&mcu_hwmon->lock);
+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, fan_speed_cmd,
+ sizeof(fan_speed_cmd), resp_buf,
+ &reply_size);
+ if (ret)
+ goto exit;
+
+ if (reply_size != 7) {
+ ret = -EIO;
+ goto exit;
+ }
+
+ *value = raw_fan_val_to_rpm(resp_buf[3], resp_buf[4]);
+exit:
+ mutex_unlock(&mcu_hwmon->lock);
+ return ret;
+}
+
+static int iei_wt61p803_puzzle_write_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
+ int channel, long pwm_set_val)
+{
+ unsigned char *resp_buf = mcu_hwmon->response_buffer;
+ unsigned char pwm_set_cmd[6] = {};
+ size_t reply_size;
+ int ret;
+
+ pwm_set_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
+ pwm_set_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
+ pwm_set_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE;
+ pwm_set_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);
+ pwm_set_cmd[4] = pwm_set_val;
+
+ mutex_lock(&mcu_hwmon->lock);
+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_set_cmd,
+ sizeof(pwm_set_cmd), resp_buf,
+ &reply_size);
+ if (ret)
+ goto exit;
+
+ if (reply_size != 3) {
+ ret = -EIO;
+ goto exit;
+ }
+
+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
+ ret = -EIO;
+ goto exit;
+ }
+exit:
+ mutex_unlock(&mcu_hwmon->lock);
+ return ret;
+}
+
+static int iei_wt61p803_puzzle_read_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
+ int channel, long *value)
+{
+ unsigned char *resp_buf = mcu_hwmon->response_buffer;
+ unsigned char pwm_get_cmd[5] = {};
+ size_t reply_size;
+ int ret;
+
+ pwm_get_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
+ pwm_get_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
+ pwm_get_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ;
+ pwm_get_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);
+
+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_get_cmd,
+ sizeof(pwm_get_cmd), resp_buf,
+ &reply_size);
+ if (ret)
+ return ret;
+
+ if (reply_size != 5)
+ return -EIO;
+
+ if (resp_buf[2] != IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ)
+ return -EIO;
+
+ *value = resp_buf[3];
+
+ return 0;
+}
+
+static int iei_wt61p803_puzzle_read(struct device *dev, enum hwmon_sensor_types type,
+ u32 attr, int channel, long *val)
+{
+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);
+
+ switch (type) {
+ case hwmon_pwm:
+ return iei_wt61p803_puzzle_read_pwm_channel(mcu_hwmon, channel, val);
+ case hwmon_fan:
+ return iei_wt61p803_puzzle_read_fan_speed(mcu_hwmon, channel, val);
+ case hwmon_temp:
+ return iei_wt61p803_puzzle_read_temp_sensor(mcu_hwmon, channel, val);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int iei_wt61p803_puzzle_write(struct device *dev, enum hwmon_sensor_types type,
+ u32 attr, int channel, long val)
+{
+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);
+
+ return iei_wt61p803_puzzle_write_pwm_channel(mcu_hwmon, channel, val);
+}
+
+static umode_t iei_wt61p803_puzzle_is_visible(const void *data, enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+ const struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = data;
+
+ switch (type) {
+ case hwmon_pwm:
+ if (mcu_hwmon->thermal_cooling_dev_present[channel])
+ return 0444;
+ if (attr == hwmon_pwm_input)
+ return 0644;
+ break;
+ case hwmon_fan:
+ if (attr == hwmon_fan_input)
+ return 0444;
+ break;
+ case hwmon_temp:
+ if (attr == hwmon_temp_input)
+ return 0444;
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static const struct hwmon_ops iei_wt61p803_puzzle_hwmon_ops = {
+ .is_visible = iei_wt61p803_puzzle_is_visible,
+ .read = iei_wt61p803_puzzle_read,
+ .write = iei_wt61p803_puzzle_write,
+};
+
+static const struct hwmon_channel_info *iei_wt61p803_puzzle_info[] = {
+ HWMON_CHANNEL_INFO(pwm,
+ HWMON_PWM_INPUT,
+ HWMON_PWM_INPUT),
+ HWMON_CHANNEL_INFO(fan,
+ HWMON_F_INPUT,
+ HWMON_F_INPUT,
+ HWMON_F_INPUT,
+ HWMON_F_INPUT,
+ HWMON_F_INPUT),
+ HWMON_CHANNEL_INFO(temp,
+ HWMON_T_INPUT,
+ HWMON_T_INPUT),
+ NULL
+};
+
+static const struct hwmon_chip_info iei_wt61p803_puzzle_chip_info = {
+ .ops = &iei_wt61p803_puzzle_hwmon_ops,
+ .info = iei_wt61p803_puzzle_info,
+};
+
+static int iei_wt61p803_puzzle_get_max_state(struct thermal_cooling_device *tcdev,
+ unsigned long *state)
+{
+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
+
+ if (!cdev)
+ return -EINVAL;
+
+ *state = cdev->num_levels - 1;
+ return 0;
+}
+
+static int iei_wt61p803_puzzle_get_cur_state(struct thermal_cooling_device *tcdev,
+ unsigned long *state)
+{
+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
+
+ if (!cdev)
+ return -EINVAL;
+
+ if (cdev->cur_level < 0)
+ return -EAGAIN;
+
+ *state = cdev->cur_level;
+ return 0;
+}
+
+static int iei_wt61p803_puzzle_set_cur_state(struct thermal_cooling_device *tcdev,
+ unsigned long state)
+{
+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
+ u8 pwm_level;
+
+ if (!cdev)
+ return -EINVAL;
+
+ if (state >= cdev->num_levels)
+ return -EINVAL;
+
+ if (state == cdev->cur_level)
+ return 0;
+
+ cdev->cur_level = state;
+ pwm_level = cdev->cooling_levels[state];
+
+ return iei_wt61p803_puzzle_write_pwm_channel(cdev->mcu_hwmon, cdev->pwm_channel, pwm_level);
+}
+
+static const struct thermal_cooling_device_ops iei_wt61p803_puzzle_cooling_ops = {
+ .get_max_state = iei_wt61p803_puzzle_get_max_state,
+ .get_cur_state = iei_wt61p803_puzzle_get_cur_state,
+ .set_cur_state = iei_wt61p803_puzzle_set_cur_state,
+};
+
+static int
+iei_wt61p803_puzzle_enable_thermal_cooling_dev(struct device *dev,
+ struct fwnode_handle *child,
+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon)
+{
+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev;
+ u32 pwm_channel;
+ u8 num_levels;
+ int i, ret;
+
+ ret = fwnode_property_read_u32(child, "reg", &pwm_channel);
+ if (ret)
+ return ret;
+
+ mcu_hwmon->thermal_cooling_dev_present[pwm_channel] = true;
+
+ num_levels = fwnode_property_count_u32(child, "cooling-levels");
+ if (!num_levels)
+ return -EINVAL;
+
+ cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
+ if (!cdev)
+ return -ENOMEM;
+
+ cdev->cooling_levels = devm_kmalloc_array(dev, num_levels, sizeof(u32), GFP_KERNEL);
+ if (!cdev->cooling_levels)
+ return -ENOMEM;
+
+ ret = fwnode_property_read_u32_array(child, "cooling-levels",
+ cdev->cooling_levels,
+ num_levels);
+ if (ret) {
+ dev_err(dev, "Couldn't read property 'cooling-levels'\n");
+ return ret;
+ }
+
+ for (i = 0; i < num_levels; i++) {
+ if (cdev->cooling_levels[i] >
+ IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL) {
+ dev_err(dev, "iei_wt61p803_fan state[%d]:%d > %d\n", i,
+ cdev->cooling_levels[i],
+ IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL);
+ return -EINVAL;
+ }
+ }
+
+ cdev->mcu_hwmon = mcu_hwmon;
+ cdev->pwm_channel = pwm_channel;
+ cdev->num_levels = num_levels;
+ cdev->cur_level = -1;
+ mcu_hwmon->cdev[pwm_channel] = cdev;
+
+ snprintf(cdev->name, THERMAL_NAME_LENGTH, "wt61p803_puzzle_%d", pwm_channel);
+ cdev->tcdev = devm_thermal_of_cooling_device_register(dev, to_of_node(child), cdev->name,
+ cdev, &iei_wt61p803_puzzle_cooling_ops);
+ if (IS_ERR(cdev->tcdev))
+ return PTR_ERR(cdev->tcdev);
+
+ return 0;
+}
+
+static int iei_wt61p803_puzzle_hwmon_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon;
+ struct fwnode_handle *child;
+ struct device *hwmon_dev;
+ int ret;
+
+ mcu_hwmon = devm_kzalloc(dev, sizeof(*mcu_hwmon), GFP_KERNEL);
+ if (!mcu_hwmon)
+ return -ENOMEM;
+
+ mcu_hwmon->mcu = mcu;
+ platform_set_drvdata(pdev, mcu_hwmon);
+ mutex_init(&mcu_hwmon->lock);
+
+ hwmon_dev = devm_hwmon_device_register_with_info(dev, "iei_wt61p803_puzzle",
+ mcu_hwmon,
+ &iei_wt61p803_puzzle_chip_info,
+ NULL);
+ if (IS_ERR(hwmon_dev))
+ return PTR_ERR(hwmon_dev);
+
+ /* Control fans via PWM lines via Linux Kernel */
+ if (IS_ENABLED(CONFIG_THERMAL)) {
+ device_for_each_child_node(dev, child) {
+ ret = iei_wt61p803_puzzle_enable_thermal_cooling_dev(dev, child, mcu_hwmon);
+ if (ret) {
+ dev_err(dev, "Enabling the PWM fan failed\n");
+ fwnode_handle_put(child);
+ return ret;
+ }
+ }
+ }
+ return 0;
+}
+
+static const struct of_device_id iei_wt61p803_puzzle_hwmon_id_table[] = {
+ { .compatible = "iei,wt61p803-puzzle-hwmon" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_hwmon_id_table);
+
+static struct platform_driver iei_wt61p803_puzzle_hwmon_driver = {
+ .driver = {
+ .name = "iei-wt61p803-puzzle-hwmon",
+ .of_match_table = iei_wt61p803_puzzle_hwmon_id_table,
+ },
+ .probe = iei_wt61p803_puzzle_hwmon_probe,
+};
+
+module_platform_driver(iei_wt61p803_puzzle_hwmon_driver);
+
+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU HWMON Driver");
+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
+MODULE_LICENSE("GPL v2");

207
target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
View File

@ -1,207 +0,0 @@
From f3b44eb69cc561cf05d00506dcec0dd9be003ed8 Mon Sep 17 00:00:00 2001
From: Luka Kovacic <luka.kovacic () sartura ! hr>
Date: Tue, 24 Aug 2021 12:44:35 +0000
Subject: [PATCH 4/7] drivers: leds: Add the IEI WT61P803 PUZZLE LED driver
Add support for the IEI WT61P803 PUZZLE LED driver.
Currently only the front panel power LED is supported,
since it is the only LED on this board wired through the
MCU.
The LED is wired directly to the on-board MCU controller
and is toggled using an MCU command.
Support for more LEDs is going to be added in case more
boards implement this microcontroller, as LEDs use many
different GPIOs.
This driver depends on the IEI WT61P803 PUZZLE MFD driver.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Robert Marko <robert.marko@sartura.hr>
---
drivers/leds/Kconfig | 8 ++
drivers/leds/Makefile | 1 +
drivers/leds/leds-iei-wt61p803-puzzle.c | 147 ++++++++++++++++++++++++
3 files changed, 156 insertions(+)
create mode 100644 drivers/leds/leds-iei-wt61p803-puzzle.c
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -300,6 +300,14 @@ config LEDS_IPAQ_MICRO
Choose this option if you want to use the notification LED on
Compaq/HP iPAQ h3100 and h3600.
+config LEDS_IEI_WT61P803_PUZZLE
+ tristate "LED Support for the IEI WT61P803 PUZZLE MCU"
+ depends on LEDS_CLASS
+ depends on MFD_IEI_WT61P803_PUZZLE
+ help
+ This option enables support for LEDs controlled by the IEI WT61P803
+ M801 MCU.
+
config LEDS_HP6XX
tristate "LED Support for the HP Jornada 6xx"
depends on LEDS_CLASS
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.
obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
obj-$(CONFIG_LEDS_IP30) += leds-ip30.o
obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o
+obj-$(CONFIG_LEDS_IEI_WT61P803_PUZZLE) += leds-iei-wt61p803-puzzle.o
obj-$(CONFIG_LEDS_IS31FL319X) += leds-is31fl319x.o
obj-$(CONFIG_LEDS_IS31FL32XX) += leds-is31fl32xx.o
obj-$(CONFIG_LEDS_LM3530) += leds-lm3530.o
--- /dev/null
+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* IEI WT61P803 PUZZLE MCU LED Driver
+ *
+ * Copyright (C) 2020 Sartura Ltd.
+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
+ */
+
+#include <linux/leds.h>
+#include <linux/mfd/iei-wt61p803-puzzle.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/slab.h>
+
+enum iei_wt61p803_puzzle_led_state {
+ IEI_LED_OFF = 0x30,
+ IEI_LED_ON = 0x31,
+ IEI_LED_BLINK_5HZ = 0x32,
+ IEI_LED_BLINK_1HZ = 0x33,
+};
+
+/**
+ * struct iei_wt61p803_puzzle_led - MCU LED Driver
+ * @cdev: LED classdev
+ * @mcu: MCU struct pointer
+ * @response_buffer Global MCU response buffer
+ * @lock: General mutex lock to protect simultaneous R/W access to led_power_state
+ * @led_power_state: State of the front panel power LED
+ */
+struct iei_wt61p803_puzzle_led {
+ struct led_classdev cdev;
+ struct iei_wt61p803_puzzle *mcu;
+ unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
+ struct mutex lock; /* mutex to protect led_power_state */
+ int led_power_state;
+};
+
+static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led
+ (struct led_classdev *led_cdev)
+{
+ return container_of(led_cdev, struct iei_wt61p803_puzzle_led, cdev);
+}
+
+static int iei_wt61p803_puzzle_led_brightness_set_blocking(struct led_classdev *cdev,
+ enum led_brightness brightness)
+{
+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
+ unsigned char *resp_buf = priv->response_buffer;
+ unsigned char led_power_cmd[5] = {};
+ size_t reply_size;
+ int ret;
+
+ led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
+ led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
+ led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;
+ led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;
+
+ ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,
+ sizeof(led_power_cmd),
+ resp_buf,
+ &reply_size);
+ if (ret)
+ return ret;
+
+ if (reply_size != 3)
+ return -EIO;
+
+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK))
+ return -EIO;
+
+ mutex_lock(&priv->lock);
+ priv->led_power_state = brightness;
+ mutex_unlock(&priv->lock);
+
+ return 0;
+}
+
+static enum led_brightness iei_wt61p803_puzzle_led_brightness_get(struct led_classdev *cdev)
+{
+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
+ int led_state;
+
+ mutex_lock(&priv->lock);
+ led_state = priv->led_power_state;
+ mutex_unlock(&priv->lock);
+
+ return led_state;
+}
+
+static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
+ struct iei_wt61p803_puzzle_led *priv;
+ struct led_init_data init_data = {};
+ struct fwnode_handle *child;
+ int ret;
+
+ if (device_get_child_node_count(dev) != 1)
+ return -EINVAL;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->mcu = mcu;
+ priv->led_power_state = 1;
+ mutex_init(&priv->lock);
+ dev_set_drvdata(dev, priv);
+
+ child = device_get_next_child_node(dev, NULL);
+ init_data.fwnode = child;
+
+ priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
+ priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
+ priv->cdev.max_brightness = 1;
+
+ ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
+ if (ret)
+ dev_err(dev, "Could not register LED\n");
+
+ fwnode_handle_put(child);
+ return ret;
+}
+
+static const struct of_device_id iei_wt61p803_puzzle_led_of_match[] = {
+ { .compatible = "iei,wt61p803-puzzle-leds" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_led_of_match);
+
+static struct platform_driver iei_wt61p803_puzzle_led_driver = {
+ .driver = {
+ .name = "iei-wt61p803-puzzle-led",
+ .of_match_table = iei_wt61p803_puzzle_led_of_match,
+ },
+ .probe = iei_wt61p803_puzzle_led_probe,
+};
+module_platform_driver(iei_wt61p803_puzzle_led_driver);
+
+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE front panel LED driver");
+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:leds-iei-wt61p803-puzzle");

82
target/linux/mvebu/patches-6.1/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch
View File

@ -1,82 +0,0 @@
From 2fab3b4956c5b2f83c1e1abffc1df39de2933d83 Mon Sep 17 00:00:00 2001
From: Luka Kovacic <luka.kovacic () sartura ! hr>
Date: Tue, 24 Aug 2021 12:44:36 +0000
Subject: [PATCH 5/7] Documentation/ABI: Add iei-wt61p803-puzzle driver sysfs
interface documentation
Add the iei-wt61p803-puzzle driver sysfs interface documentation to allow
monitoring and control of the microcontroller from user space.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Robert Marko <robert.marko@sartura.hr>
---
.../testing/sysfs-driver-iei-wt61p803-puzzle | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle
@@ -0,0 +1,61 @@
+What: /sys/bus/serial/devices/.../mac_address_*
+Date: September 2020
+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
+Description: (RW) Internal factory assigned MAC address values
+
+What: /sys/bus/serial/devices/.../serial_number
+Date: September 2020
+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
+Description: (RW) Internal factory assigned serial number
+
+What: /sys/bus/serial/devices/.../version
+Date: September 2020
+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
+Description: (RO) Internal MCU firmware version
+
+What: /sys/bus/serial/devices/.../protocol_version
+Date: September 2020
+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
+Description: (RO) Internal MCU communication protocol version
+
+What: /sys/bus/serial/devices/.../power_loss_recovery
+Date: September 2020
+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
+Description: (RW) Host platform power loss recovery settings
+ Value mapping: 0 - Always-On, 1 - Always-Off, 2 - Always-AC, 3 - Always-WA
+
+What: /sys/bus/serial/devices/.../bootloader_mode
+Date: September 2020
+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
+Description: (RO) Internal MCU bootloader mode status
+ Value mapping:
+ 0 - normal mode
+ 1 - bootloader mode
+
+What: /sys/bus/serial/devices/.../power_status
+Date: September 2020
+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
+Description: (RO) Power status indicates the host platform power on method.
+ Value mapping (bitwise list):
+ 0x80 - Null
+ 0x40 - Firmware flag
+ 0x20 - Power loss detection flag (powered off)
+ 0x10 - Power loss detection flag (AC mode)
+ 0x08 - Button power on
+ 0x04 - Wake-on-LAN power on
+ 0x02 - RTC alarm power on
+ 0x01 - AC recover power on
+
+What: /sys/bus/serial/devices/.../build_info
+Date: September 2020
+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
+Description: (RO) Internal MCU firmware build date
+ Format: yyyy/mm/dd hh:mm
+
+What: /sys/bus/serial/devices/.../ac_recovery_status
+Date: September 2020
+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
+Description: (RO) Host platform AC recovery status value
+ Value mapping:
+ 0 - board has not been recovered from power down
+ 1 - board has been recovered from power down

74
target/linux/mvebu/patches-6.1/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch
View File

@ -1,74 +0,0 @@
From 0aff3e5923fecc6842473ad07a688d6e2f2c2d55 Mon Sep 17 00:00:00 2001
From: Luka Kovacic <luka.kovacic () sartura ! hr>
Date: Tue, 24 Aug 2021 12:44:37 +0000
Subject: [PATCH 6/7] Documentation/hwmon: Add iei-wt61p803-puzzle hwmon driver
documentation
Add the iei-wt61p803-puzzle driver hwmon driver interface documentation.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Robert Marko <robert.marko@sartura.hr>
---
.../hwmon/iei-wt61p803-puzzle-hwmon.rst | 43 +++++++++++++++++++
Documentation/hwmon/index.rst | 1 +
2 files changed, 44 insertions(+)
create mode 100644 Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
--- /dev/null
+++ b/Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
@@ -0,0 +1,43 @@
+.. SPDX-License-Identifier: GPL-2.0-only
+
+Kernel driver iei-wt61p803-puzzle-hwmon
+=======================================
+
+Supported chips:
+ * IEI WT61P803 PUZZLE for IEI Puzzle M801
+
+ Prefix: 'iei-wt61p803-puzzle-hwmon'
+
+Author: Luka Kovacic <luka.kovacic@sartura.hr>
+
+
+Description
+-----------
+
+This driver adds fan and temperature sensor reading for some IEI Puzzle
+series boards.
+
+Sysfs attributes
+----------------
+
+The following attributes are supported:
+
+- IEI WT61P803 PUZZLE for IEI Puzzle M801
+
+/sys files in hwmon subsystem
+-----------------------------
+
+================= == =====================================================
+fan[1-5]_input RO files for fan speed (in RPM)
+pwm[1-2] RW files for fan[1-2] target duty cycle (0..255)
+temp[1-2]_input RO files for temperature sensors, in millidegree Celsius
+================= == =====================================================
+
+/sys files in thermal subsystem
+-------------------------------
+
+================= == =====================================================
+cur_state RW file for current cooling state of the cooling device
+ (0..max_state)
+max_state RO file for maximum cooling state of the cooling device
+================= == =====================================================
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -77,6 +77,7 @@ Hardware Monitoring Kernel Drivers
ibmaem
ibm-cffps
ibmpowernv
+ iei-wt61p803-puzzle-hwmon
ina209
ina2xx
ina238

41
target/linux/mvebu/patches-6.1/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch
View File

@ -1,41 +0,0 @@
From 12479baad28d2a08c6cb9e83471057635fa1635c Mon Sep 17 00:00:00 2001
From: Luka Kovacic <luka.kovacic () sartura ! hr>
Date: Tue, 24 Aug 2021 12:44:38 +0000
Subject: [PATCH 7/7] MAINTAINERS: Add an entry for the IEI WT61P803 PUZZLE
driver
Add an entry for the IEI WT61P803 PUZZLE driver (MFD, HWMON, LED drivers).
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Robert Marko <robert.marko@sartura.hr>
---
MAINTAINERS | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9900,6 +9900,22 @@ F: include/net/nl802154.h
F: net/ieee802154/
F: net/mac802154/
+IEI WT61P803 M801 MFD DRIVER
+M: Luka Kovacic <luka.kovacic@sartura.hr>
+M: Luka Perkov <luka.perkov@sartura.hr>
+M: Goran Medic <goran.medic@sartura.hr>
+L: linux-kernel@vger.kernel.org
+S: Maintained
+F: Documentation/ABI/stable/sysfs-driver-iei-wt61p803-puzzle
+F: Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
+F: Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
+F: Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
+F: Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
+F: drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
+F: drivers/leds/leds-iei-wt61p803-puzzle.c
+F: drivers/mfd/iei-wt61p803-puzzle.c
+F: include/linux/mfd/iei-wt61p803-puzzle.h
+
IFE PROTOCOL
M: Yotam Gigi <yotam.gi@gmail.com>
M: Jamal Hadi Salim <jhs@mojatatu.com>

271
target/linux/mvebu/patches-6.1/910-drivers-leds-wt61p803-puzzle-improvements.patch
View File

@ -1,271 +0,0 @@
--- a/drivers/leds/leds-iei-wt61p803-puzzle.c
+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c
@@ -9,9 +9,13 @@
#include <linux/mfd/iei-wt61p803-puzzle.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/slab.h>
+#include <linux/workqueue.h>
+
+#define IEI_LEDS_MAX 4
enum iei_wt61p803_puzzle_led_state {
IEI_LED_OFF = 0x30,
@@ -33,7 +37,11 @@ struct iei_wt61p803_puzzle_led {
struct iei_wt61p803_puzzle *mcu;
unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
struct mutex lock; /* mutex to protect led_power_state */
+ struct work_struct work;
int led_power_state;
+ int id;
+ u8 blinking;
+ bool active_low;
};
static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led
@@ -51,10 +59,18 @@ static int iei_wt61p803_puzzle_led_brigh
size_t reply_size;
int ret;
+ if (priv->blinking) {
+ if (brightness == LED_OFF)
+ priv->blinking = 0;
+ else
+ return 0;
+ }
+
led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
- led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;
- led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;
+ led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);
+ led_power_cmd[3] = ((brightness == LED_OFF) ^ priv->active_low) ?
+ IEI_LED_OFF : priv->blinking?priv->blinking:IEI_LED_ON;
ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,
sizeof(led_power_cmd),
@@ -90,39 +106,166 @@ static enum led_brightness iei_wt61p803_
return led_state;
}
+static void iei_wt61p803_puzzle_led_apply_blink(struct work_struct *work)
+{
+ struct iei_wt61p803_puzzle_led *priv = container_of(work, struct iei_wt61p803_puzzle_led, work);
+ unsigned char led_blink_cmd[5] = {};
+ unsigned char resp_buf[IEI_WT61P803_PUZZLE_BUF_SIZE];
+ size_t reply_size;
+
+ led_blink_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
+ led_blink_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
+ led_blink_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);
+ led_blink_cmd[3] = priv->blinking;
+
+ iei_wt61p803_puzzle_write_command(priv->mcu, led_blink_cmd,
+ sizeof(led_blink_cmd),
+ resp_buf,
+ &reply_size);
+
+ return;
+}
+
+static int iei_wt61p803_puzzle_led_set_blink(struct led_classdev *cdev,
+ unsigned long *delay_on,
+ unsigned long *delay_off)
+{
+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
+ u8 blink_mode = 0;
+ int ret = 0;
+
+ /* set defaults */
+ if (!*delay_on && !*delay_off) {
+ *delay_on = 500;
+ *delay_off = 500;
+ }
+
+ /* minimum delay for soft-driven blinking is 100ms to keep load low */
+ if (*delay_on < 100)
+ *delay_on = 100;
+
+ if (*delay_off < 100)
+ *delay_off = 100;
+
+ /* offload blinking to hardware, if possible */
+ if (*delay_on != *delay_off) {
+ ret = -EINVAL;
+ } else if (*delay_on == 100) {
+ blink_mode = IEI_LED_BLINK_5HZ;
+ *delay_on = 100;
+ *delay_off = 100;
+ } else if (*delay_on <= 500) {
+ blink_mode = IEI_LED_BLINK_1HZ;
+ *delay_on = 500;
+ *delay_off = 500;
+ } else {
+ ret = -EINVAL;
+ }
+
+ mutex_lock(&priv->lock);
+ priv->blinking = blink_mode;
+ mutex_unlock(&priv->lock);
+
+ if (blink_mode)
+ schedule_work(&priv->work);
+
+ return ret;
+}
+
+
+static int iei_wt61p803_puzzle_led_set_dt_default(struct led_classdev *cdev,
+ struct device_node *np)
+{
+ const char *state;
+ int ret = 0;
+
+ state = of_get_property(np, "default-state", NULL);
+ if (state) {
+ if (!strcmp(state, "on")) {
+ ret =
+ iei_wt61p803_puzzle_led_brightness_set_blocking(
+ cdev, cdev->max_brightness);
+ } else {
+ ret = iei_wt61p803_puzzle_led_brightness_set_blocking(
+ cdev, LED_OFF);
+ }
+ }
+
+ return ret;
+}
+
static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ struct device_node *np = dev_of_node(dev);
+ struct device_node *child;
struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
struct iei_wt61p803_puzzle_led *priv;
- struct led_init_data init_data = {};
- struct fwnode_handle *child;
int ret;
+ u32 reg;
- if (device_get_child_node_count(dev) != 1)
+ if (device_get_child_node_count(dev) > IEI_LEDS_MAX)
return -EINVAL;
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
-
- priv->mcu = mcu;
- priv->led_power_state = 1;
- mutex_init(&priv->lock);
- dev_set_drvdata(dev, priv);
-
- child = device_get_next_child_node(dev, NULL);
- init_data.fwnode = child;
-
- priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
- priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
- priv->cdev.max_brightness = 1;
+ for_each_available_child_of_node(np, child) {
+ struct led_init_data init_data = {};
- ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
- if (ret)
- dev_err(dev, "Could not register LED\n");
+ ret = of_property_read_u32(child, "reg", &reg);
+ if (ret) {
+ dev_err(dev, "Failed to read led 'reg' property\n");
+ goto put_child_node;
+ }
+
+ if (reg > IEI_LEDS_MAX) {
+ dev_err(dev, "Invalid led reg %u\n", reg);
+ ret = -EINVAL;
+ goto put_child_node;
+ }
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ ret = -ENOMEM;
+ goto put_child_node;
+ }
+
+ mutex_init(&priv->lock);
+
+ dev_set_drvdata(dev, priv);
+
+ if (of_property_read_bool(child, "active-low"))
+ priv->active_low = true;
+
+ priv->mcu = mcu;
+ priv->id = reg;
+ priv->led_power_state = 1;
+ priv->blinking = 0;
+ init_data.fwnode = of_fwnode_handle(child);
+
+ priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
+ priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
+ priv->cdev.blink_set = iei_wt61p803_puzzle_led_set_blink;
+
+ priv->cdev.max_brightness = 1;
+
+ INIT_WORK(&priv->work, iei_wt61p803_puzzle_led_apply_blink);
+
+ ret = iei_wt61p803_puzzle_led_set_dt_default(&priv->cdev, child);
+ if (ret) {
+ dev_err(dev, "Could apply default from DT\n");
+ goto put_child_node;
+ }
+
+ ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
+ if (ret) {
+ dev_err(dev, "Could not register LED\n");
+ goto put_child_node;
+ }
+ }
+
+ return ret;
- fwnode_handle_put(child);
+put_child_node:
+ of_node_put(child);
return ret;
}
--- a/include/linux/mfd/iei-wt61p803-puzzle.h
+++ b/include/linux/mfd/iei-wt61p803-puzzle.h
@@ -36,7 +36,7 @@
#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */
#define IEI_WT61P803_PUZZLE_CMD_LED 0x52 /* R */
-#define IEI_WT61P803_PUZZLE_CMD_LED_POWER 0x31 /* 1 */
+#define IEI_WT61P803_PUZZLE_CMD_LED_SET(n) (0x30 | (n))
#define IEI_WT61P803_PUZZLE_CMD_TEMP 0x54 /* T */
#define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL 0x41 /* A */
--- a/drivers/mfd/iei-wt61p803-puzzle.c
+++ b/drivers/mfd/iei-wt61p803-puzzle.c
@@ -176,6 +176,9 @@ static int iei_wt61p803_puzzle_recv_buf(
struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev);
int ret;
+ print_hex_dump_debug("puzzle-mcu rx: ", DUMP_PREFIX_NONE,
+ 16, 1, data, size, false);
+
ret = iei_wt61p803_puzzle_process_resp(mcu, data, size);
/* Return the number of processed bytes if function returns error,
* discard the remaining incoming data, since the frame this data
@@ -246,6 +249,9 @@ int iei_wt61p803_puzzle_write_command(st
cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1);
+ print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE,
+ 16, 1, cmd, size, false);
+
/* Initialize reply struct */
reinit_completion(&mcu->reply->received);
mcu->reply->size = 0;

63
target/linux/mvebu/patches-6.1/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch
View File

@ -1,63 +0,0 @@
--- a/drivers/mfd/iei-wt61p803-puzzle.c
+++ b/drivers/mfd/iei-wt61p803-puzzle.c
@@ -241,6 +241,7 @@ int iei_wt61p803_puzzle_write_command(st
{
struct device *dev = &mcu->serdev->dev;
int ret;
+ int retries;
if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH)
return -EINVAL;
@@ -252,24 +253,36 @@ int iei_wt61p803_puzzle_write_command(st
print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE,
16, 1, cmd, size, false);
+ retries = 3;
/* Initialize reply struct */
- reinit_completion(&mcu->reply->received);
- mcu->reply->size = 0;
- usleep_range(2000, 10000);
- serdev_device_write_flush(mcu->serdev);
- ret = serdev_device_write_buf(mcu->serdev, cmd, size);
- if (ret < 0)
- goto exit;
-
- serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
- ret = wait_for_completion_timeout(&mcu->reply->received,
- IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
- if (ret == 0) {
- dev_err(dev, "Command reply receive timeout\n");
- ret = -ETIMEDOUT;
- goto exit;
+ while (retries) {
+ reinit_completion(&mcu->reply->received);
+ mcu->reply->size = 0;
+ usleep_range(2000, 10000);
+ serdev_device_write_flush(mcu->serdev);
+ ret = serdev_device_write_buf(mcu->serdev, cmd, size);
+ if (ret < 0)
+ goto exit;
+
+ serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
+ ret = wait_for_completion_timeout(&mcu->reply->received,
+ IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
+ retries--;
+ if (ret == 0) {
+ if (retries == 0) {
+ dev_err(dev, "Command reply receive timeout\n");
+ ret = -ETIMEDOUT;
+ goto exit;
+ }
+ }
+ else {
+ if (mcu->reply->data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
+ mcu->reply->data[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
+ mcu->reply->data[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK) {
+ break;
+ }
+ }
}
-
*reply_size = mcu->reply->size;
/* Copy the received data, as it will not be available after a new frame is received */
memcpy(reply_data, mcu->reply->data, mcu->reply->size);