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realtek: switch RTL838X/RTL839X DT to new clock driver

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Use new DT clockdriver syntax for RTL838X/RTL839X targets. To make it work
we need to change some nodes:
- define the external oscillator speed (25MHz)
- define SRAM
- add clock controller
- Add second CPU for RTL839X
- map all devices to new clocks
- Remove dummy LXB clock
- add CPU OPP table

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This commit is contained in:
Markus Stockhausen 2022-08-25 08:24:13 +02:00 committed by Sander Vanheule
parent 7c18aab6e0
commit 48f3746fe5
2 changed files with 141 additions and 20 deletions
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68
target/linux/realtek/dts-5.10/rtl838x.dtsi
View File

@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/clock/rtl83xx-clk.h>
/dts-v1/;
#define STRINGIZE(s) #s
@ -60,14 +62,58 @@
compatible = "realtek,rtl838x-soc";
osc: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
ccu: clock-controller {
compatible = "realtek,rtl8380-clock";
#clock-cells = <1>;
clocks = <&osc>;
clock-names = "ref_clk";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
frequency = <500000000>;
cpu@0 {
compatible = "mips,mips4KEc";
reg = <0>;
clocks = <&ccu CLK_CPU>;
operating-points-v2 = <&cpu_opp_table>;
};
};
cpu_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <325000000>;
};
opp01 {
opp-hz = /bits/ 64 <350000000>;
};
opp02 {
opp-hz = /bits/ 64 <375000000>;
};
opp03 {
opp-hz = /bits/ 64 <400000000>;
};
opp04 {
opp-hz = /bits/ 64 <425000000>;
};
opp05 {
opp-hz = /bits/ 64 <450000000>;
};
opp06 {
opp-hz = /bits/ 64 <475000000>;
};
opp07 {
opp-hz = /bits/ 64 <500000000>;
};
};
@ -75,12 +121,6 @@
bootargs = "console=ttyS0,115200";
};
lx_clk: lx_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
cpuintc: cpuintc {
compatible = "mti,cpu-interrupt-controller";
#address-cells = <0>;
@ -116,7 +156,7 @@
compatible = "ns16550a";
reg = <0x2000 0x100>;
clocks = <&lx_clk>;
clocks = <&ccu CLK_LXB>;
interrupt-parent = <&intc>;
interrupts = <31 1>;
@ -134,7 +174,7 @@
compatible = "ns16550a";
reg = <0x2100 0x100>;
clocks = <&lx_clk>;
clocks = <&ccu CLK_LXB>;
interrupt-parent = <&intc>;
interrupts = <30 0>;
@ -153,7 +193,7 @@
realtek,reset-mode = "soc";
clocks = <&lx_clk>;
clocks = <&ccu CLK_LXB>;
timeout-sec = <30>;
interrupt-parent = <&intc>;
@ -220,6 +260,14 @@
};
};
sram0: sram@9f000000 {
compatible = "mmio-sram";
reg = <0x9f000000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x9f000000 0x10000>;
};
switch0: switch@1b000000 {
compatible = "realtek,rtl83xx-switch";

93
target/linux/realtek/dts-5.10/rtl839x.dtsi
View File

@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/clock/rtl83xx-clk.h>
/dts-v1/;
#define STRINGIZE(s) #s
@ -53,14 +55,83 @@
compatible = "realtek,rtl839x-soc";
osc: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
ccu: clock-controller {
compatible = "realtek,rtl8390-clock";
#clock-cells = <1>;
clocks = <&osc>;
clock-names = "ref_clk";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
frequency = <700000000>;
cpu@0 {
compatible = "mips,mips34Kc";
reg = <0>;
clocks = <&ccu CLK_CPU>;
operating-points-v2 = <&cpu_opp_table>;
};
cpu@1 {
compatible = "mips,mips34Kc";
reg = <1>;
clocks = <&ccu CLK_CPU>;
operating-points-v2 = <&cpu_opp_table>;
};
};
cpu_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <425000000>;
};
opp01 {
opp-hz = /bits/ 64 <450000000>;
};
opp02 {
opp-hz = /bits/ 64 <475000000>;
};
opp03 {
opp-hz = /bits/ 64 <500000000>;
};
opp04 {
opp-hz = /bits/ 64 <525000000>;
};
opp05 {
opp-hz = /bits/ 64 <550000000>;
};
opp06 {
opp-hz = /bits/ 64 <575000000>;
};
opp07 {
opp-hz = /bits/ 64 <600000000>;
};
opp08 {
opp-hz = /bits/ 64 <625000000>;
};
opp09 {
opp-hz = /bits/ 64 <650000000>;
};
opp10 {
opp-hz = /bits/ 64 <675000000>;
};
opp11 {
opp-hz = /bits/ 64 <700000000>;
};
opp12 {
opp-hz = /bits/ 64 <725000000>;
};
opp13 {
opp-hz = /bits/ 64 <750000000>;
};
};
@ -68,12 +139,6 @@
bootargs = "console=ttyS0,115200";
};
lx_clk: lx_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
cpuintc: cpuintc {
compatible = "mti,cpu-interrupt-controller";
#address-cells = <0>;
@ -109,7 +174,7 @@
compatible = "ns16550a";
reg = <0x2000 0x100>;
clocks = <&lx_clk>;
clocks = <&ccu CLK_LXB>;
interrupt-parent = <&intc>;
interrupts = <31 1>;
@ -127,7 +192,7 @@
compatible = "ns16550a";
reg = <0x2100 0x100>;
clocks = <&lx_clk>;
clocks = <&ccu CLK_LXB>;
interrupt-parent = <&intc>;
interrupts = <30 2>;
@ -160,7 +225,7 @@
realtek,reset-mode = "soc";
clocks = <&lx_clk>;
clocks = <&ccu CLK_LXB>;
timeout-sec = <30>;
interrupt-parent = <&intc>;
@ -215,6 +280,14 @@
};
};
sram0: sram@9f000000 {
compatible = "mmio-sram";
reg = <0x9f000000 0x18000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x9f000000 0x18000>;
};
switch0: switch@1b000000 {
status = "okay";
compatible = "realtek,rtl83xx-switch";