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realtek: update the tree to the latest refactored version

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* rename the target to realtek
* add refactored DSA driver
* add latest gpio driver
* lots of arch cleanups
* new irq driver
* additional boards

Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin 2020-11-26 12:02:21 +01:00
parent 4e39949dd1
commit 2b88563ee5
62 changed files with 4571 additions and 4255 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target/linux/rtl838x/Makefile → target/linux/realtek/Makefile
View File

@ -5,7 +5,7 @@ include $(TOPDIR)/rules.mk
ARCH:=mips
CPU_TYPE:=4kec
BOARD:=rtl838x
BOARD:=realtek
BOARDNAME:=Realtek MIPS
DEVICE_TYPE:=basic
FEATURES:=ramdisk squashfs
@ -14,7 +14,7 @@ SUBTARGETS:=generic
KERNEL_PATCHVER:=5.4
define Target/Description
Build firmware images for Realtek RTL838x based boards.
Build firmware images for Realtek RTL83xx based boards.
endef
include $(INCLUDE_DIR)/target.mk

0
target/linux/rtl838x/base-files/etc/board.d/01_leds → target/linux/realtek/base-files/etc/board.d/01_leds
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4
target/linux/rtl838x/base-files/etc/board.d/02_network → target/linux/realtek/base-files/etc/board.d/02_network
View File

@ -11,6 +11,7 @@ rtl838x_setup_switch()
for lan in /sys/class/net/lan*; do
lan_list="$lan_list $(basename $lan)"
done
ucidef_set_bridge_device switch
ucidef_set_interface_lan "$lan_list"
}
@ -22,7 +23,8 @@ rtl838x_setup_macs()
local label_mac
case $board in
allnet,all-sg8208m)
allnet,all-sg8208m|\
netgear,gs110tpp-v1)
lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)
label_mac=$lan_mac
esac

0
target/linux/rtl838x/base-files/etc/inittab → target/linux/realtek/base-files/etc/inittab
View File

0
target/linux/rtl838x/base-files/lib/upgrade/platform.sh → target/linux/realtek/base-files/lib/upgrade/platform.sh
View File

66
target/linux/rtl838x/config-5.4 → target/linux/realtek/config-5.4
View File

@ -1,28 +1,13 @@
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_CEVT_R4K=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
@ -51,6 +36,7 @@ CONFIG_DMA_NONCOHERENT=y
CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
CONFIG_EARLY_PRINTK_8250=y
CONFIG_EFI_EARLYCON=y
CONFIG_ETHERNET_PACKET_MANGLE=y
CONFIG_EXTRA_FIRMWARE="rtl838x_phy/rtl838x_8214fc.fw rtl838x_phy/rtl838x_8218b.fw rtl838x_phy/rtl838x_8380.fw"
@ -68,7 +54,6 @@ CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_LIB_ASHLDI3=y
CONFIG_GENERIC_LIB_ASHRDI3=y
@ -77,10 +62,14 @@ CONFIG_GENERIC_LIB_LSHRDI3=y
CONFIG_GENERIC_LIB_UCMPDI2=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_RTL8231=y
CONFIG_GPIO_RTL838X=y
CONFIG_GRO_CELLS=y
CONFIG_HANDLE_DOMAIN_IRQ=y
@ -88,41 +77,6 @@ CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_CBPF_JIT=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_COPY_THREAD_TLS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_HZ=250
CONFIG_HZ_250=y
@ -130,7 +84,6 @@ CONFIG_HZ_PERIODIC=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MIPS_CPU=y
CONFIG_IRQ_WORK=y
@ -155,11 +108,9 @@ CONFIG_MIPS_CLOCK_VSYSCALL=y
CONFIG_MIPS_CMDLINE_FROM_DTB=y
# CONFIG_MIPS_ELF_APPENDED_DTB is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_NO_APPENDED_DTB is not set
CONFIG_MIPS_RAW_APPENDED_DTB=y
CONFIG_MIPS_SPRAM=y
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
@ -175,7 +126,7 @@ CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_RTL838X=y
CONFIG_NET_DSA_RTL83XX=y
CONFIG_NET_DSA_TAG_TRAILER=y
CONFIG_NET_RTL838X=y
CONFIG_NET_SWITCHDEV=y
@ -196,7 +147,6 @@ CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_PSB6970_PHY=y
@ -211,7 +161,6 @@ CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_RTL838X=y
CONFIG_SRCU=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_SWCONFIG=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
@ -222,11 +171,10 @@ CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
CONFIG_SYS_SUPPORTS_VPE_LOADER=y
CONFIG_TARGET_ISA_REV=2
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TINY_SRCU=y
CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y
CONFIG_USE_OF=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

226
target/linux/realtek/dts/rtl8380_netgear_gs110tpp-v1.dts Normal file
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@ -0,0 +1,226 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
#include "rtl838x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "netgear,gs110tpp-v1", "realtek,rtl838x-soc";
model = "Netgear GS110TPP";
chosen {
bootargs = "console=ttyS0,115200";
};
keys {
compatible = "gpio-keys-polled";
poll-interval = <20>;
mode {
label = "reset";
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&gpio0 {
indirect-access-bus-id = <0>;
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x0e0000>;
read-only;
};
partition@e0000 {
label = "u-boot-env";
reg = <0x00e0000 0x010000>;
};
partition@f0000 {
label = "sysinfo";
reg = <0x00f0000 0x010000>;
read-only;
};
partition@100000{
label = "jffs2_cfg";
reg = <0x0100000 0x100000>;
read-only;
};
partition@200000{
label = "jffs2_log";
reg = <0x0200000 0x100000>;
};
partition@300000{
label = "firmware";
compatible = "netgear,uimage";
reg = <0x0300000 0x1d00000>;
};
};
};
};
&ethernet0 {
mdio: mdio-bus {
compatible = "realtek,rtl838x-mdio";
regmap = <&ethernet0>;
#address-cells = <1>;
#size-cells = <0>;
/* Internal phy */
phy8: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <8>;
};
phy9: ethernet-phy@9 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <9>;
};
phy10: ethernet-phy@10 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <10>;
};
phy11: ethernet-phy@11 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <11>;
};
phy12: ethernet-phy@12 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <12>;
};
phy13: ethernet-phy@13 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <13>;
};
phy14: ethernet-phy@14 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <14>;
};
phy15: ethernet-phy@15 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <15>;
};
/* phy10: ethernet-phy@10 {
compatible = "ethernet-phy-ieee802.3-c22";
phy-is-integrated;
reg = <10>;
};
phy11: ethernet-phy@11 {
compatible = "ethernet-phy-ieee802.3-c22";
phy-is-integrated;
reg = <11>;
};
phy12: ethernet-phy@12 {
compatible = "ethernet-phy-ieee802.3-c22";
phy-is-integrated;
reg = <12>;
};
phy13: ethernet-phy@13 {
compatible = "ethernet-phy-ieee802.3-c22";
phy-is-integrated;
reg = <13>;
};*/
};
};
&switch0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@8 {
reg = <8>;
label = "lan1";
phy-handle = <&phy8>;
phy-mode = "internal";
};
port@9 {
reg = <9>;
label = "lan2";
phy-handle = <&phy9>;
phy-mode = "internal";
};
port@10 {
reg = <10>;
label = "lan3";
phy-handle = <&phy10>;
phy-mode = "internal";
};
port@11 {
reg = <11>;
label = "lan4";
phy-handle = <&phy11>;
phy-mode = "internal";
};
port@12 {
reg = <12>;
label = "lan5";
phy-handle = <&phy12>;
phy-mode = "internal";
};
port@13 {
reg = <13>;
label = "lan6";
phy-handle = <&phy13>;
phy-mode = "internal";
};
port@14 {
reg = <14>;
label = "lan7";
phy-handle = <&phy14>;
phy-mode = "internal";
};
port@15 {
reg = <15>;
label = "lan8";
phy-handle = <&phy15>;
phy-mode = "internal";
};
/* port@10 {
reg = <10>;
label = "lan9";
phy-mode = "internal";
phy-handle = <&phy10>;
};
port@11 {
reg = <11>;
label = "lan10";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@12 {
reg = <12>;
label = "lan11";
phy-mode = "internal";
phy-handle = <&phy12>;
};
port@13 {
reg = <13>;
label = "lan12";
phy-mode = "internal";
phy-handle = <&phy13>;
};*/
port@28 {
ethernet = <&ethernet0>;
reg = <28>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};

0
target/linux/rtl838x/dts/rtl8382_allnet_all-sg8208m.dts → target/linux/realtek/dts/rtl8382_allnet_all-sg8208m.dts
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0
target/linux/rtl838x/dts/rtl8382_d-link_dgs-1210-10p.dts → target/linux/realtek/dts/rtl8382_d-link_dgs-1210-10p.dts
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0
target/linux/rtl838x/dts/rtl8382_d-link_dgs-1210-16.dts → target/linux/realtek/dts/rtl8382_d-link_dgs-1210-16.dts
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0
target/linux/rtl838x/dts/rtl8382_d-link_dgs-1210-28.dts → target/linux/realtek/dts/rtl8382_d-link_dgs-1210-28.dts
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0
target/linux/rtl838x/dts/rtl8382_d-link_dgs-1210.dtsi → target/linux/realtek/dts/rtl8382_d-link_dgs-1210.dtsi
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50
target/linux/rtl838x/dts/rtl838x.dtsi → target/linux/realtek/dts/rtl838x.dtsi
View File

@ -65,7 +65,14 @@
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "rtl838x,icu";
compatible = "mti,cpu-interrupt-controller";
};
intc: rtlintc {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "realtek,rt8380-intc";
reg = <0xb8003000 0x20>;
};
@ -80,7 +87,7 @@
};
uart0: uart@b8002000 {
status = "disabled";
status = "okay";
compatible = "ns16550a";
reg = <0xb8002000 0x100>;
@ -88,7 +95,7 @@
clock-frequency = <200000000>;
interrupt-parent = <&cpuintc>;
interrupts = <31>;
interrupts = <3>;
reg-io-width = <1>;
reg-shift = <2>;
@ -97,6 +104,9 @@
};
uart1: uart@b8002100 {
pinctrl-names = "default";
pinctrl-0 = <&enable_uart1>;
status = "okay";
compatible = "ns16550a";
@ -104,7 +114,7 @@
clock-frequency = <200000000>;
interrupt-parent = <&cpuintc>;
interrupt-parent = <&intc>;
interrupts = <30>;
reg-io-width = <1>;
@ -118,16 +128,38 @@
reg = <0xb8003500 0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&cpuintc>;
interrupt-parent = <&intc>;
interrupts = <23>;
};
gpio1: rtl8231-gpio {
status = "disabled";
compatible = "realtek,rtl8231-gpio";
#gpio-cells = <2>;
indirect-access-bus-id = <0>;
gpio-controller;
};
pinmux: pinmux@bb001000 {
compatible = "pinctrl-single";
reg = <0xbb001000 0x4>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x1>;
#pinctrl-cells = <2>;
enable_uart1: pinmux_enable_uart1 {
pinctrl-single,bits = <0x0 0x10 0x10>;
};
};
ethernet0: ethernet@bb00a300 {
status = "okay";
compatible = "realtek,rtl838x-eth";
reg = <0xbb00a300 0x100>;
interrupt-parent = <&cpuintc>;
interrupt-parent = <&intc>;
interrupts = <24>;
#interrupt-cells = <1>;
phy-mode = "internal";
@ -141,6 +173,10 @@
switch0: switch@bb000000 {
status = "okay";
compatible = "realtek,rtl838x-switch";
interrupt-parent = <&cpuintc>;
interrupts = <4>;
compatible = "realtek,rtl83xx-switch";
};
};

0
target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h → target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h
View File

66
target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h Normal file
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@ -0,0 +1,66 @@
// SPDX-License-Identifier: GPL-2.0-only
#ifndef _RTL83XX_IRQ_H_
#define _RTL83XX_IRQ_H_
#define NR_IRQS 32
#include_next <irq.h>
/* Global Interrupt Mask Register */
#define RTL83XX_ICTL_GIMR 0x00
/* Global Interrupt Status Register */
#define RTL83XX_ICTL_GISR 0x04
#define RTL83XX_IRQ_CPU_BASE 0
#define RTL83XX_IRQ_CPU_NUM 8
#define RTL83XX_IRQ_ICTL_BASE (RTL83XX_IRQ_CPU_BASE + RTL83XX_IRQ_CPU_NUM)
#define RTL83XX_IRQ_ICTL_NUM 32
/* Cascaded interrupts */
#define RTL83XX_ICTL1_IRQ (RTL83XX_IRQ_CPU_BASE + 2)
#define RTL83XX_ICTL2_IRQ (RTL83XX_IRQ_CPU_BASE + 3)
#define RTL83XX_ICTL3_IRQ (RTL83XX_IRQ_CPU_BASE + 4)
#define RTL83XX_ICTL4_IRQ (RTL83XX_IRQ_CPU_BASE + 5)
#define RTL83XX_ICTL5_IRQ (RTL83XX_IRQ_CPU_BASE + 6)
/* Interrupt routing register */
#define RTL83XX_IRR0 0x08
#define RTL83XX_IRR1 0x0c
#define RTL83XX_IRR2 0x10
#define RTL83XX_IRR3 0x14
/* Cascade map */
#define UART0_CASCADE 2
#define UART1_CASCADE 1
#define TC0_CASCADE 5
#define TC1_CASCADE 1
#define OCPTO_CASCADE 1
#define HLXTO_CASCADE 1
#define SLXTO_CASCADE 1
#define NIC_CASCADE 4
#define GPIO_ABCD_CASCADE 4
#define GPIO_EFGH_CASCADE 4
#define RTC_CASCADE 4
#define SWCORE_CASCADE 3
#define WDT_IP1_CASCADE 4
#define WDT_IP2_CASCADE 5
/* Pack cascade map into interrupt routing registers */
#define RTL83XX_IRR0_SETTING (\
(UART0_CASCADE << 28) | \
(UART1_CASCADE << 24) | \
(TC0_CASCADE << 20) | \
(TC1_CASCADE << 16) | \
(OCPTO_CASCADE << 12) | \
(HLXTO_CASCADE << 8) | \
(SLXTO_CASCADE << 4) | \
(NIC_CASCADE << 0))
#define RTL83XX_IRR1_SETTING (\
(GPIO_ABCD_CASCADE << 28) | \
(GPIO_EFGH_CASCADE << 24) | \
(RTC_CASCADE << 20) | \
(SWCORE_CASCADE << 16))
#define RTL83XX_IRR2_SETTING 0
#define RTL83XX_IRR3_SETTING 0
#endif /* _RTL83XX_IRQ_H_ */

77
target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h → target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h
View File

@ -6,29 +6,30 @@
#ifndef _MACH_RTL838X_H_
#define _MACH_RTL838X_H_
#include <asm/types.h>
/*
* Register access macros
*/
#define RTL838X_SW_BASE ((volatile void *) 0xBB000000)
#define rtl838x_r32(reg) __raw_readl(reg)
#define rtl838x_w32(val, reg) __raw_writel(val, reg)
#define rtl838x_w32_mask(clear, set, reg) rtl838x_w32((rtl838x_r32(reg) & ~(clear)) | (set), reg)
#define rtl83xx_r32(reg) readl(reg)
#define rtl83xx_w32(val, reg) writel(val, reg)
#define rtl83xx_w32_mask(clear, set, reg) rtl83xx_w32((rtl83xx_r32(reg) & ~(clear)) | (set), reg)
#define rtl838x_r8(reg) __raw_readb(reg)
#define rtl838x_w8(val, reg) __raw_writeb(val, reg)
#define rtl83xx_r8(reg) readb(reg)
#define rtl83xx_w8(val, reg) writeb(val, reg)
#define sw_r32(reg) __raw_readl(RTL838X_SW_BASE + reg)
#define sw_w32(val, reg) __raw_writel(val, RTL838X_SW_BASE + reg)
#define sw_r32(reg) readl(RTL838X_SW_BASE + reg)
#define sw_w32(val, reg) writel(val, RTL838X_SW_BASE + reg)
#define sw_w32_mask(clear, set, reg) \
sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
#define sw_r64(reg) ((((u64)__raw_readl(RTL838X_SW_BASE + reg)) << 32) | \
__raw_readl(RTL838X_SW_BASE + reg + 4))
#define sw_r64(reg) ((((u64)readl(RTL838X_SW_BASE + reg)) << 32) | \
readl(RTL838X_SW_BASE + reg + 4))
#define sw_w64(val, reg) do { \
__raw_writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
__raw_writel((u32)((val) & 0xffffffff), \
writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
writel((u32)((val) & 0xffffffff), \
RTL838X_SW_BASE + reg + 4); \
} while (0)
@ -46,6 +47,22 @@
#define RTL838X_IRQ_ICTL_BASE (RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)
#define RTL838X_IRQ_ICTL_NUM 32
#define RTL83XX_IRQ_UART0 31
#define RTL83XX_IRQ_UART1 30
#define RTL83XX_IRQ_TC0 29
#define RTL83XX_IRQ_TC1 28
#define RTL83XX_IRQ_OCPTO 27
#define RTL83XX_IRQ_HLXTO 26
#define RTL83XX_IRQ_SLXTO 25
#define RTL83XX_IRQ_NIC 24
#define RTL83XX_IRQ_GPIO_ABCD 23
#define RTL83XX_IRQ_GPIO_EFGH 22
#define RTL83XX_IRQ_RTC 21
#define RTL83XX_IRQ_SWCORE 20
#define RTL83XX_IRQ_WDT_IP1 19
#define RTL83XX_IRQ_WDT_IP2 18
/*
* MIPS32R2 counter
*/
@ -103,7 +120,6 @@
)
#define IRR1 (0x0c)
#define IRR1_SETTING_RTL838X ((GPIO_ABCD_RS << 28) | \
(GPIO_EFGH_RS << 24) | \
(RTC_RS << 20) | \
@ -113,7 +129,6 @@
(SWCORE_RS << 16) \
)
#define IRR2 (0x10)
#define IRR2_SETTING 0
@ -315,16 +330,13 @@
#define RTL839X_MODEL_NAME_INFO (0x0FF0)
#define RTL838X_LED_GLB_CTRL (0xA000)
#define RTL839X_LED_GLB_CTRL (0x00E4)
#define RTL838X_EXT_GPIO_DIR_0 (0xA08C)
#define RTL838X_EXT_GPIO_DIR_1 (0xA090)
#define RTL838X_EXT_GPIO_DATA_0 (0xA094)
#define RTL838X_EXT_GPIO_DATA_1 (0xA098)
#define RTL838X_EXT_GPIO_DIR (0xA08C)
#define RTL839X_EXT_GPIO_DIR (0x0214)
#define RTL838X_EXT_GPIO_DATA (0xA094)
#define RTL839X_EXT_GPIO_DATA (0x021c)
#define RTL838X_EXT_GPIO_INDRT_ACCESS (0xA09C)
#define RTL839X_EXT_GPIO_INDRT_ACCESS (0x0224)
#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0)
#define RTL838X_EXTRA_GPIO_DIR_0 (0xA0E4)
#define RTL838X_EXTRA_GPIO_DIR_1 (0xA0E8)
#define RTL838X_EXTRA_GPIO_DATA_0 (0xA0EC)
#define RTL838X_EXTRA_GPIO_DATA_1 (0xA0F0)
#define RTL838X_DMY_REG5 (0x0144)
#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0)
@ -374,11 +386,18 @@
#define RTL838X_LED_P_EN_CTRL (0xA008)
/* LED control by software */
#define RTL838X_LED_SW_CTRL (0xA00C)
#define RTL838X_LED_SW_CTRL (0x0128)
#define RTL839X_LED_SW_CTRL (0xA00C)
#define RTL838X_LED_SW_P_EN_CTRL (0xA010)
#define RTL839X_LED_SW_P_EN_CTRL (0x012C)
#define RTL838X_LED0_SW_P_EN_CTRL (0xA010)
#define RTL839X_LED0_SW_P_EN_CTRL (0x012C)
#define RTL838X_LED1_SW_P_EN_CTRL (0xA014)
#define RTL839X_LED1_SW_P_EN_CTRL (0x0130)
#define RTL838X_LED2_SW_P_EN_CTRL (0xA018)
#define RTL838X_LED_SW_P_CTRL(p) (0xA01C + ((p) << 2))
#define RTL839X_LED2_SW_P_EN_CTRL (0x0134)
#define RTL838X_LED_SW_P_CTRL (0xA01C)
#define RTL839X_LED_SW_P_CTRL (0x0144)
#define RTL839X_MAC_EFUSE_CTRL (0x02ac)
@ -420,7 +439,7 @@
#define RTL8380_FAMILY_ID (0x8380)
#define RTL8330_FAMILY_ID (0x8330)
struct rtl838x_soc_info {
struct rtl83xx_soc_info {
unsigned char *name;
unsigned int id;
unsigned int family;
@ -429,9 +448,11 @@ struct rtl838x_soc_info {
volatile void *icu_base;
};
extern struct rtl838x_soc_info soc_info;
extern struct mutex smi_lock;
void rtl838x_soc_detect(struct rtl838x_soc_info *i);
/* rtl83xx-related functions used across subsystems */
int rtl838x_smi_wait_op(int timeout);
int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
#endif /* _MACH_RTL838X_H_ */

2
target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Makefile → target/linux/realtek/files-5.4/arch/mips/rtl838x/Makefile
View File

@ -2,4 +2,4 @@
# Makefile for the rtl838x specific parts of the kernel
#
obj-y := serial.o setup.o prom.o irq.o
obj-y := setup.o prom.o irq.o

0
target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Platform → target/linux/realtek/files-5.4/arch/mips/rtl838x/Platform
View File

167
target/linux/realtek/files-5.4/arch/mips/rtl838x/irq.c Normal file
View File

@ -0,0 +1,167 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Realtek RTL83XX architecture specific IRQ handling
*
* based on the original BSP
* Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
* Copyright (C) 2020 B. Koblitz
* Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
* Copyright (C) 2020 John Crispin <john@phrozen.org>
*/
#include <linux/irqchip.h>
#include <linux/spinlock.h>
#include <linux/of_address.h>
#include <asm/irq_cpu.h>
#include <linux/of_irq.h>
#include <asm/cevt-r4k.h>
#include <mach-rtl83xx.h>
#include "irq.h"
#define REALTEK_CPU_IRQ_SHARED0 (MIPS_CPU_IRQ_BASE + 2)
#define REALTEK_CPU_IRQ_UART (MIPS_CPU_IRQ_BASE + 3)
#define REALTEK_CPU_IRQ_SWITCH (MIPS_CPU_IRQ_BASE + 4)
#define REALTEK_CPU_IRQ_SHARED1 (MIPS_CPU_IRQ_BASE + 5)
#define REALTEK_CPU_IRQ_EXTERNAL (MIPS_CPU_IRQ_BASE + 6)
#define REALTEK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
#define REG(x) (rtl83xx_ictl_base + x)
extern struct rtl83xx_soc_info soc_info;
static DEFINE_RAW_SPINLOCK(irq_lock);
static void __iomem *rtl83xx_ictl_base;
static void rtl83xx_ictl_enable_irq(struct irq_data *i)
{
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&irq_lock, flags);
value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
value |= BIT(i->hwirq);
rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
raw_spin_unlock_irqrestore(&irq_lock, flags);
}
static void rtl83xx_ictl_disable_irq(struct irq_data *i)
{
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&irq_lock, flags);
value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
value &= ~BIT(i->hwirq);
rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
raw_spin_unlock_irqrestore(&irq_lock, flags);
}
static struct irq_chip rtl83xx_ictl_irq = {
.name = "RTL83xx",
.irq_enable = rtl83xx_ictl_enable_irq,
.irq_disable = rtl83xx_ictl_disable_irq,
.irq_ack = rtl83xx_ictl_disable_irq,
.irq_mask = rtl83xx_ictl_disable_irq,
.irq_unmask = rtl83xx_ictl_enable_irq,
.irq_eoi = rtl83xx_ictl_enable_irq,
};
static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
{
irq_set_chip_and_handler(hw, &rtl83xx_ictl_irq, handle_level_irq);
return 0;
}
static const struct irq_domain_ops irq_domain_ops = {
.map = intc_map,
.xlate = irq_domain_xlate_onecell,
};
static void rtl838x_irq_dispatch(struct irq_desc *desc)
{
unsigned int pending = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR)) & rtl83xx_r32(REG(RTL83XX_ICTL_GISR));
if (pending) {
struct irq_domain *domain = irq_desc_get_handler_data(desc);
generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
} else {
spurious_interrupt();
}
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending;
pending = read_c0_cause() & read_c0_status() & ST0_IM;
if (pending & CAUSEF_IP7)
do_IRQ(REALTEK_CPU_IRQ_COUNTER);
else if (pending & CAUSEF_IP6)
do_IRQ(REALTEK_CPU_IRQ_EXTERNAL);
else if (pending & CAUSEF_IP5)
do_IRQ(REALTEK_CPU_IRQ_SHARED1);
else if (pending & CAUSEF_IP4)
do_IRQ(REALTEK_CPU_IRQ_SWITCH);
else if (pending & CAUSEF_IP3)
do_IRQ(REALTEK_CPU_IRQ_UART);
else if (pending & CAUSEF_IP2)
do_IRQ(REALTEK_CPU_IRQ_SHARED0);
else
spurious_interrupt();
}
static void __init icu_of_init(struct device_node *node, struct device_node *parent)
{
struct irq_domain *domain;
domain = irq_domain_add_simple(node, 32, 0,
&irq_domain_ops, NULL);
irq_set_chained_handler_and_data(2, rtl838x_irq_dispatch, domain);
irq_set_chained_handler_and_data(5, rtl838x_irq_dispatch, domain);
rtl83xx_ictl_base = of_iomap(node, 0);
if (!rtl83xx_ictl_base)
return;
/* Disable all cascaded interrupts */
rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR));
/* Set up interrupt routing */
rtl83xx_w32(RTL83XX_IRR0_SETTING, REG(RTL83XX_IRR0));
rtl83xx_w32(RTL83XX_IRR1_SETTING, REG(RTL83XX_IRR1));
rtl83xx_w32(RTL83XX_IRR2_SETTING, REG(RTL83XX_IRR2));
rtl83xx_w32(RTL83XX_IRR3_SETTING, REG(RTL83XX_IRR3));
/* Clear timer interrupt */
write_c0_compare(0);
/* Enable all CPU interrupts */
write_c0_status(read_c0_status() | ST0_IM);
/* Enable timer0 and uart0 interrupts */
rtl83xx_w32(BIT(RTL83XX_IRQ_TC0) | BIT(RTL83XX_IRQ_UART0), REG(RTL83XX_ICTL_GIMR));
}
static struct of_device_id __initdata of_irq_ids[] = {
{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
{ .compatible = "realtek,rt8380-intc", .data = icu_of_init },
{},
};
void __init arch_init_irq(void)
{
of_irq_init(of_irq_ids);
}

66
target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c → target/linux/realtek/files-5.4/arch/mips/rtl838x/prom.c
View File

@ -19,59 +19,19 @@
#include <asm/page.h>
#include <asm/cpu.h>
#include <mach-rtl838x.h>
#include <mach-rtl83xx.h>
extern char arcs_cmdline[];
const void *fdt;
extern const char __appended_dtb;
void prom_console_init(void)
{
/* UART 16550A is initialized by the bootloader */
}
#ifdef CONFIG_EARLY_PRINTK
#define rtl838x_r8(reg) __raw_readb(reg)
#define rtl838x_w8(val, reg) __raw_writeb(val, reg)
void unregister_prom_console(void)
{
}
void disable_early_printk(void)
{
}
void prom_putchar(char c)
{
unsigned int retry = 0;
do {
if (retry++ >= 30000) {
/* Reset Tx FIFO */
rtl838x_w8(TXRST | CHAR_TRIGGER_14, UART0_FCR);
return;
}
} while ((rtl838x_r8(UART0_LSR) & LSR_THRE) == TxCHAR_AVAIL);
/* Send Character */
rtl838x_w8(c, UART0_THR);
}
char prom_getchar(void)
{
return '\0';
}
#endif
struct rtl83xx_soc_info soc_info;
const void *fdt;
const char *get_system_type(void)
{
return soc_info.name;
}
void __init prom_free_prom_memory(void)
{
@ -79,7 +39,6 @@ void __init prom_free_prom_memory(void)
void __init device_tree_init(void)
{
pr_info("%s called\r\n", __func__);
if (!fdt_check_header(&__appended_dtb)) {
fdt = &__appended_dtb;
pr_info("Using appended Device Tree.\n");
@ -107,24 +66,19 @@ static void __init prom_init_cmdline(void)
pr_info("Kernel command line: %s\n", arcs_cmdline);
}
/* Do basic initialization */
void __init prom_init(void)
{
uint32_t model;
pr_info("%s called\n", __func__);
/* uart0 */
setup_8250_early_printk_port(0xb8002000, 2, 0);
soc_info.sw_base = RTL838X_SW_BASE;
model = sw_r32(RTL838X_MODEL_NAME_INFO);
pr_info("RTL838X model is %x\n", model);
model = model >> 16 & 0xFFFF;
if ((model != 0x8328) && (model != 0x8330) && (model != 0x8332)
&& (model != 0x8380) && (model != 0x8382)) {
model = sw_r32(RTL839X_MODEL_NAME_INFO);
pr_info("RTL839X model is %x\n", model);
model = model >> 16 & 0xFFFF;
}
model = sw_r32(RTL838X_MODEL_NAME_INFO) >> 16;
if (model != 0x8328 && model != 0x8330 && model != 0x8332 &&
model != 0x8380 && model != 0x8382)
model = sw_r32(RTL839X_MODEL_NAME_INFO) >> 16;
soc_info.id = model;

91
target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c → target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c
View File

@ -25,17 +25,10 @@
#include <asm/prom.h>
#include <asm/smp-ops.h>
#include "mach-rtl838x.h"
#include "mach-rtl83xx.h"
extern int rtl838x_serial_init(void);
struct rtl838x_soc_info soc_info;
struct clk {
struct clk_lookup cl;
unsigned long rate;
};
struct clk cpu_clk;
extern struct rtl83xx_soc_info soc_info;
u32 pll_reset_value;
@ -69,38 +62,16 @@ static void rtl838x_restart(char *command)
static void rtl838x_halt(void)
{
pr_info("System halted.\n");
while
(1);
}
static void __init rtl838x_setup(void)
{
unsigned int val;
pr_info("Registering _machine_restart\n");
_machine_restart = rtl838x_restart;
_machine_halt = rtl838x_halt;
val = rtl838x_r32((volatile void *)0xBB0040000);
if (val == 3)
pr_info("PCI device found\n");
else
pr_info("NO PCI device found\n");
/* Setup System LED. Bit 15 (14 for RTL8390) then allows to toggle it */
if (soc_info.family == RTL8380_FAMILY_ID)
sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL);
else
sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL);
while(1);
}
void __init plat_mem_setup(void)
{
void *dtb;
pr_info("%s called\n", __func__);
set_io_port_base(KSEG1);
_machine_restart = rtl838x_restart;
_machine_halt = rtl838x_halt;
if (fw_passed_dtb) /* UHI interface */
dtb = (void *)fw_passed_dtb;
@ -114,52 +85,12 @@ void __init plat_mem_setup(void)
* parsed resulting in our memory appearing
*/
__dt_setup_arch(dtb);
rtl838x_setup();
}
/*
* Linux clock API
*/
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL_GPL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL_GPL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
return 0;
return clk->rate;
}
EXPORT_SYMBOL_GPL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
return -1;
}
EXPORT_SYMBOL_GPL(clk_set_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
return -1;
}
EXPORT_SYMBOL_GPL(clk_round_rate);
void __init plat_time_init(void)
{
u32 freq = 500000000;
struct device_node *np;
struct clk *clk = &cpu_clk;
u32 freq = 500000000;
np = of_find_node_by_name(NULL, "cpus");
if (!np) {
@ -172,17 +103,7 @@ void __init plat_time_init(void)
of_node_put(np);
}
clk->rate = freq;
if (IS_ERR(clk))
panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
pr_info("CPU Clock: %ld MHz\n", clk->rate / 1000000);
mips_hpt_frequency = freq / 2;
pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
pr_info("PLL control register: %x\n", pll_reset_value);
/* With the info from the command line and cpu-freq we can setup the console */
rtl838x_serial_init();
}

321
target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl8231.c Normal file
View File

@ -0,0 +1,321 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <asm/mach-rtl838x/mach-rtl83xx.h>
/* RTL8231 registers for LED control */
#define RTL8231_LED_FUNC0 0x0000
#define RTL8231_GPIO_PIN_SEL(gpio) ((0x0002) + ((gpio) >> 4))
#define RTL8231_GPIO_DIR(gpio) ((0x0005) + ((gpio) >> 4))
#define RTL8231_GPIO_DATA(gpio) ((0x001C) + ((gpio) >> 4))
struct rtl8231_gpios {
struct gpio_chip gc;
struct device *dev;
u32 id;
int smi_bus_id;
u16 reg_shadow[0x20];
u32 reg_cached;
int ext_gpio_indrt_access;
};
extern struct mutex smi_lock;
extern struct rtl83xx_soc_info soc_info;
static u32 rtl8231_read(struct rtl8231_gpios *gpios, u32 reg)
{
u32 t = 0;
u8 bus_id = gpios->smi_bus_id;
reg &= 0x1f;
bus_id &= 0x1f;
/* Calculate read register address */
t = (bus_id << 2) | (reg << 7);
/* Set execution bit: cleared when operation completed */
t |= 1;
sw_w32(t, gpios->ext_gpio_indrt_access);
do { /* TODO: Return 0x80000000 if timeout */
t = sw_r32(gpios->ext_gpio_indrt_access);
} while (t & 1);
pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, (t & 0xffff0000) >> 16);
return (t & 0xffff0000) >> 16;
}
static int rtl8231_write(struct rtl8231_gpios *gpios, u32 reg, u32 data)
{
u32 t = 0;
u8 bus_id = gpios->smi_bus_id;
pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, data);
reg &= 0x1f;
bus_id &= 0x1f;
t = (bus_id << 2) | (reg << 7) | (data << 16);
/* Set write bit */
t |= 2;
/* Set execution bit: cleared when operation completed */
t |= 1;
sw_w32(t, gpios->ext_gpio_indrt_access);
do { /* TODO: Return -1 if timeout */
t = sw_r32(gpios->ext_gpio_indrt_access);
} while (t & 1);
return 0;
}
static u32 rtl8231_read_cached(struct rtl8231_gpios *gpios, u32 reg)
{
if (reg > 0x1f)
return 0;
if (gpios->reg_cached & (1 << reg))
return gpios->reg_shadow[reg];
return rtl8231_read(gpios, reg);
}
/* Set Direction of the RTL8231 pin:
* dir 1: input
* dir 0: output
*/
static int rtl8231_pin_dir(struct rtl8231_gpios *gpios, u32 gpio, u32 dir)
{
u32 v;
int pin_sel_addr = RTL8231_GPIO_PIN_SEL(gpio);
int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
int pin = gpio % 16;
int dpin = pin;
if (gpio > 31) {
pr_info("WARNING: HIGH pin\n");
dpin = pin << 5;
pin_dir_addr = pin_sel_addr;
}
v = rtl8231_read_cached(gpios, pin_dir_addr);
if (v & 0x80000000) {
pr_err("Error reading RTL8231\n");
return -1;
}
v = (v & ~(1 << dpin)) | (dir << dpin);
rtl8231_write(gpios, pin_dir_addr, v);
gpios->reg_shadow[pin_dir_addr] = v;
gpios->reg_cached |= 1 << pin_dir_addr;
return 0;
}
static int rtl8231_pin_dir_get(struct rtl8231_gpios *gpios, u32 gpio, u32 *dir)
{
/* dir 1: input
* dir 0: output
*/
u32 v;
int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
int pin = gpio % 16;
if (gpio > 31) {
pin_dir_addr = RTL8231_GPIO_PIN_SEL(gpio);
pin = pin << 5;
}
v = rtl8231_read(gpios, pin_dir_addr);
if (v & (1 << pin))
*dir = 1;
else
*dir = 0;
return 0;
}
static int rtl8231_pin_set(struct rtl8231_gpios *gpios, u32 gpio, u32 data)
{
u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));
pr_debug("%s: %d to %d\n", __func__, gpio, data);
if (v & 0x80000000) {
pr_err("Error reading RTL8231\n");
return -1;
}
v = (v & ~(1 << (gpio % 16))) | (data << (gpio % 16));
rtl8231_write(gpios, RTL8231_GPIO_DATA(gpio), v);
gpios->reg_shadow[RTL8231_GPIO_DATA(gpio)] = v;
gpios->reg_cached |= 1 << RTL8231_GPIO_DATA(gpio);
return 0;
}
static int rtl8231_pin_get(struct rtl8231_gpios *gpios, u32 gpio, u16 *state)
{
u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));
if (v & 0x80000000) {
pr_err("Error reading RTL8231\n");
return -1;
}
*state = v & 0xffff;
return 0;
}
static int rtl8231_direction_input(struct gpio_chip *gc, unsigned int offset)
{
int err;
struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
pr_debug("%s: %d\n", __func__, offset);
mutex_lock(&smi_lock);
err = rtl8231_pin_dir(gpios, offset, 1);
mutex_unlock(&smi_lock);
return err;
}
static int rtl8231_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
{
int err;
struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
pr_debug("%s: %d\n", __func__, offset);
mutex_lock(&smi_lock);
err = rtl8231_pin_dir(gpios, offset, 0);
mutex_unlock(&smi_lock);
if (!err)
err = rtl8231_pin_set(gpios, offset, value);
return err;
}
static int rtl8231_get_direction(struct gpio_chip *gc, unsigned int offset)
{
u32 v = 0;
struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
pr_debug("%s: %d\n", __func__, offset);
mutex_lock(&smi_lock);
rtl8231_pin_dir_get(gpios, offset, &v);
mutex_unlock(&smi_lock);
return v;
}
static int rtl8231_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
u16 state = 0;
struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
mutex_lock(&smi_lock);
rtl8231_pin_get(gpios, offset, &state);
mutex_unlock(&smi_lock);
if (state & (1 << (offset % 16)))
return 1;
return 0;
}
void rtl8231_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
{
struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
rtl8231_pin_set(gpios, offset, value);
}
int rtl8231_init(struct rtl8231_gpios *gpios)
{
pr_info("%s called, MDIO bus ID: %d\n", __func__, gpios->smi_bus_id);
if (soc_info.family == RTL8390_FAMILY_ID) {
sw_w32_mask(0x7 << 18, 0x4 << 18, RTL839X_LED_GLB_CTRL);
return 0;
}
/* Enable RTL8231 indirect access mode */
sw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL);
sw_w32_mask(3, 1, RTL838X_DMY_REG5);
/* Enable RTL8231 via GPIO_A1 line
rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DIR);
rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DATA); */
mdelay(50); /* wait 50ms for reset */
/*Select GPIO functionality for pins 0-15, 16-31 and 32-37 */
rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(0), 0xffff);
rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(16), 0xffff);
gpios->reg_cached = 0;
return 0;
}
static const struct of_device_id rtl8231_gpio_of_match[] = {
{ .compatible = "realtek,rtl8231-gpio" },
{},
};
MODULE_DEVICE_TABLE(of, rtl8231_gpio_of_match);
static int rtl8231_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct rtl8231_gpios *gpios;
int err;
u8 indirect_bus_id;
pr_info("Probing RTL8231 GPIOs\n");
if (!np) {
dev_err(&pdev->dev, "No DT found\n");
return -EINVAL;
}
gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
if (!gpios)
return -ENOMEM;
gpios->id = soc_info.id;
if (soc_info.family == RTL8380_FAMILY_ID) {
gpios->ext_gpio_indrt_access = RTL838X_EXT_GPIO_INDRT_ACCESS;
}
if (soc_info.family == RTL8390_FAMILY_ID) {
gpios->ext_gpio_indrt_access = RTL839X_EXT_GPIO_INDRT_ACCESS;
}
if (!of_property_read_u8(np, "indirect-access-bus-id", &indirect_bus_id)) {
gpios->smi_bus_id = indirect_bus_id;
rtl8231_init(gpios);
}
gpios->dev = dev;
gpios->gc.base = 160;
gpios->gc.ngpio = 36;
gpios->gc.label = "rtl8231";
gpios->gc.parent = dev;
gpios->gc.owner = THIS_MODULE;
gpios->gc.can_sleep = true;
gpios->gc.direction_input = rtl8231_direction_input;
gpios->gc.direction_output = rtl8231_direction_output;
gpios->gc.set = rtl8231_gpio_set;
gpios->gc.get = rtl8231_gpio_get;
gpios->gc.get_direction = rtl8231_get_direction;
err = devm_gpiochip_add_data(dev, &gpios->gc, gpios);
return err;
}
static struct platform_driver rtl8231_gpio_driver = {
.driver = {
.name = "rtl8231-gpio",
.of_match_table = rtl8231_gpio_of_match,
},
.probe = rtl8231_gpio_probe,
};
module_platform_driver(rtl8231_gpio_driver);
MODULE_DESCRIPTION("Realtek RTL8231 GPIO expansion chip support");
MODULE_LICENSE("GPL v2");

425
target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl838x.c Normal file
View File

@ -0,0 +1,425 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <asm/mach-rtl838x/mach-rtl83xx.h>
/* RTL8231 registers for LED control */
#define RTL8231_LED_FUNC0 0x0000
#define RTL8231_GPIO_PIN_SEL(gpio) ((0x0002) + ((gpio) >> 4))
#define RTL8231_GPIO_DIR(gpio) ((0x0005) + ((gpio) >> 4))
#define RTL8231_GPIO_DATA(gpio) ((0x001C) + ((gpio) >> 4))
struct rtl838x_gpios {
struct gpio_chip gc;
u32 id;
struct device *dev;
int irq;
int num_leds;
int min_led;
int leds_per_port;
u32 led_mode;
int led_glb_ctrl;
int led_sw_ctrl;
int (*led_sw_p_ctrl)(int port);
int (*led_sw_p_en_ctrl)(int port);
int (*ext_gpio_dir)(int i);
int (*ext_gpio_data)(int i);
};
inline int rtl838x_ext_gpio_dir(int i)
{
return RTL838X_EXT_GPIO_DIR + ((i >>5) << 2);
}
inline int rtl839x_ext_gpio_dir(int i)
{
return RTL839X_EXT_GPIO_DIR + ((i >>5) << 2);
}
inline int rtl838x_ext_gpio_data(int i)
{
return RTL838X_EXT_GPIO_DATA + ((i >>5) << 2);
}
inline int rtl839x_ext_gpio_data(int i)
{
return RTL839X_EXT_GPIO_DATA + ((i >>5) << 2);
}
inline int rtl838x_led_sw_p_ctrl(int p)
{
return RTL838X_LED_SW_P_CTRL + (p << 2);
}
inline int rtl839x_led_sw_p_ctrl(int p)
{
return RTL839X_LED_SW_P_CTRL + (p << 2);
}
inline int rtl838x_led_sw_p_en_ctrl(int p)
{
return RTL838X_LED_SW_P_EN_CTRL + ((p / 10) << 2);
}
inline int rtl839x_led_sw_p_en_ctrl(int p)
{
return RTL839X_LED_SW_P_EN_CTRL + ((p / 10) << 2);
}
extern struct mutex smi_lock;
extern struct rtl83xx_soc_info soc_info;
void rtl838x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
{
int bit;
struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
pr_debug("rtl838x_set: %d, value: %d\n", offset, value);
/* Internal GPIO of the RTL8380 */
if (offset < 32) {
if (value)
rtl83xx_w32_mask(0, BIT(offset), RTL838X_GPIO_PABC_DATA);
else
rtl83xx_w32_mask(BIT(offset), 0, RTL838X_GPIO_PABC_DATA);
}
/* LED driver for PWR and SYS */
if (offset >= 32 && offset < 64) {
bit = offset - 32;
if (value)
sw_w32_mask(0, BIT(bit), gpios->led_glb_ctrl);
else
sw_w32_mask(BIT(bit), 0, gpios->led_glb_ctrl);
return;
}
bit = (offset - 64) % 32;
/* First Port-LED */
if (offset >= 64 && offset < 96
&& offset >= (64 + gpios->min_led)
&& offset < (64 + gpios->min_led + gpios->num_leds)) {
if (value)
sw_w32_mask(7, 5, gpios->led_sw_p_ctrl(bit));
else
sw_w32_mask(7, 0, gpios->led_sw_p_ctrl(bit));
}
if (offset >= 96 && offset < 128
&& offset >= (96 + gpios->min_led)
&& offset < (96 + gpios->min_led + gpios->num_leds)) {
if (value)
sw_w32_mask(7 << 3, 5 << 3, gpios->led_sw_p_ctrl(bit));
else
sw_w32_mask(7 << 3, 0, gpios->led_sw_p_ctrl(bit));
}
if (offset >= 128 && offset < 160
&& offset >= (128 + gpios->min_led)
&& offset < (128 + gpios->min_led + gpios->num_leds)) {
if (value)
sw_w32_mask(7 << 6, 5 << 6, gpios->led_sw_p_ctrl(bit));
else
sw_w32_mask(7 << 6, 0, gpios->led_sw_p_ctrl(bit));
}
__asm__ volatile ("sync");
}
static int rtl838x_direction_input(struct gpio_chip *gc, unsigned int offset)
{
pr_debug("%s: %d\n", __func__, offset);
if (offset < 32) {
rtl83xx_w32_mask(BIT(offset), 0, RTL838X_GPIO_PABC_DIR);
return 0;
}
/* Internal LED driver does not support input */
return -ENOTSUPP;
}
static int rtl838x_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
{
pr_debug("%s: %d\n", __func__, offset);
if (offset < 32)
rtl83xx_w32_mask(0, BIT(offset), RTL838X_GPIO_PABC_DIR);
rtl838x_gpio_set(gc, offset, value);
/* LED for PWR and SYS driver is direction output by default */
return 0;
}
static int rtl838x_get_direction(struct gpio_chip *gc, unsigned int offset)
{
u32 v = 0;
pr_debug("%s: %d\n", __func__, offset);
if (offset < 32) {
v = rtl83xx_r32(RTL838X_GPIO_PABC_DIR);
if (v & BIT(offset))
return 0;
return 1;
}
/* LED driver for PWR and SYS is direction output by default */
if (offset >= 32 && offset < 64)
return 0;
return 0;
}
static int rtl838x_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
u32 v;
struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
pr_debug("%s: %d\n", __func__, offset);
/* Internal GPIO of the RTL8380 */
if (offset < 32) {
v = rtl83xx_r32(RTL838X_GPIO_PABC_DATA);
if (v & BIT(offset))
return 1;
return 0;
}
/* LED driver for PWR and SYS */
if (offset >= 32 && offset < 64) {
v = sw_r32(gpios->led_glb_ctrl);
if (v & BIT(offset-32))
return 1;
return 0;
}
/* BUG:
bit = (offset - 64) % 32;
if (offset >= 64 && offset < 96) {
if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
return 1;
return 0;
}
if (offset >= 96 && offset < 128) {
if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
return 1;
return 0;
}
if (offset >= 128 && offset < 160) {
if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
return 1;
return 0;
}
*/
return 0;
}
void rtl8380_led_test(struct rtl838x_gpios *gpios, u32 mask)
{
int i;
u32 led_gbl = sw_r32(gpios->led_glb_ctrl);
u32 mode_sel, led_p_en;
if (soc_info.family == RTL8380_FAMILY_ID) {
mode_sel = sw_r32(RTL838X_LED_MODE_SEL);
led_p_en = sw_r32(RTL838X_LED_P_EN_CTRL);
}
/* 2 Leds for ports 0-23 and 24-27, 3 would be 0x7 */
sw_w32_mask(0x3f, 0x3 | (0x3 << 3), gpios->led_glb_ctrl);
if(soc_info.family == RTL8380_FAMILY_ID) {
/* Enable all leds */
sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
}
/* Enable software control of all leds */
sw_w32(0xFFFFFFF, gpios->led_sw_ctrl);
sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(0));
sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(10));
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
for (i = 0; i < 28; i++) {
if (mask & BIT(i))
sw_w32(5 | (5 << 3) | (5 << 6), gpios->led_sw_p_ctrl(i));
}
msleep(3000);
if (soc_info.family == RTL8380_FAMILY_ID)
sw_w32(led_p_en, RTL838X_LED_P_EN_CTRL);
/* Disable software control of all leds */
sw_w32(0x0000000, gpios->led_sw_ctrl);
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(0));
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(10));
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
sw_w32(led_gbl, gpios->led_glb_ctrl);
if (soc_info.family == RTL8380_FAMILY_ID)
sw_w32(mode_sel, RTL838X_LED_MODE_SEL);
}
void take_port_leds(struct rtl838x_gpios *gpios)
{
int leds_per_port = gpios->leds_per_port;
int mode = gpios->led_mode;
pr_info("%s, %d, %x\n", __func__, leds_per_port, mode);
pr_debug("Bootloader settings: %x %x %x\n",
sw_r32(gpios->led_sw_p_en_ctrl(0)),
sw_r32(gpios->led_sw_p_en_ctrl(10)),
sw_r32(gpios->led_sw_p_en_ctrl(20))
);
if (soc_info.family == RTL8380_FAMILY_ID) {
pr_debug("led glb: %x, sel %x\n",
sw_r32(gpios->led_glb_ctrl), sw_r32(RTL838X_LED_MODE_SEL));
pr_debug("RTL838X_LED_P_EN_CTRL: %x", sw_r32(RTL838X_LED_P_EN_CTRL));
pr_debug("RTL838X_LED_MODE_CTRL: %x", sw_r32(RTL838X_LED_MODE_CTRL));
sw_w32_mask(3, 0, RTL838X_LED_MODE_SEL);
sw_w32(mode, RTL838X_LED_MODE_CTRL);
}
/* Enable software control of all leds */
sw_w32(0xFFFFFFF, gpios->led_sw_ctrl);
if (soc_info.family == RTL8380_FAMILY_ID)
sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(0));
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(10));
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
sw_w32_mask(0x3f, 0, gpios->led_glb_ctrl);
switch (leds_per_port) {
case 3:
sw_w32_mask(0, 0x7 | (0x7 << 3), gpios->led_glb_ctrl);
sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(20));
/* FALLTHRU */
case 2:
sw_w32_mask(0, 0x3 | (0x3 << 3), gpios->led_glb_ctrl);
sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(10));
/* FALLTHRU */
case 1:
sw_w32_mask(0, 0x1 | (0x1 << 3), gpios->led_glb_ctrl);
sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(0));
break;
default:
pr_err("No LEDS configured for software control\n");
}
}
static const struct of_device_id rtl838x_gpio_of_match[] = {
{ .compatible = "realtek,rtl838x-gpio" },
{},
};
MODULE_DEVICE_TABLE(of, rtl838x_gpio_of_match);
static int rtl838x_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct rtl838x_gpios *gpios;
int err;
pr_info("Probing RTL838X GPIOs\n");
if (!np) {
dev_err(&pdev->dev, "No DT found\n");
return -EINVAL;
}
gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
if (!gpios)
return -ENOMEM;
gpios->id = soc_info.id;
switch (gpios->id) {
case 0x8332:
pr_debug("Found RTL8332M GPIO\n");
break;
case 0x8380:
pr_debug("Found RTL8380M GPIO\n");
break;
case 0x8381:
pr_debug("Found RTL8381M GPIO\n");
break;
case 0x8382:
pr_debug("Found RTL8382M GPIO\n");
break;
case 0x8391:
pr_debug("Found RTL8391 GPIO\n");
break;
case 0x8393:
pr_debug("Found RTL8393 GPIO\n");
break;
default:
pr_err("Unknown GPIO chip id (%04x)\n", gpios->id);
return -ENODEV;
}
if (soc_info.family == RTL8380_FAMILY_ID) {
gpios->led_glb_ctrl = gpios->led_glb_ctrl;
gpios->led_sw_ctrl = RTL838X_LED_SW_CTRL;
gpios->led_sw_p_ctrl = rtl838x_led_sw_p_ctrl;
gpios->led_sw_p_en_ctrl = rtl838x_led_sw_p_en_ctrl;
gpios->ext_gpio_dir = rtl838x_ext_gpio_dir;
gpios->ext_gpio_data = rtl838x_ext_gpio_data;
}
if (soc_info.family == RTL8390_FAMILY_ID) {
gpios->led_glb_ctrl = RTL839X_LED_GLB_CTRL;
gpios->led_sw_ctrl = RTL839X_LED_SW_CTRL;
gpios->led_sw_p_ctrl = rtl839x_led_sw_p_ctrl;
gpios->led_sw_p_en_ctrl = rtl839x_led_sw_p_en_ctrl;
gpios->ext_gpio_dir = rtl839x_ext_gpio_dir;
gpios->ext_gpio_data = rtl839x_ext_gpio_data;
}
gpios->dev = dev;
gpios->gc.base = 0;
/* 0-31: internal
* 32-63, LED control register
* 64-95: PORT-LED 0
* 96-127: PORT-LED 1
* 128-159: PORT-LED 2
*/
gpios->gc.ngpio = 160;
gpios->gc.label = "rtl838x";
gpios->gc.parent = dev;
gpios->gc.owner = THIS_MODULE;
gpios->gc.can_sleep = true;
gpios->irq = 31;
gpios->gc.direction_input = rtl838x_direction_input;
gpios->gc.direction_output = rtl838x_direction_output;
gpios->gc.set = rtl838x_gpio_set;
gpios->gc.get = rtl838x_gpio_get;
gpios->gc.get_direction = rtl838x_get_direction;
if (of_property_read_bool(np, "take-port-leds")) {
if (of_property_read_u32(np, "leds-per-port", &gpios->leds_per_port))
gpios->leds_per_port = 2;
if (of_property_read_u32(np, "led-mode", &gpios->led_mode))
gpios->led_mode = (0x1ea << 15) | 0x1ea;
if (of_property_read_u32(np, "num-leds", &gpios->num_leds))
gpios->num_leds = 32;
if (of_property_read_u32(np, "min-led", &gpios->min_led))
gpios->min_led = 0;
take_port_leds(gpios);
}
err = devm_gpiochip_add_data(dev, &gpios->gc, gpios);
return err;
}
static struct platform_driver rtl838x_gpio_driver = {
.driver = {
.name = "rtl838x-gpio",
.of_match_table = rtl838x_gpio_of_match,
},
.probe = rtl838x_gpio_probe,
};
module_platform_driver(rtl838x_gpio_driver);
MODULE_DESCRIPTION("Realtek RTL838X GPIO API support");
MODULE_LICENSE("GPL v2");

4
target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c → target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c
View File

@ -13,7 +13,9 @@
#include <linux/mtd/spi-nor.h>
#include "rtl838x-spi.h"
#include <asm/mach-rtl838x/mach-rtl838x.h>
#include <asm/mach-rtl838x/mach-rtl83xx.h>
extern struct rtl83xx_soc_info soc_info;
struct rtl838x_nor {
struct spi_nor nor;

6
target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h → target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h
View File

@ -22,8 +22,8 @@
* Register access macros
*/
#define spi_r32(reg) __raw_readl(rtl838x_nor->base + reg)
#define spi_w32(val, reg) __raw_writel(val, rtl838x_nor->base + reg)
#define spi_r32(reg) readl(rtl838x_nor->base + reg)
#define spi_w32(val, reg) writel(val, rtl838x_nor->base + reg)
#define spi_w32_mask(clear, set, reg) \
spi_w32((spi_r32(reg) & ~(clear)) | (set), reg)
@ -31,7 +31,7 @@
} while (!(spi_r32(SFCSR) & SFCSR_SPI_RDY))
#define spi_w32w(val, reg) do { \
__raw_writel(val, rtl838x_nor->base + reg); \
writel(val, rtl838x_nor->base + reg); \
SPI_WAIT_READY; \
} while (0)

8
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Kconfig Normal file
View File

@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only
config NET_DSA_RTL83XX
tristate "Realtek RTL838x/RTL839x switch support"
depends on RTL838X
select NET_DSA_TAG_TRAILER
---help---
This driver adds support for Realtek RTL83xx series switching.

3
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Makefile Normal file
View File

@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_NET_DSA_RTL83XX) += common.o dsa.o \
rtl838x.o rtl839x.o storm.o debugfs.o

407
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c Normal file
View File

@ -0,0 +1,407 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/of_mdio.h>
#include <linux/of_platform.h>
#include <asm/mach-rtl838x/mach-rtl83xx.h>
#include "rtl83xx.h"
extern struct rtl83xx_soc_info soc_info;
extern const struct rtl838x_reg rtl838x_reg;
extern const struct rtl838x_reg rtl839x_reg;
extern const struct dsa_switch_ops rtl83xx_switch_ops;
DEFINE_MUTEX(smi_lock);
// TODO: unused
static void dump_fdb(struct rtl838x_switch_priv *priv)
{
struct rtl838x_l2_entry e;
int i;
mutex_lock(&priv->reg_mutex);
for (i = 0; i < priv->fib_entries; i++) {
priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
if (!e.valid) /* Check for invalid entry */
continue;
pr_debug("-> port %02d: mac %pM, vid: %d, rvid: %d, MC: %d, %d\n",
e.port, &e.mac[0], e.vid, e.rvid, e.is_ip_mc, e.is_ipv6_mc);
}
mutex_unlock(&priv->reg_mutex);
}
// TODO: unused
static void rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
{
u32 cmd, msti = 0;
u32 port_state[4];
int index, bit, i;
int pos = port;
int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4;
/* CPU PORT can only be configured on RTL838x */
if (port >= priv->cpu_port || port > 51)
return;
mutex_lock(&priv->reg_mutex);
/* For the RTL839x, the bits are left-aligned in the 128 bit field */
if (priv->family_id == RTL8390_FAMILY_ID)
pos += 12;
index = n - (pos >> 4) - 1;
bit = (pos << 1) % 32;
if (priv->family_id == RTL8380_FAMILY_ID) {
cmd = BIT(15) /* Execute cmd */
| BIT(14) /* Read */
| 2 << 12 /* Table type 0b10 */
| (msti & 0xfff);
} else {
cmd = BIT(16) /* Execute cmd */
| 0 << 15 /* Read */
| 5 << 12 /* Table type 0b101 */
| (msti & 0xfff);
}
priv->r->exec_tbl0_cmd(cmd);
for (i = 0; i < n; i++)
port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
mutex_unlock(&priv->reg_mutex);
}
int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
{
u32 val;
u32 offset = 0;
struct rtl838x_switch_priv *priv = ds->priv;
if (phy_addr >= 24 && phy_addr <= 27
&& priv->ports[24].phy == PHY_RTL838X_SDS) {
if (phy_addr == 26)
offset = 0x100;
val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff;
return val;
}
if (soc_info.family == RTL8390_FAMILY_ID)
rtl839x_read_phy(phy_addr, 0, phy_reg, &val);
else
rtl838x_read_phy(phy_addr, 0, phy_reg, &val);
return val;
}
int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
{
u32 offset = 0;
struct rtl838x_switch_priv *priv = ds->priv;
if (phy_addr >= 24 && phy_addr <= 27
&& priv->ports[24].phy == PHY_RTL838X_SDS) {
if (phy_addr == 26)
offset = 0x100;
sw_w32(val, MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2));
return 0;
}
if (soc_info.family == RTL8390_FAMILY_ID)
return rtl839x_write_phy(phy_addr, 0, phy_reg, val);
else
return rtl838x_write_phy(phy_addr, 0, phy_reg, val);
}
static int rtl83xx_mdio_read(struct mii_bus *bus, int addr, int regnum)
{
int ret;
struct rtl838x_switch_priv *priv = bus->priv;
ret = rtl83xx_dsa_phy_read(priv->ds, addr, regnum);
return ret;
}
static int rtl83xx_mdio_write(struct mii_bus *bus, int addr, int regnum,
u16 val)
{
struct rtl838x_switch_priv *priv = bus->priv;
return rtl83xx_dsa_phy_write(priv->ds, addr, regnum, val);
}
static void rtl8380_sds_rst(int mac)
{
u32 offset = (mac == 24) ? 0 : 0x100;
sw_w32_mask(1 << 11, 0, RTL8380_SDS4_FIB_REG0 + offset);
sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
pr_debug("SERDES reset: %d\n", mac);
}
static int __init rtl8380_sds_power(int mac, int val)
{
u32 mode = (val == 1) ? 0x4 : 0x9;
u32 offset = (mac == 24) ? 5 : 0;
if ((mac != 24) && (mac != 26)) {
pr_err("%s: not a fibre port: %d\n", __func__, mac);
return -1;
}
sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
rtl8380_sds_rst(mac);
return 0;
}
static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
{
struct device *dev = priv->dev;
struct device_node *dn, *mii_np = dev->of_node;
struct mii_bus *bus;
int ret;
u32 pn;
pr_debug("In %s\n", __func__);
mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
if (mii_np) {
pr_debug("Found compatible MDIO node!\n");
} else {
dev_err(priv->dev, "no %s child node found", "mdio-bus");
return -ENODEV;
}
priv->mii_bus = of_mdio_find_bus(mii_np);
if (!priv->mii_bus) {
pr_debug("Deferring probe of mdio bus\n");
return -EPROBE_DEFER;
}
if (!of_device_is_available(mii_np))
ret = -ENODEV;
bus = devm_mdiobus_alloc(priv->ds->dev);
if (!bus)
return -ENOMEM;
bus->name = "rtl838x slave mii";
bus->read = &rtl83xx_mdio_read;
bus->write = &rtl83xx_mdio_write;
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
bus->parent = dev;
priv->ds->slave_mii_bus = bus;
priv->ds->slave_mii_bus->priv = priv;
ret = mdiobus_register(priv->ds->slave_mii_bus);
if (ret && mii_np) {
of_node_put(dn);
return ret;
}
dn = mii_np;
for_each_node_by_name(dn, "ethernet-phy") {
if (of_property_read_u32(dn, "reg", &pn))
continue;
priv->ports[pn].dp = dsa_to_port(priv->ds, pn);
// Check for the integrated SerDes of the RTL8380M first
if (of_property_read_bool(dn, "phy-is-integrated")
&& priv->id == 0x8380 && pn >= 24) {
pr_debug("----> FÓUND A SERDES\n");
priv->ports[pn].phy = PHY_RTL838X_SDS;
continue;
}
if (of_property_read_bool(dn, "phy-is-integrated")
&& !of_property_read_bool(dn, "sfp")) {
priv->ports[pn].phy = PHY_RTL8218B_INT;
continue;
}
if (!of_property_read_bool(dn, "phy-is-integrated")
&& of_property_read_bool(dn, "sfp")) {
priv->ports[pn].phy = PHY_RTL8214FC;
continue;
}
if (!of_property_read_bool(dn, "phy-is-integrated")
&& !of_property_read_bool(dn, "sfp")) {
priv->ports[pn].phy = PHY_RTL8218B_EXT;
continue;
}
}
/* Disable MAC polling the PHY so that we can start configuration */
priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
/* Enable PHY control via SoC */
if (priv->family_id == RTL8380_FAMILY_ID) {
/* Enable PHY control via SoC */
sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL);
} else {
/* Disable PHY polling via SoC */
sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
}
/* Power on fibre ports and reset them if necessary */
if (priv->ports[24].phy == PHY_RTL838X_SDS) {
pr_debug("Powering on fibre ports & reset\n");
rtl8380_sds_power(24, 1);
rtl8380_sds_power(26, 1);
}
pr_debug("%s done\n", __func__);
return 0;
}
static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
{
int t = sw_r32(priv->r->l2_ctrl_1);
t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
if (priv->family_id == RTL8380_FAMILY_ID)
t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
else
t = (t * 3) / 5;
pr_debug("L2 AGING time: %d sec\n", t);
pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
return t;
}
static int __init rtl83xx_sw_probe(struct platform_device *pdev)
{
int err = 0, i;
struct rtl838x_switch_priv *priv;
struct device *dev = &pdev->dev;
u64 irq_mask;
pr_debug("Probing RTL838X switch device\n");
if (!pdev->dev.of_node) {
dev_err(dev, "No DT found\n");
return -EINVAL;
}
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
if (!priv->ds)
return -ENOMEM;
priv->ds->dev = dev;
priv->ds->priv = priv;
priv->ds->ops = &rtl83xx_switch_ops;
priv->dev = dev;
priv->family_id = soc_info.family;
priv->id = soc_info.id;
if (soc_info.family == RTL8380_FAMILY_ID) {
priv->cpu_port = RTL838X_CPU_PORT;
priv->port_mask = 0x1f;
priv->r = &rtl838x_reg;
priv->ds->num_ports = 30;
priv->fib_entries = 8192;
rtl8380_get_version(priv);
} else {
priv->cpu_port = RTL839X_CPU_PORT;
priv->port_mask = 0x3f;
priv->r = &rtl839x_reg;
priv->ds->num_ports = 53;
priv->fib_entries = 16384;
rtl8390_get_version(priv);
}
pr_debug("Chip version %c\n", priv->version);
err = rtl83xx_mdio_probe(priv);
if (err) {
/* Probing fails the 1st time because of missing ethernet driver
* initialization. Use this to disable traffic in case the bootloader left if on
*/
return err;
}
err = dsa_register_switch(priv->ds);
if (err) {
dev_err(dev, "Error registering switch: %d\n", err);
return err;
}
/* Enable link and media change interrupts. Are the SERDES masks needed? */
sw_w32_mask(0, 3, priv->r->isr_glb_src);
/* ... for all ports */
irq_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x0FFFFFFF : 0xFFFFFFFFFFFFFULL;
priv->r->set_port_reg_le(irq_mask, priv->r->isr_port_link_sts_chg);
priv->r->set_port_reg_le(irq_mask, priv->r->imr_port_link_sts_chg);
priv->link_state_irq = platform_get_irq(pdev, 0);;
if (priv->family_id == RTL8380_FAMILY_ID) {
err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
IRQF_SHARED, "rtl838x-link-state", priv->ds);
} else {
err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
IRQF_SHARED, "rtl839x-link-state", priv->ds);
}
if (err) {
dev_err(dev, "Error setting up switch interrupt.\n");
/* Need to free allocated switch here */
}
/* Enable interrupts for switch */
sw_w32(0x1, priv->r->imr_glb);
rtl83xx_get_l2aging(priv);
/*
if (priv->family_id == RTL8380_FAMILY_ID)
rtl83xx_storm_control_init(priv);
*/
/* Clear all destination ports for mirror groups */
for (i = 0; i < 4; i++)
priv->mirror_group_ports[i] = -1;
rtl838x_dbgfs_init(priv);
return err;
}
static int rtl83xx_sw_remove(struct platform_device *pdev)
{
// TODO:
pr_debug("Removing platform driver for rtl83xx-sw\n");
return 0;
}
static const struct of_device_id rtl83xx_switch_of_ids[] = {
{ .compatible = "realtek,rtl83xx-switch"},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
static struct platform_driver rtl83xx_switch_driver = {
.probe = rtl83xx_sw_probe,
.remove = rtl83xx_sw_remove,
.driver = {
.name = "rtl83xx-switch",
.pm = NULL,
.of_match_table = rtl83xx_switch_of_ids,
},
};
module_platform_driver(rtl83xx_switch_driver);
MODULE_AUTHOR("B. Koblitz");
MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
MODULE_LICENSE("GPL");

99
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/debugfs.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
#include <linux/debugfs.h>
#include <asm/mach-rtl838x/mach-rtl83xx.h>
#include "rtl838x.h"
#define RTL838X_DRIVER_NAME "rtl838x"
static const struct debugfs_reg32 port_ctrl_regs[] = {
{ .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), },
{ .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, },
};
void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv)
{
debugfs_remove_recursive(priv->dbgfs_dir);
// kfree(priv->dbgfs_entries);
}
static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv,
int port)
{
struct dentry *port_dir;
struct debugfs_regset32 *port_ctrl_regset;
port_dir = debugfs_create_dir(priv->ports[port].dp->name, parent);
debugfs_create_x32("rate_uc", 0644, port_dir,
(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port)));
debugfs_create_x32("rate_mc", 0644, port_dir,
(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
debugfs_create_x32("rate_bc", 0644, port_dir,
(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
debugfs_create_u32("id", 0444, port_dir, &priv->ports[port].dp->index);
debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir,
(u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_PORT_TAG_STS_CTRL(port)));
port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
if (!port_ctrl_regset)
return -ENOMEM;
port_ctrl_regset->regs = port_ctrl_regs;
port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
port_ctrl_regset->base = RTL838X_SW_BASE + (port << 2);
debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
return 0;
}
void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv)
{
struct dentry *rtl838x_dir;
struct dentry *port_dir;
struct debugfs_regset32 *port_ctrl_regset;
int ret, i;
rtl838x_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL);
if (!rtl838x_dir)
rtl838x_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL);
priv->dbgfs_dir = rtl838x_dir;
debugfs_create_u32("soc", 0444, rtl838x_dir,
(u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO));
/* Create one directory per port */
for (i = 0; i < priv->cpu_port; i++) {
if (priv->ports[i].phy) {
pr_debug("debugfs, port %d\n", i);
ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i);
if (ret)
goto err;
}
}
/* Create directory for CPU-port */
port_dir = debugfs_create_dir("cpu_port", rtl838x_dir); port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
if (!port_ctrl_regset) {
ret = -ENOMEM;
goto err;
}
port_ctrl_regset->regs = port_ctrl_regs;
port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
port_ctrl_regset->base = RTL838X_SW_BASE + (priv->cpu_port << 2);
debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port);
return;
err:
rtl838x_dbgfs_cleanup(priv);
}

1170
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c Normal file
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476
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
#include <asm/mach-rtl838x/mach-rtl83xx.h>
#include "rtl83xx.h"
extern struct mutex smi_lock;
static inline void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
{
sw_w32_mask((u32)clear, (u32)set, reg);
}
static inline void rtl838x_set_port_reg(u64 set, int reg)
{
sw_w32(set, reg);
}
static inline u64 rtl838x_get_port_reg(int reg)
{
return ((u64) sw_r32(reg));
}
static inline int rtl838x_stat_port_std_mib(int p)
{
return RTL838X_STAT_PORT_STD_MIB + (p << 8);
}
static inline int rtl838x_port_iso_ctrl(int p)
{
return RTL838X_PORT_ISO_CTRL(p);
}
static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
{
sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));
}
static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
{
sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));
}
static inline int rtl838x_tbl_access_data_0(int i)
{
return RTL838X_TBL_ACCESS_DATA_0(i);
}
static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
{
u32 cmd, v;
cmd = BIT(15) /* Execute cmd */
| BIT(14) /* Read */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
rtl838x_exec_tbl0_cmd(cmd);
info->tagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0));
v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1));
info->profile_id = v & 0x7;
info->hash_mc_fid = !!(v & 0x8);
info->hash_uc_fid = !!(v & 0x10);
info->fid = (v >> 5) & 0x3f;
cmd = BIT(15) /* Execute cmd */
| BIT(14) /* Read */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
rtl838x_exec_tbl1_cmd(cmd);
info->untagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
}
static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
{
u32 cmd = BIT(15) /* Execute cmd */
| 0 << 14 /* Write */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
u32 v;
sw_w32(info->tagged_ports, RTL838X_TBL_ACCESS_DATA_0(0));
v = info->profile_id;
v |= info->hash_mc_fid ? 0x8 : 0;
v |= info->hash_uc_fid ? 0x10 : 0;
v |= ((u32)info->fid) << 5;
sw_w32(v, RTL838X_TBL_ACCESS_DATA_0(1));
rtl838x_exec_tbl0_cmd(cmd);
}
static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
{
u32 cmd = BIT(15) /* Execute cmd */
| 0 << 14 /* Write */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
sw_w32(portmask & 0x1fffffff, RTL838X_TBL_ACCESS_DATA_1(0));
rtl838x_exec_tbl1_cmd(cmd);
}
static inline int rtl838x_mac_force_mode_ctrl(int p)
{
return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
}
static inline int rtl838x_mac_port_ctrl(int p)
{
return RTL838X_MAC_PORT_CTRL(p);
}
static inline int rtl838x_l2_port_new_salrn(int p)
{
return RTL838X_L2_PORT_NEW_SALRN(p);
}
static inline int rtl838x_l2_port_new_sa_fwd(int p)
{
return RTL838X_L2_PORT_NEW_SA_FWD(p);
}
static inline int rtl838x_mir_ctrl(int group)
{
return RTL838X_MIR_CTRL(group);
}
static inline int rtl838x_mir_dpm(int group)
{
return RTL838X_MIR_DPM_CTRL(group);
}
static inline int rtl838x_mir_spm(int group)
{
return RTL838X_MIR_SPM_CTRL(group);
}
static inline int rtl838x_mac_link_spd_sts(int p)
{
return RTL838X_MAC_LINK_SPD_STS(p);
}
static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
{
u64 entry;
u32 r[3];
/* Search in SRAM, with hash and at position in hash bucket (0-3) */
u32 idx = (0 << 14) | (hash << 2) | position;
u32 cmd = BIT(16) /* Execute cmd */
| BIT(15) /* Read */
| 0 << 13 /* Table type 0b00 */
| (idx & 0x1fff);
sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
e->mac[0] = (r[1] >> 20);
e->mac[1] = (r[1] >> 12);
e->mac[2] = (r[1] >> 4);
e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
e->mac[4] = (r[2] >> 20);
e->mac[5] = (r[2] >> 12);
e->is_static = !!((r[0] >> 19) & 1);
e->vid = r[0] & 0xfff;
e->rvid = r[2] & 0xfff;
e->port = (r[0] >> 12) & 0x1f;
e->valid = true;
if (!(r[0] >> 17)) /* Check for invalid entry */
e->valid = false;
if (e->valid)
pr_debug("Found in Hash: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
return entry;
}
static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
{
u64 entry;
u32 r[3];
u32 cmd = BIT(16) /* Execute cmd */
| BIT(15) /* Read */
| BIT(13) /* Table type 0b01 */
| (idx & 0x3f);
sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
e->mac[0] = (r[1] >> 20);
e->mac[1] = (r[1] >> 12);
e->mac[2] = (r[1] >> 4);
e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
e->mac[4] = (r[2] >> 20);
e->mac[5] = (r[2] >> 12);
e->is_static = !!((r[0] >> 19) & 1);
e->vid = r[0] & 0xfff;
e->rvid = r[2] & 0xfff;
e->port = (r[0] >> 12) & 0x1f;
e->valid = true;
if (!(r[0] >> 17)) /* Check for invalid entry */
e->valid = false;
if (e->valid)
pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
return entry;
}
static inline int rtl838x_vlan_profile(int profile)
{
return RTL838X_VLAN_PROFILE(profile);
}
static inline int rtl838x_vlan_port_egr_filter(int port)
{
return RTL838X_VLAN_PORT_EGR_FLTR;
}
static inline int rtl838x_vlan_port_igr_filter(int port)
{
return RTL838X_VLAN_PORT_IGR_FLTR(port);
}
static inline int rtl838x_vlan_port_pb(int port)
{
return RTL838X_VLAN_PORT_PB_VLAN(port);
}
static inline int rtl838x_vlan_port_tag_sts_ctrl(int port)
{
return RTL838X_VLAN_PORT_TAG_STS_CTRL(port);
}
const struct rtl838x_reg rtl838x_reg = {
.mask_port_reg_be = rtl838x_mask_port_reg,
.set_port_reg_be = rtl838x_set_port_reg,
.get_port_reg_be = rtl838x_get_port_reg,
.mask_port_reg_le = rtl838x_mask_port_reg,
.set_port_reg_le = rtl838x_set_port_reg,
.get_port_reg_le = rtl838x_get_port_reg,
.stat_port_rst = RTL838X_STAT_PORT_RST,
.stat_rst = RTL838X_STAT_RST,
.stat_port_std_mib = rtl838x_stat_port_std_mib,
.port_iso_ctrl = rtl838x_port_iso_ctrl,
.l2_ctrl_0 = RTL838X_L2_CTRL_0,
.l2_ctrl_1 = RTL838X_L2_CTRL_1,
.l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,
.smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,
.l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
.exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,
.exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,
.tbl_access_data_0 = rtl838x_tbl_access_data_0,
.isr_glb_src = RTL838X_ISR_GLB_SRC,
.isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,
.imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,
.imr_glb = RTL838X_IMR_GLB,
.vlan_tables_read = rtl838x_vlan_tables_read,
.vlan_set_tagged = rtl838x_vlan_set_tagged,
.vlan_set_untagged = rtl838x_vlan_set_untagged,
.mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
.mac_port_ctrl = rtl838x_mac_port_ctrl,
.l2_port_new_salrn = rtl838x_l2_port_new_salrn,
.l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd,
.mir_ctrl = rtl838x_mir_ctrl,
.mir_dpm = rtl838x_mir_dpm,
.mir_spm = rtl838x_mir_spm,
.mac_link_sts = RTL838X_MAC_LINK_STS,
.mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS,
.mac_link_spd_sts = rtl838x_mac_link_spd_sts,
.mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS,
.mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS,
.read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash,
.read_cam = rtl838x_read_cam,
.vlan_profile = rtl838x_vlan_profile,
.vlan_port_egr_filter = rtl838x_vlan_port_egr_filter,
.vlan_port_igr_filter = rtl838x_vlan_port_igr_filter,
.vlan_port_pb = rtl838x_vlan_port_pb,
.vlan_port_tag_sts_ctrl = rtl838x_vlan_port_tag_sts_ctrl,
};
irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
{
struct dsa_switch *ds = dev_id;
u32 status = sw_r32(RTL838X_ISR_GLB_SRC);
u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);
u32 link;
int i;
/* Clear status */
sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
pr_debug("RTL8380 Link change: status: %x, ports %x\n", status, ports);
for (i = 0; i < 28; i++) {
if (ports & BIT(i)) {
link = sw_r32(RTL838X_MAC_LINK_STS);
if (link & BIT(i))
dsa_port_phylink_mac_change(ds, i, true);
else
dsa_port_phylink_mac_change(ds, i, false);
}
}
return IRQ_HANDLED;
}
int rtl838x_smi_wait_op(int timeout)
{
do {
timeout--;
udelay(10);
} while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & 0x1) && (timeout >= 0));
if (timeout <= 0)
return -1;
return 0;
}
/*
* Reads a register in a page from the PHY
*/
int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
{
u32 v;
u32 park_page;
if (port > 31) {
*val = 0xffff;
return 0;
}
if (page > 4095 || reg > 31)
return -ENOTSUPP;
mutex_lock(&smi_lock);
if (rtl838x_smi_wait_op(10000))
goto timeout;
sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
v = reg << 20 | page << 3;
sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
if (rtl838x_smi_wait_op(10000))
goto timeout;
*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
mutex_unlock(&smi_lock);
return 0;
timeout:
mutex_unlock(&smi_lock);
return -ETIMEDOUT;
}
/*
* Write to a register in a page of the PHY
*/
int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
{
u32 v;
u32 park_page;
val &= 0xffff;
if (port > 31 || page > 4095 || reg > 31)
return -ENOTSUPP;
mutex_lock(&smi_lock);
if (rtl838x_smi_wait_op(10000))
goto timeout;
sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
mdelay(10);
sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
v = reg << 20 | page << 3 | 0x4;
sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
if (rtl838x_smi_wait_op(10000))
goto timeout;
mutex_unlock(&smi_lock);
return 0;
timeout:
mutex_unlock(&smi_lock);
return -ETIMEDOUT;
}
void rtl8380_get_version(struct rtl838x_switch_priv *priv)
{
u32 rw_save, info_save;
u32 info;
rw_save = sw_r32(RTL838X_INT_RW_CTRL);
sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);
info_save = sw_r32(RTL838X_CHIP_INFO);
sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);
info = sw_r32(RTL838X_CHIP_INFO);
sw_w32(info_save, RTL838X_CHIP_INFO);
sw_w32(rw_save, RTL838X_INT_RW_CTRL);
if ((info & 0xFFFF) == 0x6275) {
if (((info >> 16) & 0x1F) == 0x1)
priv->version = RTL8380_VERSION_A;
else if (((info >> 16) & 0x1F) == 0x2)
priv->version = RTL8380_VERSION_B;
else
priv->version = RTL8380_VERSION_B;
} else {
priv->version = '-';
}
}
/*
* Applies the same hash algorithm as the one used currently by the ASIC
*/
u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed)
{
u32 h1, h2, h3, h;
if (sw_r32(priv->r->l2_ctrl_0) & 1) {
h1 = (seed >> 11) & 0x7ff;
h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
h2 = (seed >> 33) & 0x7ff;
h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
h3 = (seed >> 44) & 0x7ff;
h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
} else {
h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff)
^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
}
return h;
}
void rtl838x_vlan_profile_dump(int index)
{
u32 profile;
if (index < 0 || index > 7)
return;
profile = sw_r32(RTL838X_VLAN_PROFILE(index));
pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
index, profile & 1, (profile >> 1) & 0x1ff, (profile >> 10) & 0x1ff,
(profile >> 19) & 0x1ff);
}

81
target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h → target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h
View File

@ -54,34 +54,28 @@
#define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880)
#define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980)
/* Registers of the internal Serdes of the 8390 */
#define RTL8390_SDS0_1_XSG0 (0xA000)
#define RTL8390_SDS0_1_XSG1 (0xA100)
#define RTL839X_SDS12_13_XSG0 (0xB800)
#define RTL839X_SDS12_13_XSG1 (0xB900)
#define RTL839X_SDS12_13_PWR0 (0xb880)
#define RTL839X_SDS12_13_PWR1 (0xb980)
/* VLAN registers */
#define RTL838X_VLAN_PROFILE (0x3A88)
#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2))
#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84)
#define RTL838X_VLAN_PORT_PB_VLAN (0x3C00)
#define RTL838X_VLAN_PORT_IGR_FLTR (0x3A7C)
#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2))
#define RTL838X_VLAN_PORT_IGR_FLTR(port) (0x3A7C + (((port >> 4) << 2)))
#define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C)
#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A80)
#define RTL839X_VLAN_PROFILE (0x25C0)
#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4)
#define RTL838X_VLAN_PORT_TAG_STS_CTRL(port) (0xA530 + (((port) << 2)))
#define RTL839X_VLAN_PROFILE(idx) (0x25C0 + (((idx) << 3)))
#define RTL839X_VLAN_CTRL (0x26D4)
#define RTL839X_VLAN_PORT_PB_VLAN (0x26D8)
#define RTL839X_VLAN_PORT_IGR_FLTR (0x27B4)
#define RTL839X_VLAN_PORT_EGR_FLTR (0x27C4)
#define RTL839X_VLAN_PORT_PB_VLAN(port) (0x26D8 + (((port) << 2)))
#define RTL839X_VLAN_PORT_IGR_FLTR(port) (0x27B4 + (((port >> 4) << 2)))
#define RTL839X_VLAN_PORT_EGR_FLTR(port) (0x27C4 + (((port >> 5) << 2)))
#define RTL839X_VLAN_PORT_TAG_STS_CTRL(port) (0x6828 + (((port) << 2)))
/* Table 0/1 access registers */
#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
#define RTL838X_TBL_ACCESS_DATA_0 (0x6918)
#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2))
#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8)
#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2))
#define RTL839X_TBL_ACCESS_CTRL_0 (0x1190)
#define RTL839X_TBL_ACCESS_DATA_0 (0x1194)
#define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2))
#define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80)
#define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2))
@ -143,6 +137,36 @@
#define RTL839X_MIR_DPM_CTRL(grp) (0x2530 + (((grp) << 2)))
#define RTL839X_MIR_SPM_CTRL(grp) (0x2510 + (((grp) << 2)))
/* Storm control */
#define RTL838X_STORM_CTRL (0x4700)
#define RTL839X_STORM_CTRL (0x1800)
#define RTL838X_STORM_CTRL_LB_CTRL(p) (0x4884 + (((p) << 2)))
#define RTL838X_STORM_CTRL_BURST_PPS_0 (0x4874)
#define RTL838X_STORM_CTRL_BURST_PPS_1 (0x4878)
#define RTL838X_STORM_CTRL_BURST_0 (0x487c)
#define RTL838X_STORM_CTRL_BURST_1 (0x4880)
#define RTL838X_SCHED_CTRL (0xB980)
#define RTL838X_SCHED_LB_TICK_TKN_CTRL_0 (0xAD58)
#define RTL838X_SCHED_LB_TICK_TKN_CTRL_1 (0xAD5C)
#define RTL839X_SCHED_LB_TICK_TKN_CTRL_0 (0x1804)
#define RTL839X_SCHED_LB_TICK_TKN_CTRL_1 (0x1808)
#define RTL838X_SCHED_LB_THR (0xB984)
#define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C)
#define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710)
#define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714)
#define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p) (0x180c + (((p >> 5) << 2)))
#define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p) (0x1814 + (((p >> 5) << 2)))
#define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p) (0x181c + (((p >> 5) << 2)))
#define RTL838X_STORM_CTRL_PORT_UC(p) (0x4718 + (((p) << 2)))
#define RTL838X_STORM_CTRL_PORT_MC(p) (0x478c + (((p) << 2)))
#define RTL838X_STORM_CTRL_PORT_BC(p) (0x4800 + (((p) << 2)))
/* Attack prevention */
#define RTL838X_ATK_PRVNT_PORT_EN (0x5B00)
#define RTL838X_ATK_PRVNT_CTRL (0x5B04)
#define RTL838X_ATK_PRVNT_ACT (0x5B08)
#define RTL838X_ATK_PRVNT_STS (0x5B1C)
enum phy_type {
PHY_NONE = 0,
PHY_RTL838X_SDS = 1,
@ -158,14 +182,15 @@ struct rtl838x_port {
u16 pvid;
bool eee_enabled;
enum phy_type phy;
const struct dsa_port *dp;
};
struct rtl838x_vlan_info {
u64 untagged_ports;
u64 tagged_ports;
u8 profile_id;
bool hash_mc;
bool hash_uc;
bool hash_mc_fid;
bool hash_uc_fid;
u8 fid;
};
@ -178,7 +203,7 @@ enum l2_entry_type {
};
struct rtl838x_l2_entry {
u8 mac[ETH_ALEN];
u8 mac[6];
u16 vid;
u16 rvid;
u8 port;
@ -221,7 +246,7 @@ struct rtl838x_reg {
int imr_port_link_sts_chg;
int imr_glb;
void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
void (*vlan_set_tagged)(u32 vlan, const struct rtl838x_vlan_info *info);
void (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info);
void (*vlan_set_untagged)(u32 vlan, u64 portmask);
int (*mac_force_mode_ctrl)(int port);
int (*mac_port_ctrl)(int port);
@ -241,6 +266,7 @@ struct rtl838x_reg {
int (*vlan_port_egr_filter)(int port);
int (*vlan_port_igr_filter)(int port);
int (*vlan_port_pb)(int port);
int (*vlan_port_tag_sts_ctrl)(int port);
};
struct rtl838x_switch_priv {
@ -259,16 +285,9 @@ struct rtl838x_switch_priv {
u8 cpu_port;
u8 port_mask;
u32 fib_entries;
struct dentry *dbgfs_dir;
};
extern struct rtl838x_soc_info soc_info;
extern void rtl8380_sds_rst(int mac);
extern int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
extern int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
extern int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
extern int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
extern int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val);
extern int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val);
void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv);
#endif /* _RTL838X_H */

514
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c Normal file
View File

@ -0,0 +1,514 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <asm/mach-rtl838x/mach-rtl83xx.h>
#include "rtl83xx.h"
extern struct mutex smi_lock;
static inline void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
{
sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
}
static inline u64 rtl839x_get_port_reg_be(int reg)
{
u64 v = sw_r32(reg);
v <<= 32;
v |= sw_r32(reg + 4);
return v;
}
static inline void rtl839x_set_port_reg_be(u64 set, int reg)
{
sw_w32(set >> 32, reg);
sw_w32(set & 0xffffffff, reg + 4);
}
static inline void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
{
sw_w32_mask((u32)clear, (u32)set, reg);
sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
}
static inline void rtl839x_set_port_reg_le(u64 set, int reg)
{
sw_w32(set, reg);
sw_w32(set >> 32, reg + 4);
}
static inline u64 rtl839x_get_port_reg_le(int reg)
{
u64 v = sw_r32(reg + 4);
v <<= 32;
v |= sw_r32(reg);
return v;
}
static inline int rtl839x_stat_port_std_mib(int p)
{
return RTL839X_STAT_PORT_STD_MIB + (p << 8);
}
static inline int rtl839x_port_iso_ctrl(int p)
{
return RTL839X_PORT_ISO_CTRL(p);
}
static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
{
sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
}
static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
{
sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
}
static inline int rtl839x_tbl_access_data_0(int i)
{
return RTL839X_TBL_ACCESS_DATA_0(i);
}
static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
{
u32 cmd;
u64 v;
u32 u, w;
cmd = BIT(16) /* Execute cmd */
| 0 << 15 /* Read */
| 0 << 12 /* Table type 0b000 */
| (vlan & 0xfff);
rtl839x_exec_tbl0_cmd(cmd);
v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0));
v <<= 32;
u = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1));
v |= u;
info->tagged_ports = v >> 11;
w = sw_r32(RTL838X_TBL_ACCESS_DATA_0(2));
info->profile_id = w >> 30 | ((u & 1) << 2);
info->hash_mc_fid = !!(u & 2);
info->hash_uc_fid = !!(u & 4);
info->fid = (u >> 3) & 0xff;
cmd = BIT(16) /* Execute cmd */
| 0 << 15 /* Read */
| 0 << 12 /* Table type 0b000 */
| (vlan & 0xfff);
rtl839x_exec_tbl1_cmd(cmd);
v = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
v <<= 32;
v |= sw_r32(RTL838X_TBL_ACCESS_DATA_1(1));
info->untagged_ports = v >> 11;
}
static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
{
u32 cmd = BIT(16) /* Execute cmd */
| BIT(15) /* Write */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
u32 w;
u64 v = info->tagged_ports << 11;
v |= info->profile_id >> 2;
v |= info->hash_mc_fid ? 2 : 0;
v |= info->hash_uc_fid ? 4 : 0;
v |= ((u32)info->fid) << 3;
rtl839x_set_port_reg_be(v, RTL838X_TBL_ACCESS_DATA_0(0));
w = info->profile_id;
sw_w32(w << 30, RTL838X_TBL_ACCESS_DATA_0(2));
rtl839x_exec_tbl0_cmd(cmd);
}
static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
{
u32 cmd = BIT(16) /* Execute cmd */
| BIT(15) /* Write */
| 0 << 12 /* Table type 0b00 */
| (vlan & 0xfff);
rtl839x_set_port_reg_be(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0));
rtl839x_exec_tbl1_cmd(cmd);
}
static inline int rtl839x_mac_force_mode_ctrl(int p)
{
return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
}
static inline int rtl839x_mac_port_ctrl(int p)
{
return RTL839X_MAC_PORT_CTRL(p);
}
static inline int rtl839x_l2_port_new_salrn(int p)
{
return RTL839X_L2_PORT_NEW_SALRN(p);
}
static inline int rtl839x_l2_port_new_sa_fwd(int p)
{
return RTL839X_L2_PORT_NEW_SA_FWD(p);
}
static inline int rtl839x_mir_ctrl(int group)
{
return RTL839X_MIR_CTRL(group);
}
static inline int rtl839x_mir_dpm(int group)
{
return RTL839X_MIR_DPM_CTRL(group);
}
static inline int rtl839x_mir_spm(int group)
{
return RTL839X_MIR_SPM_CTRL(group);
}
static inline int rtl839x_mac_link_spd_sts(int p)
{
return RTL839X_MAC_LINK_SPD_STS(p);
}
static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
{
u64 entry;
u32 r[3];
/* Search in SRAM, with hash and at position in hash bucket (0-3) */
u32 idx = (0 << 14) | (hash << 2) | position;
u32 cmd = BIT(17) /* Execute cmd */
| 0 << 16 /* Read */
| 0 << 14 /* Table type 0b00 */
| (idx & 0x3fff);
sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17));
r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
/* Table contains different entry types, we need to identify the right one:
* Check for MC entries, first
*/
e->is_ip_mc = !!(r[2] & BIT(31));
e->is_ipv6_mc = !!(r[2] & BIT(30));
e->type = L2_INVALID;
if (!e->is_ip_mc) {
e->mac[0] = (r[0] >> 12);
e->mac[1] = (r[0] >> 4);
e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
e->mac[3] = (r[1] >> 20);
e->mac[4] = (r[1] >> 12);
e->mac[5] = (r[1] >> 4);
/* Is it a unicast entry? check multicast bit */
if (!(e->mac[0] & 1)) {
e->is_static = !!((r[2] >> 18) & 1);
e->vid = (r[2] >> 4) & 0xfff;
e->rvid = (r[0] >> 20) & 0xfff;
e->port = (r[2] >> 24) & 0x3f;
e->block_da = !!(r[2] & BIT(19));
e->block_sa = !!(r[2] & BIT(20));
e->suspended = !!(r[2] & BIT(17));
e->next_hop = !!(r[2] & BIT(16));
if (e->next_hop)
pr_debug("Found next hop entry, need to read data\n");
e->age = (r[2] >> 21) & 3;
e->valid = true;
if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
e->valid = false;
else
e->type = L2_UNICAST;
} else {
e->valid = true;
e->type = L2_MULTICAST;
e->mc_portmask_index = (r[2]>>6) & 0xfff;
}
}
if (e->is_ip_mc) {
e->valid = true;
e->type = IP4_MULTICAST;
}
if (e->is_ipv6_mc) {
e->valid = true;
e->type = IP6_MULTICAST;
}
entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
return entry;
}
static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
{
u64 entry;
u32 r[3];
u32 cmd = BIT(17) /* Execute cmd */
| 0 << 16 /* Read */
| BIT(14) /* Table type 0b01 */
| (idx & 0x3f);
sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17));
r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
e->mac[0] = (r[0] >> 12);
e->mac[1] = (r[0] >> 4);
e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
e->mac[3] = (r[1] >> 20);
e->mac[4] = (r[1] >> 12);
e->mac[5] = (r[1] >> 4);
e->is_static = !!((r[2] >> 18) & 1);
e->vid = (r[2] >> 4) & 0xfff;
e->rvid = (r[0] >> 20) & 0xfff;
e->port = (r[2] >> 24) & 0x3f;
e->valid = true;
if (!(r[2] & 0x10fd0000)) /* Check for invalid entry */
e->valid = false;
if (e->valid)
pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
return entry;
}
static inline int rtl839x_vlan_profile(int profile)
{
return RTL839X_VLAN_PROFILE(profile);
}
static inline int rtl839x_vlan_port_egr_filter(int port)
{
return RTL839X_VLAN_PORT_EGR_FLTR(port);
}
static inline int rtl839x_vlan_port_igr_filter(int port)
{
return RTL839X_VLAN_PORT_IGR_FLTR(port);
}
static inline int rtl839x_vlan_port_pb(int port)
{
return RTL839X_VLAN_PORT_PB_VLAN(port);
}
static inline int rtl839x_vlan_port_tag_sts_ctrl(int port)
{
return RTL839X_VLAN_PORT_TAG_STS_CTRL(port);
}
const struct rtl838x_reg rtl839x_reg = {
.mask_port_reg_be = rtl839x_mask_port_reg_be,
.set_port_reg_be = rtl839x_set_port_reg_be,
.get_port_reg_be = rtl839x_get_port_reg_be,
.mask_port_reg_le = rtl839x_mask_port_reg_le,
.set_port_reg_le = rtl839x_set_port_reg_le,
.get_port_reg_le = rtl839x_get_port_reg_le,
.stat_port_rst = RTL839X_STAT_PORT_RST,
.stat_rst = RTL839X_STAT_RST,
.stat_port_std_mib = rtl839x_stat_port_std_mib,
.port_iso_ctrl = rtl839x_port_iso_ctrl,
.l2_ctrl_0 = RTL839X_L2_CTRL_0,
.l2_ctrl_1 = RTL839X_L2_CTRL_1,
.l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
.smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
.exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
.exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
.tbl_access_data_0 = rtl839x_tbl_access_data_0,
.isr_glb_src = RTL839X_ISR_GLB_SRC,
.isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
.imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
.imr_glb = RTL839X_IMR_GLB,
.vlan_tables_read = rtl839x_vlan_tables_read,
.vlan_set_tagged = rtl839x_vlan_set_tagged,
.vlan_set_untagged = rtl839x_vlan_set_untagged,
.mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
.mac_port_ctrl = rtl839x_mac_port_ctrl,
.l2_port_new_salrn = rtl839x_l2_port_new_salrn,
.l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
.mir_ctrl = rtl839x_mir_ctrl,
.mir_dpm = rtl839x_mir_dpm,
.mir_spm = rtl839x_mir_spm,
.mac_link_sts = RTL839X_MAC_LINK_STS,
.mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
.mac_link_spd_sts = rtl839x_mac_link_spd_sts,
.mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
.mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
.read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
.read_cam = rtl839x_read_cam,
.vlan_profile = rtl839x_vlan_profile,
.vlan_port_egr_filter = rtl839x_vlan_port_egr_filter,
.vlan_port_igr_filter = rtl839x_vlan_port_igr_filter,
.vlan_port_pb = rtl839x_vlan_port_pb,
.vlan_port_tag_sts_ctrl = rtl839x_vlan_port_tag_sts_ctrl,
};
irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
{
struct dsa_switch *ds = dev_id;
u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
u64 link;
int i;
/* Clear status */
rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
for (i = 0; i < 52; i++) {
if (ports & (1ULL << i)) {
link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
if (link & (1ULL << i))
dsa_port_phylink_mac_change(ds, i, true);
else
dsa_port_phylink_mac_change(ds, i, false);
}
}
return IRQ_HANDLED;
}
// TODO: unused
int rtl8390_sds_power(int mac, int val)
{
u32 offset = (mac == 48) ? 0x0 : 0x100;
u32 mode = val ? 0 : 1;
pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
if ((mac != 48) && (mac != 49)) {
pr_err("%s: not an SFP port: %d\n", __func__, mac);
return -1;
}
// Set bit 1003. 1000 starts at 7c
sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
return 0;
}
int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
{
u32 v;
if (port > 63 || page > 4095 || reg > 31)
return -ENOTSUPP;
mutex_lock(&smi_lock);
sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
v |= 1;
sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
do {
} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
*val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
mutex_unlock(&smi_lock);
return 0;
}
int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
{
u32 v;
int err = 0;
val &= 0xffff;
if (port > 63 || page > 4095 || reg > 31)
return -ENOTSUPP;
mutex_lock(&smi_lock);
/* Clear both port registers */
sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0));
sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4);
sw_w32_mask(0, BIT(port), RTL839X_PHYREG_PORT_CTRL(port));
sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
v |= BIT(3) | 1; /* Write operation and execute */
sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
do {
} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
err = -EIO;
mutex_unlock(&smi_lock);
return err;
}
void rtl8390_get_version(struct rtl838x_switch_priv *priv)
{
u32 info;
sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
info = sw_r32(RTL839X_CHIP_INFO);
pr_debug("Chip-Info: %x\n", info);
priv->version = RTL8390_VERSION_A;
}
u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed)
{
u32 h1, h2, h;
if (sw_r32(priv->r->l2_ctrl_0) & 1) {
h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
^ (seed & 0x3f));
h = (h1 << 6) | h2;
} else {
h = (seed >> 60)
^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
}
return h;
}
void rtl839x_vlan_profile_dump(int index)
{
u32 profile, profile1;
if (index < 0 || index > 7)
return;
profile1 = sw_r32(RTL839X_VLAN_PROFILE(index) + 4);
profile = sw_r32(RTL839X_VLAN_PROFILE(index));
pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
index, profile & 1, (profile >> 1) & 0xfff, (profile >> 13) & 0xfff,
(profile1) & 0xfff);
}

44
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl83xx.h Normal file
View File

@ -0,0 +1,44 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _NET_DSA_RTL83XX_H
#define _NET_DSA_RTL83XX_H
#include <net/dsa.h>
#include "rtl838x.h"
#define RTL8380_VERSION_A 'A'
#define RTL8390_VERSION_A 'A'
#define RTL8380_VERSION_B 'B'
struct fdb_update_work {
struct work_struct work;
struct net_device *ndev;
u64 macs[];
};
#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
struct rtl83xx_mib_desc {
unsigned int size;
unsigned int offset;
const char *name;
};
void __init rtl83xx_storm_control_init(struct rtl838x_switch_priv *priv);
/* RTL838x-specific */
u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed);
irqreturn_t rtl838x_switch_irq(int irq, void *dev_id);
void rtl8380_get_version(struct rtl838x_switch_priv *priv);
void rtl838x_vlan_profile_dump(int index);
int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg);
/* RTL839x-specific */
u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed);
irqreturn_t rtl839x_switch_irq(int irq, void *dev_id);
void rtl8390_get_version(struct rtl838x_switch_priv *priv);
void rtl839x_vlan_profile_dump(int index);
int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val);
#endif /* _NET_DSA_RTL83XX_H */

64
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/storm.c Normal file
View File

@ -0,0 +1,64 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <asm/mach-rtl838x/mach-rtl83xx.h>
#include "rtl83xx.h"
static void rtl83xx_storm_enable(struct rtl838x_switch_priv *priv, int port, bool enable)
{
// Enable Storm control for that port for UC, MC, and BC
if (enable)
sw_w32(0x7, RTL838X_STORM_CTRL_LB_CTRL(port));
else
sw_w32(0x0, RTL838X_STORM_CTRL_LB_CTRL(port));
}
void __init rtl83xx_storm_control_init(struct rtl838x_switch_priv *priv)
{
int i;
pr_debug("Enabling Storm control\n");
// TICK_PERIOD_PPS
if (priv->id == 0x8380)
sw_w32_mask(0x3ff << 20, 434 << 20, RTL838X_SCHED_LB_TICK_TKN_CTRL_0);
// Set burst rate
sw_w32(0x00008000, RTL838X_STORM_CTRL_BURST_0); // UC
sw_w32(0x80008000, RTL838X_STORM_CTRL_BURST_1); // MC and BC
// Set burst Packets per Second to 32
sw_w32(0x00000020, RTL838X_STORM_CTRL_BURST_PPS_0); // UC
sw_w32(0x00200020, RTL838X_STORM_CTRL_BURST_PPS_1); // MC and BC
// Include IFG in storm control
sw_w32_mask(0, BIT(6), RTL838X_STORM_CTRL);
// Rate control is based on bytes/s (0 = packets)
sw_w32_mask(0, BIT(5), RTL838X_STORM_CTRL);
// Bandwidth control includes preamble and IFG (10 Bytes)
sw_w32_mask(0, 1, RTL838X_SCHED_CTRL);
// On SoCs except RTL8382M, set burst size of port egress
if (priv->id != 0x8382)
sw_w32_mask(0xffff, 0x800, RTL838X_SCHED_LB_THR);
/* Enable storm control on all ports with a PHY and limit rates,
* for UC and MC for both known and unknown addresses */
for (i = 0; i < priv->cpu_port; i++) {
if (priv->ports[i].phy) {
sw_w32(BIT(18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i));
sw_w32(BIT(18) | 0x8000, RTL838X_STORM_CTRL_PORT_MC(i));
sw_w32(0x000, RTL838X_STORM_CTRL_PORT_BC(i));
rtl83xx_storm_enable(priv, i, true);
}
}
// Attack prevention, enable all attack prevention measures
//sw_w32(0x1ffff, RTL838X_ATK_PRVNT_CTRL);
/* Attack prevention, drop (bit = 0) problematic packets on all ports.
* Setting bit = 1 means: trap to CPU
*/
//sw_w32(0, RTL838X_ATK_PRVNT_ACT);
// Enable attack prevention on all ports
//sw_w32(0x0fffffff, RTL838X_ATK_PRVNT_PORT_EN);
}

136
target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c → target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.c
View File

@ -20,9 +20,11 @@
#include <net/switchdev.h>
#include <asm/cacheflush.h>
#include <asm/mach-rtl838x/mach-rtl838x.h>
#include <asm/mach-rtl838x/mach-rtl83xx.h>
#include "rtl838x_eth.h"
extern struct rtl83xx_soc_info soc_info;
/*
* Maximum number of RX rings is 8, assigned by switch based on
* packet/port priortity (not implemented)
@ -43,6 +45,11 @@
#define RING_BUFFER 1600
#define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C)
#define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710)
#define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714)
#define RTL838X_ATK_PRVNT_STS (0x5B1C)
struct p_hdr {
uint8_t *buf;
uint16_t reserved;
@ -118,8 +125,6 @@ inline void rtl839x_create_tx_header(struct p_hdr *h, int dest_port)
}
}
extern void rtl838x_fdb_sync(struct work_struct *work);
struct rtl838x_eth_priv {
struct net_device *netdev;
struct platform_device *pdev;
@ -222,6 +227,29 @@ struct fdb_update_work {
u64 macs[NOTIFY_EVENTS + 1];
};
void rtl838x_fdb_sync(struct work_struct *work)
{
const struct fdb_update_work *uw =
container_of(work, struct fdb_update_work, work);
struct switchdev_notifier_fdb_info info;
u8 addr[ETH_ALEN];
int i = 0;
int action;
while (uw->macs[i]) {
action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
: SWITCHDEV_FDB_DEL_TO_BRIDGE;
u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
info.addr = &addr[0];
info.vid = 0;
info.offloaded = 1;
pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
i++;
}
kfree(work);
}
static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
{
struct notify_b *nb = priv->membase + sizeof(struct ring_b);
@ -265,6 +293,28 @@ static irqreturn_t rtl838x_net_irq(int irq, void *dev_id)
struct net_device *dev = dev_id;
struct rtl838x_eth_priv *priv = netdev_priv(dev);
u32 status = sw_r32(priv->r->dma_if_intr_sts);
bool triggered = false;
u32 atk = sw_r32(RTL838X_ATK_PRVNT_STS);
u32 storm_uc = sw_r32(RTL838X_STORM_CTRL_PORT_UC_EXCEED);
u32 storm_mc = sw_r32(RTL838X_STORM_CTRL_PORT_MC_EXCEED);
u32 storm_bc = sw_r32(RTL838X_STORM_CTRL_PORT_BC_EXCEED);
if (storm_uc || storm_mc || storm_bc) {
pr_warn("Storm control UC: %08x, MC: %08x, BC: %08x\n",
storm_uc, storm_mc, storm_bc);
sw_w32(storm_uc, RTL838X_STORM_CTRL_PORT_UC_EXCEED);
sw_w32(storm_mc, RTL838X_STORM_CTRL_PORT_MC_EXCEED);
sw_w32(storm_bc, RTL838X_STORM_CTRL_PORT_BC_EXCEED);
triggered = true;
}
if (atk) {
pr_debug("Attack prevention triggered: %08x\n", atk);
sw_w32(atk, RTL838X_ATK_PRVNT_STS);
}
spin_lock(&priv->lock);
/* Ignore TX interrupt */
@ -276,6 +326,8 @@ static irqreturn_t rtl838x_net_irq(int irq, void *dev_id)
/* RX interrupt */
if (status & 0x0ff00) {
/* Disable RX interrupt */
if (triggered)
pr_info("RX\n");
sw_w32_mask(0xff00, 0, priv->r->dma_if_intr_msk);
sw_w32(0x0000ff00, priv->r->dma_if_intr_sts);
napi_schedule(&priv->napi);
@ -283,14 +335,24 @@ static irqreturn_t rtl838x_net_irq(int irq, void *dev_id)
/* RX buffer overrun */
if (status & 0x000ff) {
pr_debug("RX buffer overrun: status %x, mask: %x\n",
pr_info("RX buffer overrun: status %x, mask: %x\n",
status, sw_r32(priv->r->dma_if_intr_msk));
sw_w32(0x000000ff, priv->r->dma_if_intr_sts);
rtl838x_rb_cleanup(priv);
}
if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
sw_w32(0x00700000, priv->r->dma_if_intr_sts);
sw_w32(0x00100000, priv->r->dma_if_intr_sts);
rtl839x_l2_notification_handler(priv);
}
if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
sw_w32(0x00200000, priv->r->dma_if_intr_sts);
rtl839x_l2_notification_handler(priv);
}
if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
sw_w32(0x00400000, priv->r->dma_if_intr_sts);
rtl839x_l2_notification_handler(priv);
}
@ -1051,6 +1113,70 @@ static int rtl838x_set_link_ksettings(struct net_device *ndev,
return phylink_ethtool_ksettings_set(priv->phylink, cmd);
}
int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
{
int offset = 0;
int reg;
u32 val;
if (phy_addr == 49)
offset = 0x100;
/* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
* which would otherwise read as 0
*/
if (soc_info.id == 0x8393) {
if (phy_reg == 2)
return 0x1c;
if (phy_reg == 3)
return 0x8393;
}
reg = (phy_reg << 1) & 0xfc;
val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
if (phy_reg & 1)
val = (val >> 16) & 0xffff;
else
val &= 0xffff;
return val;
}
int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
{
int offset = 0;
u32 val;
if (phy_addr == 26)
offset = 0x100;
val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff;
return val;
}
int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
{
int offset = 0;
int reg;
u32 val;
if (phy_addr == 49)
offset = 0x100;
reg = (phy_reg << 1) & 0xfc;
val = v;
if (phy_reg & 1) {
val = val << 16;
sw_w32_mask(0xffff0000, val,
RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
} else {
sw_w32_mask(0xffff, val,
RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
}
return 0;
}
static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
{
u32 val;

6
target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h → target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.h
View File

@ -116,6 +116,10 @@
#define RTL839X_RMA_CTRL_2 (0x1208)
#define RTL839X_RMA_CTRL_3 (0x120C)
/* Registers of the internal Serdes of the 8390 */
#define RTL839X_SDS12_13_XSG0 (0xB800)
inline int rtl838x_mac_port_ctrl(int p)
{
return RTL838X_MAC_PORT_CTRL + (p << 7);
@ -272,6 +276,4 @@ int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
extern int rtl8380_sds_power(int mac, int val);
#endif /* _RTL838X_ETH_H */

343
target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_phy.c → target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.c
View File

@ -4,52 +4,24 @@
* Copyright (C) 2020 B. Koblitz
*/
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_mdio.h>
#include <linux/delay.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/netdevice.h>
#include <linux/firmware.h>
#include <linux/crc32.h>
#include <asm/mach-rtl838x/mach-rtl838x.h>
#include "rtl838x.h"
#include <asm/mach-rtl838x/mach-rtl83xx.h>
#include "rtl83xx-phy.h"
/* External RTL8218B and RTL8214FC IDs are identical */
#define PHY_ID_RTL8214C 0x001cc942
#define PHY_ID_RTL8214FC 0x001cc981
#define PHY_ID_RTL8218B_E 0x001cc981
#define PHY_ID_RTL8218B_I 0x001cca40
#define PHY_ID_RTL8390_GENERIC 0x001ccab0
#define PHY_ID_RTL8393_I 0x001c8393
struct __attribute__ ((__packed__)) part {
uint16_t start;
uint8_t wordsize;
uint8_t words;
};
struct __attribute__ ((__packed__)) fw_header {
uint32_t magic;
uint32_t phy;
uint32_t checksum;
uint32_t version;
struct part parts[10];
};
#define FIRMWARE_838X_8380_1 "rtl838x_phy/rtl838x_8380.fw"
#define FIRMWARE_838X_8214FC_1 "rtl838x_phy/rtl838x_8214fc.fw"
#define FIRMWARE_838X_8218b_1 "rtl838x_phy/rtl838x_8218b.fw"
extern struct rtl83xx_soc_info soc_info;
extern struct mutex smi_lock;
static const struct firmware rtl838x_8380_fw;
static const struct firmware rtl838x_8214fc_fw;
static const struct firmware rtl838x_8218b_fw;
struct rtl838x_phy_priv {
char *name;
};
static int read_phy(u32 port, u32 page, u32 reg, u32 *val)
{
@ -67,7 +39,7 @@ static int write_phy(u32 port, u32 page, u32 reg, u32 val)
return rtl838x_write_phy(port, page, reg, val);
}
static void rtl8380_int_phy_on_off(int mac, bool on)
static void int_phy_on_off(int mac, bool on)
{
u32 val;
@ -78,7 +50,7 @@ static void rtl8380_int_phy_on_off(int mac, bool on)
write_phy(mac, 0, 0, val | (1 << 11));
}
static void rtl8380_rtl8214fc_on_off(int mac, bool on)
static void rtl8214fc_on_off(int mac, bool on)
{
u32 val;
@ -99,7 +71,7 @@ static void rtl8380_rtl8214fc_on_off(int mac, bool on)
write_phy(mac, 0xa40, 16, val | (1 << 11));
}
static void rtl8380_phy_reset(int mac)
static void phy_reset(int mac)
{
u32 val;
@ -107,89 +79,12 @@ static void rtl8380_phy_reset(int mac)
write_phy(mac, 0, 0, val | (0x1 << 15));
}
void rtl8380_sds_rst(int mac)
{
u32 offset = (mac == 24) ? 0 : 0x100;
sw_w32_mask(1 << 11, 0, RTL8380_SDS4_FIB_REG0 + offset);
sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
pr_info("SERDES reset: %d\n", mac);
}
int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
{
int offset = 0;
int reg;
u32 val;
if (phy_addr == 49)
offset = 0x100;
/* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
* which would otherwise read as 0
*/
if (soc_info.id == 0x8393) {
if (phy_reg == 2)
return 0x1c;
if (phy_reg == 3)
return 0x8393;
}
reg = (phy_reg << 1) & 0xfc;
val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
if (phy_reg & 1)
val = (val >> 16) & 0xffff;
else
val &= 0xffff;
return val;
}
int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
{
int offset = 0;
u32 val;
if (phy_addr == 26)
offset = 0x100;
val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff;
return val;
}
int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
{
int offset = 0;
int reg;
u32 val;
if (phy_addr == 49)
offset = 0x100;
reg = (phy_reg << 1) & 0xfc;
val = v;
if (phy_reg & 1) {
val = val << 16;
sw_w32_mask(0xffff0000, val,
RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
} else {
sw_w32_mask(0xffff, val,
RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
}
return 0;
}
/* Read the link and speed status of the 2 internal SGMII/1000Base-X
* ports of the RTL838x SoCs
*/
static int rtl8380_read_status(struct phy_device *phydev)
{
int err;
int phy_addr = phydev->mdio.addr;
err = genphy_read_status(phydev);
@ -229,9 +124,9 @@ static int rtl8393_read_status(struct phy_device *phydev)
return err;
}
static struct fw_header *
rtl838x_request_fw(struct phy_device *phydev, const struct firmware *fw,
const char *name)
static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
const struct firmware *fw,
const char *name)
{
struct device *dev = &phydev->mdio.dev;
int err;
@ -339,9 +234,9 @@ static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
read_phy(mac, 0, 0, &val);
if (val & (1 << 11))
rtl8380_int_phy_on_off(mac, true);
int_phy_on_off(mac, true);
else
rtl8380_phy_reset(mac);
phy_reset(mac);
msleep(100);
/* Ready PHY for patch */
@ -431,9 +326,9 @@ static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
read_phy(mac, 0, 0, &val);
if (val & (1 << 11))
rtl8380_int_phy_on_off(mac, true);
int_phy_on_off(mac, true);
else
rtl8380_phy_reset(mac);
phy_reset(mac);
msleep(100);
/* Get Chip revision */
@ -528,28 +423,100 @@ static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
return phydev->phy_id == PHY_ID_RTL8218B_E;
}
static int rtl8380_rtl8218b_write_mmd(struct phy_device *phydev,
int devnum, u16 regnum, u16 val)
/*
* Read an mmd register of the PHY
*/
static int rtl83xx_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
{
int addr = phydev->mdio.addr;
u32 v;
return rtl838x_write_mmd_phy(addr, devnum, regnum, val);
mutex_lock(&smi_lock);
if (rtl838x_smi_wait_op(10000))
goto timeout;
sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
mdelay(10);
sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
v = addr << 16 | reg;
sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
/* mmd-access | read | cmd-start */
v = 1 << 1 | 0 << 2 | 1;
sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
if (rtl838x_smi_wait_op(10000))
goto timeout;
*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
mutex_unlock(&smi_lock);
return 0;
timeout:
mutex_unlock(&smi_lock);
return -ETIMEDOUT;
}
static int rtl8380_rtl8218b_read_mmd(struct phy_device *phydev,
/*
* Write to an mmd register of the PHY
*/
static int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
{
u32 v;
pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
val &= 0xffff;
mutex_lock(&smi_lock);
if (rtl838x_smi_wait_op(10000))
goto timeout;
sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
mdelay(10);
sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
/* mmd-access | write | cmd-start */
v = 1 << 1 | 1 << 2 | 1;
sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
if (rtl838x_smi_wait_op(10000))
goto timeout;
mutex_unlock(&smi_lock);
return 0;
timeout:
mutex_unlock(&smi_lock);
return -ETIMEDOUT;
}
static int rtl8218b_read_mmd(struct phy_device *phydev,
int devnum, u16 regnum)
{
int ret;
u32 val;
int addr = phydev->mdio.addr;
ret = rtl838x_read_mmd_phy(addr, devnum, regnum, &val);
ret = rtl83xx_read_mmd_phy(addr, devnum, regnum, &val);
if (ret)
return ret;
return val;
}
static int rtl8218b_write_mmd(struct phy_device *phydev,
int devnum, u16 regnum, u16 val)
{
int addr = phydev->mdio.addr;
return rtl838x_write_mmd_phy(addr, devnum, regnum, val);
}
static void rtl8380_rtl8214fc_media_set(int mac, bool set_fibre)
{
int base = mac - (mac % 4);
@ -622,7 +589,7 @@ static bool rtl8380_rtl8214fc_media_is_fibre(int mac)
return true;
}
static int rtl8380_rtl8214fc_set_port(struct phy_device *phydev, int port)
static int rtl8214fc_set_port(struct phy_device *phydev, int port)
{
bool is_fibre = (port == PORT_FIBRE ? true : false);
int addr = phydev->mdio.addr;
@ -633,7 +600,7 @@ static int rtl8380_rtl8214fc_set_port(struct phy_device *phydev, int port)
return 0;
}
static int rtl8380_rtl8214fc_get_port(struct phy_device *phydev)
static int rtl8214fc_get_port(struct phy_device *phydev)
{
int addr = phydev->mdio.addr;
@ -643,12 +610,7 @@ static int rtl8380_rtl8214fc_get_port(struct phy_device *phydev)
return PORT_MII;
}
void rtl8380_rtl8214fc_ldps_set(int mac, struct ethtool_eee *e)
{
}
static void rtl8380_rtl8218b_eee_set_u_boot(int port, bool enable)
static void rtl8218b_eee_set_u_boot(int port, bool enable)
{
u32 val;
bool an_enabled;
@ -691,29 +653,8 @@ static void rtl8380_rtl8218b_eee_set_u_boot(int port, bool enable)
write_phy(port, 0xa42, 29, 0);
}
static int rtl8380_rtl8218b_get_eee_u_boot(struct phy_device *phydev, struct ethtool_eee *e)
{
u32 val;
int addr = phydev->mdio.addr;
pr_debug("In %s %d\n", __func__, addr);
/* Set GPHY page to copper */
write_phy(addr, 0xa42, 29, 0x0001);
read_phy(addr, 0xa43, 25, &val);
if (e->eee_enabled && (!!(val & (1 << 4))))
e->eee_enabled = !!(val & (1 << 4));
else
e->eee_enabled = 0;
/* GPHY page to auto */
write_phy(addr, 0xa42, 29, 0x0000);
return 0;
}
void rtl8380_rtl8218b_eee_set(int port, bool enable)
// TODO: unused
static void rtl8380_rtl8218b_eee_set(int port, bool enable)
{
u32 val;
bool an_enabled;
@ -755,7 +696,7 @@ void rtl8380_rtl8218b_eee_set(int port, bool enable)
write_phy(port, 0xa42, 29, 0);
}
int rtl8380_rtl8218b_get_eee(struct phy_device *phydev,
static int rtl8218b_get_eee(struct phy_device *phydev,
struct ethtool_eee *e)
{
u32 val;
@ -766,7 +707,7 @@ int rtl8380_rtl8218b_get_eee(struct phy_device *phydev,
/* Set GPHY page to copper */
write_phy(addr, 0xa42, 29, 0x0001);
rtl838x_read_mmd_phy(addr, 7, 60, &val);
rtl83xx_read_mmd_phy(addr, 7, 60, &val);
if (e->eee_enabled && (!!(val & (1 << 7))))
e->eee_enabled = !!(val & (1 << 7));
else
@ -778,7 +719,8 @@ int rtl8380_rtl8218b_get_eee(struct phy_device *phydev,
return 0;
}
void rtl8380_rtl8218b_green_set(int mac, bool enable)
// TODO: unused
static void rtl8380_rtl8218b_green_set(int mac, bool enable)
{
u32 val;
@ -801,7 +743,8 @@ void rtl8380_rtl8218b_green_set(int mac, bool enable)
write_phy(mac, 0xa42, 29, 0x0000);
}
int rtl8380_rtl8214fc_get_green(struct phy_device *phydev, struct ethtool_eee *e)
// TODO: unused
static int rtl8380_rtl8214fc_get_green(struct phy_device *phydev, struct ethtool_eee *e)
{
u32 val;
int addr = phydev->mdio.addr;
@ -823,8 +766,8 @@ int rtl8380_rtl8214fc_get_green(struct phy_device *phydev, struct ethtool_eee *e
return 0;
}
static int rtl8380_rtl8214fc_set_eee(struct phy_device *phydev,
struct ethtool_eee *e)
static int rtl8214fc_set_eee(struct phy_device *phydev,
struct ethtool_eee *e)
{
u32 pollMask;
int addr = phydev->mdio.addr;
@ -838,12 +781,12 @@ static int rtl8380_rtl8214fc_set_eee(struct phy_device *phydev,
pollMask = sw_r32(RTL838X_SMI_POLL_CTRL);
sw_w32(0, RTL838X_SMI_POLL_CTRL);
rtl8380_rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled);
rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled);
sw_w32(pollMask, RTL838X_SMI_POLL_CTRL);
return 0;
}
static int rtl8380_rtl8214fc_get_eee(struct phy_device *phydev,
static int rtl8214fc_get_eee(struct phy_device *phydev,
struct ethtool_eee *e)
{
int addr = phydev->mdio.addr;
@ -854,10 +797,10 @@ static int rtl8380_rtl8214fc_get_eee(struct phy_device *phydev,
return -ENOTSUPP;
}
return rtl8380_rtl8218b_get_eee_u_boot(phydev, e);
return rtl8218b_get_eee(phydev, e);
}
static int rtl8380_rtl8218b_set_eee(struct phy_device *phydev,
static int rtl8218b_set_eee(struct phy_device *phydev,
struct ethtool_eee *e)
{
u32 pollMask;
@ -867,7 +810,7 @@ static int rtl8380_rtl8218b_set_eee(struct phy_device *phydev,
pollMask = sw_r32(RTL838X_SMI_POLL_CTRL);
sw_w32(0, RTL838X_SMI_POLL_CTRL);
rtl8380_rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled);
rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled);
sw_w32(pollMask, RTL838X_SMI_POLL_CTRL);
return 0;
@ -943,9 +886,9 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
read_phy(mac, 0, 16, &val);
if (val & (1 << 11))
rtl8380_rtl8214fc_on_off(mac, true);
rtl8214fc_on_off(mac, true);
else
rtl8380_phy_reset(mac);
phy_reset(mac);
msleep(100);
write_phy(mac, 0, 30, 0x0001);
@ -1356,10 +1299,10 @@ static int rtl8390_serdes_probe(struct phy_device *phydev)
return rtl8390_configure_generic(phydev);
}
static struct phy_driver rtl838x_phy_driver[] = {
static struct phy_driver rtl83xx_phy_driver[] = {
{
PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
.name = "REALTEK RTL8214C",
.name = "Realtek RTL8214C",
.features = PHY_GBIT_FEATURES,
.match_phy_device = rtl8214c_match_phy_device,
.probe = rtl8214c_phy_probe,
@ -1369,62 +1312,62 @@ static struct phy_driver rtl838x_phy_driver[] = {
},
{
PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
.name = "REALTEK RTL8214FC",
.name = "Realtek RTL8214FC",
.features = PHY_GBIT_FIBRE_FEATURES,
.match_phy_device = rtl8214fc_match_phy_device,
.probe = rtl8214fc_phy_probe,
.suspend = genphy_suspend,
.resume = genphy_resume,
.set_loopback = genphy_loopback,
.read_mmd = rtl8380_rtl8218b_read_mmd,
.write_mmd = rtl8380_rtl8218b_write_mmd,
.set_port = rtl8380_rtl8214fc_set_port,
.get_port = rtl8380_rtl8214fc_get_port,
.set_eee = rtl8380_rtl8214fc_set_eee,
.get_eee = rtl8380_rtl8214fc_get_eee,
.read_mmd = rtl8218b_read_mmd,
.write_mmd = rtl8218b_write_mmd,
.set_port = rtl8214fc_set_port,
.get_port = rtl8214fc_get_port,
.set_eee = rtl8214fc_set_eee,
.get_eee = rtl8214fc_get_eee,
},
{
PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
.name = "REALTEK RTL8218B (external)",
.name = "Realtek RTL8218B (external)",
.features = PHY_GBIT_FEATURES,
.match_phy_device = rtl8218b_ext_match_phy_device,
.probe = rtl8218b_ext_phy_probe,
.suspend = genphy_suspend,
.resume = genphy_resume,
.set_loopback = genphy_loopback,
.read_mmd = rtl8380_rtl8218b_read_mmd,
.write_mmd = rtl8380_rtl8218b_write_mmd,
.set_eee = rtl8380_rtl8218b_set_eee,
.get_eee = rtl8380_rtl8218b_get_eee_u_boot,
.read_mmd = rtl8218b_read_mmd,
.write_mmd = rtl8218b_write_mmd,
.set_eee = rtl8218b_set_eee,
.get_eee = rtl8218b_get_eee,
},
{
PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
.name = "REALTEK RTL8218B (internal)",
.name = "Realtek RTL8218B (internal)",
.features = PHY_GBIT_FEATURES,
.probe = rtl8218b_int_phy_probe,
.suspend = genphy_suspend,
.resume = genphy_resume,
.set_loopback = genphy_loopback,
.read_mmd = rtl8380_rtl8218b_read_mmd,
.write_mmd = rtl8380_rtl8218b_write_mmd,
.set_eee = rtl8380_rtl8218b_set_eee,
.get_eee = rtl8380_rtl8218b_get_eee_u_boot,
.read_mmd = rtl8218b_read_mmd,
.write_mmd = rtl8218b_write_mmd,
.set_eee = rtl8218b_set_eee,
.get_eee = rtl8218b_get_eee,
},
{
PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
.name = "REALTEK RTL8380 SERDES",
.name = "Realtek RTL8380 SERDES",
.features = PHY_GBIT_FIBRE_FEATURES,
.probe = rtl838x_serdes_probe,
.suspend = genphy_suspend,
.resume = genphy_resume,
.set_loopback = genphy_loopback,
.read_mmd = rtl8380_rtl8218b_read_mmd,
.write_mmd = rtl8380_rtl8218b_write_mmd,
.read_mmd = rtl8218b_read_mmd,
.write_mmd = rtl8218b_write_mmd,
.read_status = rtl8380_read_status,
},
{
PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
.name = "REALTEK RTL8393 SERDES",
.name = "Realtek RTL8393 SERDES",
.features = PHY_GBIT_FIBRE_FEATURES,
.probe = rtl8393_serdes_probe,
.suspend = genphy_suspend,
@ -1434,7 +1377,7 @@ static struct phy_driver rtl838x_phy_driver[] = {
},
{
PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
.name = "REALTEK RTL8390 Generic",
.name = "Realtek RTL8390 Generic",
.features = PHY_GBIT_FIBRE_FEATURES,
.probe = rtl8390_serdes_probe,
.suspend = genphy_suspend,
@ -1443,15 +1386,15 @@ static struct phy_driver rtl838x_phy_driver[] = {
}
};
module_phy_driver(rtl838x_phy_driver);
module_phy_driver(rtl83xx_phy_driver);
static struct mdio_device_id __maybe_unused rtl838x_tbl[] = {
static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
{ PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
{ }
};
MODULE_DEVICE_TABLE(mdio, rtl838x_tbl);
MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
MODULE_AUTHOR("B. Koblitz");
MODULE_DESCRIPTION("RTL838x PHY driver");
MODULE_DESCRIPTION("RTL83xx PHY driver");
MODULE_LICENSE("GPL");

40
target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h Normal file
View File

@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0-only
// TODO: not really used
struct rtl838x_phy_priv {
char *name;
};
struct __attribute__ ((__packed__)) part {
uint16_t start;
uint8_t wordsize;
uint8_t words;
};
struct __attribute__ ((__packed__)) fw_header {
uint32_t magic;
uint32_t phy;
uint32_t checksum;
uint32_t version;
struct part parts[10];
};
// TODO: fixed path?
#define FIRMWARE_838X_8380_1 "rtl838x_phy/rtl838x_8380.fw"
#define FIRMWARE_838X_8214FC_1 "rtl838x_phy/rtl838x_8214fc.fw"
#define FIRMWARE_838X_8218b_1 "rtl838x_phy/rtl838x_8218b.fw"
/* External RTL8218B and RTL8214FC IDs are identical */
#define PHY_ID_RTL8214C 0x001cc942
#define PHY_ID_RTL8214FC 0x001cc981
#define PHY_ID_RTL8218B_E 0x001cc981
#define PHY_ID_RTL8218B_I 0x001cca40
#define PHY_ID_RTL8390_GENERIC 0x001ccab0
#define PHY_ID_RTL8393_I 0x001c8393
#define RTL839X_SDS12_13_XSG0 (0xB800)
#define RTL838X_SDS_MODE_SEL (0x0028)
#define RTL838X_SDS_CFG_REG (0x0034)
#define RTL838X_INT_MODE_CTRL (0x005c)
#define RTL838X_DMY_REG31 (0x3b28)

0
target/linux/rtl838x/files/firmware/rtl838x_phy/rtl838x_8214fc.fw → target/linux/realtek/files/firmware/rtl838x_phy/rtl838x_8214fc.fw
View File

0
target/linux/rtl838x/files/firmware/rtl838x_phy/rtl838x_8218b.fw → target/linux/realtek/files/firmware/rtl838x_phy/rtl838x_8218b.fw
View File

0
target/linux/rtl838x/files/firmware/rtl838x_phy/rtl838x_8380.fw → target/linux/realtek/files/firmware/rtl838x_phy/rtl838x_8380.fw
View File

0
target/linux/rtl838x/generic/target.mk → target/linux/realtek/generic/target.mk
View File

13
target/linux/rtl838x/image/Makefile → target/linux/realtek/image/Makefile
View File

@ -55,4 +55,17 @@ define Device/d-link_dgs-1210-28
DEVICE_MODEL := DGS-1210-28
endef
TARGET_DEVICES += d-link_dgs-1210-28
define Device/netgear_gs110tpp-v1
$(Device/Default)
SOC := rtl8380
IMAGE_SIZE := 14848k
UIMAGE_MAGIC := 0x4e474520
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := GS110TP
DEVICE_VARIANT := v1
DEVICE_PACKAGES := ip-full ip-bridge ethtool tc
endef
TARGET_DEVICES += netgear_gs110tpp-v1
$(eval $(call BuildImage))

21
target/linux/rtl838x/patches-5.4/300-mips-add-rtl838x-platform.patch → target/linux/realtek/patches-5.4/300-mips-add-rtl838x-platform.patch
View File

@ -1,5 +1,7 @@
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
Index: linux-5.4.77/arch/mips/Kbuild.platforms
===================================================================
--- linux-5.4.77.orig/arch/mips/Kbuild.platforms
+++ linux-5.4.77/arch/mips/Kbuild.platforms
@@ -27,6 +27,7 @@ platforms += pistachio
platforms += pmcs-msp71xx
platforms += pnx833x
@ -8,9 +10,11 @@
platforms += rb532
platforms += sgi-ip22
platforms += sgi-ip27
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -630,6 +630,29 @@ config RALINK
Index: linux-5.4.77/arch/mips/Kconfig
===================================================================
--- linux-5.4.77.orig/arch/mips/Kconfig
+++ linux-5.4.77/arch/mips/Kconfig
@@ -630,6 +630,26 @@ config RALINK
select ARCH_HAS_RESET_CONTROLLER
select RESET_CONTROLLER
@ -25,16 +29,13 @@
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_MIPS16
+ select SYS_SUPPORTS_MULTITHREADING
+ select SYS_SUPPORTS_VPE_LOADER
+ select SYS_HAS_EARLY_PRINTK
+ select SWAP_IO_SPACE
+ select SYS_HAS_EARLY_PRINTK_8250
+ select USE_GENERIC_EARLY_PRINTK_8250
+ select BOOT_RAW
+ select CLKDEV_LOOKUP
+ select PINCTRL
+ select ARCH_HAS_RESET_CONTROLLER
+ select RESET_CONTROLLER
+ select RTL8380_SERIES
+ select USE_OF
+
config SGI_IP22

11
target/linux/rtl838x/patches-5.4/301-gpio-add-rtl838x-driver.patch → target/linux/realtek/patches-5.4/301-gpio-add-rtl838x-driver.patch
View File

@ -1,9 +1,15 @@
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -441,6 +441,12 @@ config GPIO_REG
@@ -441,6 +441,18 @@ config GPIO_REG
A 32-bit single register GPIO fixed in/out implementation. This
can be used to represent any register as a set of GPIO signals.
+config GPIO_RTL8231
+ tristate "RTL8231 GPIO"
+ depends on GPIO_RTL838X
+ help
+ Say yes here to support Realtek RTL8231 GPIO expansion chips.
+
+config GPIO_RTL838X
+ tristate "RTL838X GPIO"
+ depends on RTL838X
@ -15,10 +21,11 @@
depends on MFD_SYSCON
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -117,6 +117,7 @@ obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t
@@ -117,6 +117,8 @@ obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t
obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
obj-$(CONFIG_GPIO_REG) += gpio-reg.o
+obj-$(CONFIG_GPIO_RTL8231) += gpio-rtl8231.o
+obj-$(CONFIG_GPIO_RTL838X) += gpio-rtl838x.o
obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o

0
target/linux/rtl838x/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch → target/linux/realtek/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch
View File

22
target/linux/realtek/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch Normal file
View File

@ -0,0 +1,22 @@
Index: linux-5.4.77/drivers/net/dsa/Kconfig
===================================================================
--- linux-5.4.77.orig/drivers/net/dsa/Kconfig
+++ linux-5.4.77/drivers/net/dsa/Kconfig
@@ -63,6 +63,8 @@ config NET_DSA_QCA8K
This enables support for the Qualcomm Atheros QCA8K Ethernet
switch chips.
+source "drivers/net/dsa/rtl83xx/Kconfig"
+
config NET_DSA_REALTEK_SMI
tristate "Realtek SMI Ethernet switch family support"
depends on NET_DSA
Index: linux-5.4.77/drivers/net/dsa/Makefile
===================================================================
--- linux-5.4.77.orig/drivers/net/dsa/Makefile
+++ linux-5.4.77/drivers/net/dsa/Makefile
@@ -21,3 +21,4 @@ obj-y += b53/
obj-y += microchip/
obj-y += mv88e6xxx/
obj-y += sja1105/
+obj-y += rtl83xx/

12
target/linux/rtl838x/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch → target/linux/realtek/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch
View File

@ -1,15 +1,17 @@
--- a/net/dsa/tag_trailer.c
+++ b/net/dsa/tag_trailer.c
Index: linux-5.4.77/net/dsa/tag_trailer.c
===================================================================
--- linux-5.4.77.orig/net/dsa/tag_trailer.c
+++ linux-5.4.77/net/dsa/tag_trailer.c
@@ -44,7 +44,12 @@ static struct sk_buff *trailer_xmit(stru
trailer = skb_put(nskb, 4);
trailer[0] = 0x80;
+
+#ifdef CONFIG_NET_DSA_RTL838X
+#ifdef CONFIG_NET_DSA_RTL83XX
+ trailer[1] = dp->index;
+#else
trailer[1] = 1 << dp->index;
+#endif /* CONFIG_NET_DSA_RTL838X */
+#endif /* CONFIG_NET_DSA_RTL83XX */
trailer[2] = 0x10;
trailer[3] = 0x00;
@ -18,7 +20,7 @@
trailer = skb_tail_pointer(skb) - 4;
+
+#ifdef CONFIG_NET_DSA_RTL838X
+#ifdef CONFIG_NET_DSA_RTL83XX
+ if (trailer[0] != 0x80 || (trailer[1] & 0xe0) != 0x00 ||
+ (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00)
+ return NULL;

0
target/linux/rtl838x/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch → target/linux/realtek/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch
View File

0
target/linux/rtl838x/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch → target/linux/realtek/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch
View File

0
target/linux/rtl838x/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch → target/linux/realtek/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch
View File

0
target/linux/rtl838x/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch → target/linux/realtek/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch
View File

13
target/linux/realtek/patches-5.4/705-add-rtl-phy.patch Normal file
View File

@ -0,0 +1,13 @@
Index: linux-5.4.77/drivers/net/phy/Makefile
===================================================================
--- linux-5.4.77.orig/drivers/net/phy/Makefile
+++ linux-5.4.77/drivers/net/phy/Makefile
@@ -101,7 +101,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
-obj-$(CONFIG_REALTEK_PHY) += realtek.o
+obj-$(CONFIG_REALTEK_PHY) += realtek.o rtl83xx-phy.o
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
obj-$(CONFIG_SMSC_PHY) += smsc.o

11
target/linux/realtek/patches-5.4/705-include-linux-phy-increase-phy-address-number-for-rtl839x.patch Normal file
View File

@ -0,0 +1,11 @@
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -188,7 +188,7 @@
#define PHY_INIT_TIMEOUT 100000
#define PHY_FORCE_TIMEOUT 10
-#define PHY_MAX_ADDR 32
+#define PHY_MAX_ADDR 64
/* Used when trying to connect to a specific phy (mii bus id:phy device id) */
#define PHY_ID_FMT "%s:%02x"

0
target/linux/rtl838x/profiles/00-default.mk → target/linux/realtek/profiles/00-default.mk
View File

10
target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h
View File

@ -1,10 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __ASM_MACH_RTL838X_IRQ_H
#define __ASM_MACH_RTL838X_IRQ_H
#define MIPS_CPU_IRQ_BASE 0
#define NR_IRQS 64
#include_next <irq.h>
#endif /* __ASM_MACH_ATH79_IRQ_H */

203
target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c
View File

@ -1,203 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Realtek RTL838X architecture specific IRQ handling
*
* Copyright (C) 2020 B. Koblitz
* based on the original BSP
* Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/spinlock.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <mach-rtl838x.h>
#define icu_r32(reg) rtl838x_r32(soc_info.icu_base + reg)
#define icu_w32(val, reg) rtl838x_w32(val, soc_info.icu_base + reg)
#define icu_w32_mask(clear, set, reg) rtl838x_w32_mask(clear, set, soc_info.icu_base + reg)
static DEFINE_RAW_SPINLOCK(irq_lock);
extern irqreturn_t c0_compare_interrupt(int irq, void *dev_id);
static void rtl838x_ictl_enable_irq(struct irq_data *i)
{
unsigned long flags;
raw_spin_lock_irqsave(&irq_lock, flags);
icu_w32_mask(0, 1 << i->irq, GIMR);
raw_spin_unlock_irqrestore(&irq_lock, flags);
}
static void rtl838x_ictl_disable_irq(struct irq_data *i)
{
unsigned long flags;
raw_spin_lock_irqsave(&irq_lock, flags);
icu_w32_mask(1 << i->irq, 0, GIMR);
raw_spin_unlock_irqrestore(&irq_lock, flags);
}
static void rtl838x_ictl_eoi_irq(struct irq_data *i)
{
unsigned long flags;
raw_spin_lock_irqsave(&irq_lock, flags);
icu_w32_mask(0, 1 << i->irq, GIMR);
raw_spin_unlock_irqrestore(&irq_lock, flags);
}
static struct irq_chip rtl838x_ictl_irq = {
.name = "RTL83xx",
.irq_enable = rtl838x_ictl_enable_irq,
.irq_disable = rtl838x_ictl_disable_irq,
.irq_ack = rtl838x_ictl_disable_irq,
.irq_mask = rtl838x_ictl_disable_irq,
.irq_unmask = rtl838x_ictl_enable_irq,
.irq_eoi = rtl838x_ictl_eoi_irq,
};
/*
* RTL8390/80/28 Interrupt Scheme
*
* Source IRQ CPU INT
* -------- ------- -------
* UART0 31 IP3
* UART1 30 IP2
* TIMER0 29 IP6
* TIMER1 28 IP2
* OCPTO 27 IP2
* HLXTO 26 IP2
* SLXTO 25 IP2
* NIC 24 IP5
* GPIO_ABCD 23 IP5
* SWCORE 20 IP4
*/
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending, ext_int;
pending = read_c0_cause();
if (pending & CAUSEF_IP7) {
c0_compare_interrupt(7, NULL);
} else if (pending & CAUSEF_IP6) {
do_IRQ(TC0_IRQ);
} else if (pending & CAUSEF_IP5) {
ext_int = icu_r32(GIMR) & icu_r32(GISR);
if (ext_int & NIC_IP)
do_IRQ(NIC_IRQ);
else if (ext_int & GPIO_ABCD_IP)
do_IRQ(GPIO_ABCD_IRQ);
else if ((ext_int & GPIO_EFGH_IP) && (soc_info.family == RTL8328_FAMILY_ID))
do_IRQ(GPIO_EFGH_IRQ);
else
spurious_interrupt();
} else if (pending & CAUSEF_IP4) {
do_IRQ(SWCORE_IRQ);
} else if (pending & CAUSEF_IP3) {
do_IRQ(UART0_IRQ);
} else if (pending & CAUSEF_IP2) {
ext_int = icu_r32(GIMR) & icu_r32(GISR);
if (ext_int & TC1_IP)
do_IRQ(TC1_IRQ);
else if (ext_int & UART1_IP)
do_IRQ(UART1_IRQ);
else
spurious_interrupt();
} else {
spurious_interrupt();
}
}
static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
{
irq_set_chip_and_handler(hw, &rtl838x_ictl_irq, handle_level_irq);
return 0;
}
static const struct irq_domain_ops irq_domain_ops = {
.xlate = irq_domain_xlate_onecell,
.map = intc_map,
};
int __init icu_of_init(struct device_node *node, struct device_node *parent)
{
int i;
struct irq_domain *domain;
struct resource res;
pr_info("Found Interrupt controller: %s (%s)\n", node->name, node->full_name);
if (of_address_to_resource(node, 0, &res))
panic("Failed to get icu memory range");
if (!request_mem_region(res.start, resource_size(&res), res.name))
pr_err("Failed to request icu memory\n");
soc_info.icu_base = ioremap(res.start, resource_size(&res));
pr_info("ICU Memory: %08x\n", (u32)soc_info.icu_base);
mips_cpu_irq_init();
domain = irq_domain_add_simple(node, 32, 0, &irq_domain_ops, NULL);
/* Setup all external HW irqs */
for (i = 8; i < RTL838X_IRQ_ICTL_NUM; i++) {
irq_domain_associate(domain, i, i);
irq_set_chip_and_handler(RTL838X_IRQ_ICTL_BASE + i,
&rtl838x_ictl_irq, handle_level_irq);
}
if (request_irq(RTL838X_ICTL1_IRQ, no_action, IRQF_NO_THREAD,
"IRQ cascade 1", NULL)) {
pr_err("request_irq() cascade 1 for irq %d failed\n", RTL838X_ICTL1_IRQ);
}
if (request_irq(RTL838X_ICTL2_IRQ, no_action, IRQF_NO_THREAD,
"IRQ cascade 2", NULL)) {
pr_err("request_irq() cascade 2 for irq %d failed\n", RTL838X_ICTL2_IRQ);
}
if (request_irq(RTL838X_ICTL3_IRQ, no_action, IRQF_NO_THREAD,
"IRQ cascade 3", NULL)) {
pr_err("request_irq() cascade 3 for irq %d failed\n", RTL838X_ICTL3_IRQ);
}
if (request_irq(RTL838X_ICTL4_IRQ, no_action, IRQF_NO_THREAD,
"IRQ cascade 4", NULL)) {
pr_err("request_irq() cascade 4 for irq %d failed\n", RTL838X_ICTL4_IRQ);
}
if (request_irq(RTL838X_ICTL5_IRQ, no_action, IRQF_NO_THREAD,
"IRQ cascade 5", NULL)) {
pr_err("request_irq() cascade 5 for irq %d failed\n", RTL838X_ICTL5_IRQ);
}
/* Set up interrupt routing scheme */
icu_w32(IRR0_SETTING, IRR0);
if (soc_info.family == RTL8380_FAMILY_ID)
icu_w32(IRR1_SETTING_RTL838X, IRR1);
else
icu_w32(IRR1_SETTING_RTL839X, IRR1);
icu_w32(IRR2_SETTING, IRR2);
icu_w32(IRR3_SETTING, IRR3);
/* Enable timer0 and uart0 interrupts */
icu_w32(TC0_IE | UART0_IE, GIMR);
return 0;
}
void __init arch_init_irq(void)
{
/* do board-specific irq initialization */
irqchip_init();
}
IRQCHIP_DECLARE(mips_cpu_intc, "rtl838x,icu", icu_of_init);

100
target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c
View File

@ -1,100 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* 8250 serial console setup for the Realtek RTL838X SoC
*
* based on the original BSP by
* Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
*
* Copyright (C) 2020 B. Koblitz
*
*/
#include <linux/types.h>
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/version.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/tty.h>
#include <linux/clk.h>
#include <asm/mach-rtl838x/mach-rtl838x.h>
extern char arcs_cmdline[];
int __init rtl838x_serial_init(void)
{
#ifdef CONFIG_SERIAL_8250
int ret;
struct uart_port p;
unsigned long baud = 0;
int err;
char parity = '\0', bits = '\0', flow = '\0';
char *s;
struct device_node *dn;
dn = of_find_compatible_node(NULL, NULL, "ns16550a");
if (dn) {
pr_info("Found NS16550a: %s (%s)\n", dn->name, dn->full_name);
dn = of_find_compatible_node(dn, NULL, "ns16550a");
if (dn && of_device_is_available(dn) && soc_info.family == RTL8380_FAMILY_ID) {
/* Enable UART1 on RTL838x */
pr_info("Enabling uart1\n");
sw_w32(0x10, RTL838X_GMII_INTF_SEL);
}
} else {
pr_err("No NS16550a UART found!");
return -ENODEV;
}
s = strstr(arcs_cmdline, "console=ttyS0,");
if (s) {
s += 14;
err = kstrtoul(s, 10, &baud);
if (err)
baud = 0;
while (isdigit(*s))
s++;
if (*s == ',')
s++;
if (*s)
parity = *s++;
if (*s == ',')
s++;
if (*s)
bits = *s++;
if (*s == ',')
s++;
if (*s == 'h')
flow = 'r';
}
if (baud == 0) {
baud = 38400;
pr_warn("Using default baud rate: %lu\n", baud);
}
if (parity != 'n' && parity != 'o' && parity != 'e')
parity = 'n';
if (bits != '7' && bits != '8')
bits = '8';
memset(&p, 0, sizeof(p));
p.type = PORT_16550A;
p.membase = (unsigned char *) RTL838X_UART0_BASE;
p.irq = RTL838X_UART0_IRQ;
p.uartclk = SYSTEM_FREQ - (24 * baud);
p.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY | UPF_FIXED_TYPE;
p.iotype = UPIO_MEM;
p.regshift = 2;
p.fifosize = 1;
/* Call early_serial_setup() here, to set up 8250 console driver */
if (early_serial_setup(&p) != 0)
ret = 1;
#endif
return 0;
}

806
target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c
View File

@ -1,806 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <asm/mach-rtl838x/mach-rtl838x.h>
/* RTL8231 registers for LED control */
#define RTL8231_LED_FUNC0 0x0000
#define RTL8231_GPIO_PIN_SEL(gpio) ((0x0002) + ((gpio) >> 4))
#define RTL8231_GPIO_DIR(gpio) ((0x0005) + ((gpio) >> 4))
#define RTL8231_GPIO_DATA(gpio) ((0x001C) + ((gpio) >> 4))
#define RTL8231_GPIO_PIN_SEL0 0x0002
#define RTL8231_GPIO_PIN_SEL1 0x0003
#define RTL8231_GPIO_PIN_SEL2 0x0004
#define RTL8231_GPIO_IO_SEL0 0x0005
#define RTL8231_GPIO_IO_SEL1 0x0006
#define RTL8231_GPIO_IO_SEL2 0x0007
#define MDC_WAIT { int i; for (i = 0; i < 2; i++); }
#define I2C_WAIT { int i; for (i = 0; i < 5; i++); }
struct rtl838x_gpios {
struct gpio_chip gc;
u32 id;
struct device *dev;
int irq;
int bus_id;
int num_leds;
int min_led;
int leds_per_port;
u32 led_mode;
u16 rtl8381_phy_id;
int smi_clock;
int smi_data;
int i2c_sda;
int i2c_sdc;
};
u32 rtl838x_rtl8231_read(u8 bus_id, u32 reg)
{
u32 t = 0;
reg &= 0x1f;
bus_id &= 0x1f;
/* Calculate read register address */
t = (bus_id << 2) | (reg << 7);
mutex_lock(&smi_lock);
/* Set execution bit: cleared when operation completed */
t |= 1;
sw_w32(t, RTL838X_EXT_GPIO_INDRT_ACCESS);
do { /* TODO: Return 0x80000000 if timeout */
t = sw_r32(RTL838X_EXT_GPIO_INDRT_ACCESS);
} while (t & 1);
pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, (t & 0xffff0000) >> 16);
mutex_unlock(&smi_lock);
return (t & 0xffff0000) >> 16;
}
int rtl838x_rtl8231_write(u8 bus_id, u32 reg, u32 data)
{
u32 t = 0;
pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, data);
data &= 0xffff;
reg &= 0x1f;
bus_id &= 0x1f;
mutex_lock(&smi_lock);
t = (bus_id << 2) | (reg << 7) | (data << 16);
/* Set write bit */
t |= 2;
/* Set execution bit: cleared when operation completed */
t |= 1;
sw_w32(t, RTL838X_EXT_GPIO_INDRT_ACCESS);
do { /* TODO: Return -1 if timeout */
t = sw_r32(RTL838X_EXT_GPIO_INDRT_ACCESS);
} while (t & 1);
mutex_unlock(&smi_lock);
return 0;
}
static int rtl8231_pin_dir(u8 bus_id, u32 gpio, u32 dir)
{
/* dir 1: input
* dir 0: output
*/
u32 v;
int pin_sel_addr = RTL8231_GPIO_PIN_SEL(gpio);
int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
int pin = gpio % 16;
int dpin = pin;
if (gpio > 31) {
dpin = pin << 5;
pin_dir_addr = pin_sel_addr;
}
/* Select GPIO function for pin */
v = rtl838x_rtl8231_read(bus_id, pin_sel_addr);
if (v & 0x80000000) {
pr_err("Error reading RTL8231\n");
return -1;
}
rtl838x_rtl8231_write(bus_id, pin_sel_addr, v | (1 << pin));
v = rtl838x_rtl8231_read(bus_id, pin_dir_addr);
if (v & 0x80000000) {
pr_err("Error reading RTL8231\n");
return -1;
}
rtl838x_rtl8231_write(bus_id, pin_dir_addr,
(v & ~(1 << dpin)) | (dir << dpin));
return 0;
}
static int rtl8231_pin_dir_get(u8 bus_id, u32 gpio, u32 *dir)
{
/* dir 1: input
* dir 0: output
*/
u32 v;
int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
int pin = gpio % 16;
if (gpio > 31) {
pin_dir_addr = RTL8231_GPIO_PIN_SEL(gpio);
pin = pin << 5;
}
v = rtl838x_rtl8231_read(bus_id, pin_dir_addr);
if (v & (1 << pin))
*dir = 1;
else
*dir = 0;
return 0;
}
static int rtl8231_pin_set(u8 bus_id, u32 gpio, u32 data)
{
u32 v = rtl838x_rtl8231_read(bus_id, RTL8231_GPIO_DATA(gpio));
if (v & 0x80000000) {
pr_err("Error reading RTL8231\n");
return -1;
}
rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_DATA(gpio),
(v & ~(1 << (gpio % 16))) | (data << (gpio % 16)));
return 0;
}
static int rtl8231_pin_get(u8 bus_id, u32 gpio, u16 *state)
{
u32 v = rtl838x_rtl8231_read(bus_id, RTL8231_GPIO_DATA(gpio));
if (v & 0x80000000) {
pr_err("Error reading RTL8231\n");
return -1;
}
*state = v & 0xffff;
return 0;
}
static int rtl838x_direction_input(struct gpio_chip *gc, unsigned int offset)
{
struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
pr_debug("%s: %d\n", __func__, offset);
if (offset < 32) {
rtl838x_w32_mask(1 << offset, 0, RTL838X_GPIO_PABC_DIR);
return 0;
}
/* Internal LED driver does not support input */
if (offset >= 32 && offset < 64)
return -ENOTSUPP;
if (offset >= 64 && offset < 100 && gpios->bus_id >= 0)
return rtl8231_pin_dir(gpios->bus_id, offset - 64, 1);
return -ENOTSUPP;
}
static int rtl838x_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
{
struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
pr_debug("%s: %d\n", __func__, offset);
if (offset < 32)
rtl838x_w32_mask(0, 1 << offset, RTL838X_GPIO_PABC_DIR);
/* LED for PWR and SYS driver is direction output by default */
if (offset >= 32 && offset < 64)
return 0;
if (offset >= 64 && offset < 100 && gpios->bus_id >= 0)
return rtl8231_pin_dir(gpios->bus_id, offset - 64, 0);
return 0;
}
static int rtl838x_get_direction(struct gpio_chip *gc, unsigned int offset)
{
u32 v = 0;
struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
pr_debug("%s: %d\n", __func__, offset);
if (offset < 32) {
v = rtl838x_r32(RTL838X_GPIO_PABC_DIR);
if (v & (1 << offset))
return 0;
return 1;
}
/* LED driver for PWR and SYS is direction output by default */
if (offset >= 32 && offset < 64)
return 0;
if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) {
rtl8231_pin_dir_get(gpios->bus_id, offset - 64, &v);
return v;
}
return 0;
}
static int rtl838x_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
u32 v;
u16 state = 0;
int bit;
struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
pr_debug("%s: %d\n", __func__, offset);
/* Internal GPIO of the RTL8380 */
if (offset < 32) {
v = rtl838x_r32(RTL838X_GPIO_PABC_DATA);
if (v & (1 << offset))
return 1;
return 0;
}
/* LED driver for PWR and SYS */
if (offset >= 32 && offset < 64) {
v = sw_r32(RTL838X_LED_GLB_CTRL);
if (v & (1 << (offset-32)))
return 1;
return 0;
}
/* Indirect access GPIO with RTL8231 */
if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) {
rtl8231_pin_get(gpios->bus_id, offset - 64, &state);
if (state & (1 << (offset % 16)))
return 1;
return 0;
}
bit = (offset - 100) % 32;
if (offset >= 100 && offset < 132) {
if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit))
return 1;
return 0;
}
if (offset >= 132 && offset < 164) {
if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit))
return 1;
return 0;
}
if (offset >= 164 && offset < 196) {
if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit))
return 1;
return 0;
}
return 0;
}
void rtl838x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
{
int bit;
struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
pr_debug("rtl838x_set: %d, value: %d\n", offset, value);
/* Internal GPIO of the RTL8380 */
if (offset < 32) {
if (value)
rtl838x_w32_mask(0, 1 << offset, RTL838X_GPIO_PABC_DATA);
else
rtl838x_w32_mask(1 << offset, 0, RTL838X_GPIO_PABC_DATA);
}
/* LED driver for PWR and SYS */
if (offset >= 32 && offset < 64) {
bit = offset - 32;
if (value)
sw_w32_mask(0, 1 << bit, RTL838X_LED_GLB_CTRL);
else
sw_w32_mask(1 << bit, 0, RTL838X_LED_GLB_CTRL);
return;
}
/* Indirect access GPIO with RTL8231 */
if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) {
rtl8231_pin_set(gpios->bus_id, offset - 64, value);
return;
}
bit = (offset - 100) % 32;
/* First Port-LED */
if (offset >= 100 && offset < 132
&& offset >= (100 + gpios->min_led)
&& offset < (100 + gpios->min_led + gpios->num_leds)) {
if (value)
sw_w32_mask(7, 5, RTL838X_LED_SW_P_CTRL(bit));
else
sw_w32_mask(7, 0, RTL838X_LED_SW_P_CTRL(bit));
}
if (offset >= 132 && offset < 164
&& offset >= (132 + gpios->min_led)
&& offset < (132 + gpios->min_led + gpios->num_leds)) {
if (value)
sw_w32_mask(7 << 3, 5 << 3, RTL838X_LED_SW_P_CTRL(bit));
else
sw_w32_mask(7 << 3, 0, RTL838X_LED_SW_P_CTRL(bit));
}
if (offset >= 164 && offset < 196
&& offset >= (164 + gpios->min_led)
&& offset < (164 + gpios->min_led + gpios->num_leds)) {
if (value)
sw_w32_mask(7 << 6, 5 << 6, RTL838X_LED_SW_P_CTRL(bit));
else
sw_w32_mask(7 << 6, 0, RTL838X_LED_SW_P_CTRL(bit));
}
__asm__ volatile ("sync");
}
int rtl8231_init(struct rtl838x_gpios *gpios)
{
uint32_t v;
u8 bus_id = gpios->bus_id;
pr_info("%s called\n", __func__);
/* Enable RTL8231 indirect access mode */
sw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL);
sw_w32_mask(3, 1, RTL838X_DMY_REG5);
/* Enable RTL8231 via GPIO_A1 line */
rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DIR);
rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DATA);
mdelay(50); /* wait 50ms for reset */
/*Select GPIO functionality for pins 0-15, 16-31 and 32-37 */
rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL(0), 0xffff);
rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL(16), 0xffff);
rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL2, 0x03ff);
v = rtl838x_rtl8231_read(bus_id, RTL8231_LED_FUNC0);
pr_info("RTL8231 led function now: %x\n", v);
return 0;
}
static void smi_write_bit(struct rtl838x_gpios *gpios, u32 bit)
{
if (bit)
rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DATA);
else
rtl838x_w32_mask(1 << gpios->smi_data, 0, RTL838X_GPIO_PABC_DATA);
MDC_WAIT;
rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA);
MDC_WAIT;
rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA);
}
static int smi_read_bit(struct rtl838x_gpios *gpios)
{
u32 v;
MDC_WAIT;
rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA);
MDC_WAIT;
rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA);
v = rtl838x_r32(RTL838X_GPIO_PABC_DATA);
if (v & (1 << gpios->smi_data))
return 1;
return 0;
}
/* Tri-state of MDIO line */
static void smi_z(struct rtl838x_gpios *gpios)
{
/* MDIO pin to input */
rtl838x_w32_mask(1 << gpios->smi_data, 0, RTL838X_GPIO_PABC_DIR);
MDC_WAIT;
rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA);
MDC_WAIT;
rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA);
}
static void smi_write_bits(struct rtl838x_gpios *gpios, u32 data, int len)
{
while (len) {
len--;
smi_write_bit(gpios, data & (1 << len));
}
}
static void smi_read_bits(struct rtl838x_gpios *gpios, int len, u32 *data)
{
u32 v = 0;
while (len) {
len--;
v <<= 1;
v |= smi_read_bit(gpios);
}
*data = v;
}
/* Bit-banged verson of SMI write access, caller must hold smi_lock */
int rtl8380_smi_write(struct rtl838x_gpios *gpios, u16 reg, u32 data)
{
u16 bus_id = gpios->bus_id;
/* Set clock and data pins on RTL838X to output */
rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DIR);
rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DIR);
/* Write start bits */
smi_write_bits(gpios, 0xffffffff, 32);
smi_write_bits(gpios, 0x5, 4); /* ST and write OP */
smi_write_bits(gpios, bus_id, 5); /* 5 bits: phy address */
smi_write_bits(gpios, reg, 5); /* 5 bits: register address */
smi_write_bits(gpios, 0x2, 2); /* TURNAROUND */
smi_write_bits(gpios, data, 16); /* 16 bits: data*/
smi_z(gpios);
return 0;
}
/* Bit-banged verson of SMI read access, caller must hold smi_lock */
int rtl8380_smi_read(struct rtl838x_gpios *gpios, u16 reg, u32 *data)
{
u16 bus_id = gpios->bus_id;
/* Set clock and data pins on RTL838X to output */
rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DIR);
rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DIR);
/* Write start bits */
smi_write_bits(gpios, 0xffffffff, 32);
smi_write_bits(gpios, 0x6, 4); /* ST and read OP */
smi_write_bits(gpios, bus_id, 5); /* 5 bits: phy address */
smi_write_bits(gpios, reg, 5); /* 5 bits: register address */
smi_z(gpios); /* TURNAROUND */
smi_read_bits(gpios, 16, data);
return 0;
}
static void i2c_pin_set(struct rtl838x_gpios *gpios, int pin, u32 data)
{
u32 v;
rtl8380_smi_read(gpios, RTL8231_GPIO_DATA(pin), &v);
if (!data)
v &= ~(1 << (pin % 16));
else
v |= (1 << (pin % 16));
rtl8380_smi_write(gpios, RTL8231_GPIO_DATA(pin), v);
}
static void i2c_pin_get(struct rtl838x_gpios *gpios, int pin, u32 *data)
{
u32 v;
rtl8380_smi_read(gpios, RTL8231_GPIO_DATA(pin), &v);
if (v & (1 << (pin % 16))) {
*data = 1;
return;
}
*data = 0;
}
static void i2c_pin_dir(struct rtl838x_gpios *gpios, int pin, u16 direction)
{
u32 v;
rtl8380_smi_read(gpios, RTL8231_GPIO_DIR(pin), &v);
if (direction) // Output
v &= ~(1 << (pin % 16));
else
v |= (1 << (pin % 16));
rtl8380_smi_write(gpios, RTL8231_GPIO_DIR(pin), v);
}
static void i2c_start(struct rtl838x_gpios *gpios)
{
i2c_pin_dir(gpios, gpios->i2c_sda, 0); /* Output */
i2c_pin_dir(gpios, gpios->i2c_sdc, 0); /* Output */
I2C_WAIT;
i2c_pin_set(gpios, gpios->i2c_sdc, 1);
I2C_WAIT;
i2c_pin_set(gpios, gpios->i2c_sda, 1);
I2C_WAIT;
i2c_pin_set(gpios, gpios->i2c_sda, 0);
I2C_WAIT;
i2c_pin_set(gpios, gpios->i2c_sdc, 0);
I2C_WAIT;
}
static void i2c_stop(struct rtl838x_gpios *gpios)
{
I2C_WAIT;
i2c_pin_set(gpios, gpios->i2c_sdc, 1);
i2c_pin_set(gpios, gpios->i2c_sda, 0);
I2C_WAIT;
i2c_pin_set(gpios, gpios->i2c_sda, 1);
I2C_WAIT;
i2c_pin_set(gpios, gpios->i2c_sdc, 0);
i2c_pin_dir(gpios, gpios->i2c_sda, 1); /* Input */
i2c_pin_dir(gpios, gpios->i2c_sdc, 1); /* Input */
}
static void i2c_read_bits(struct rtl838x_gpios *gpios, int len, u32 *data)
{
u32 v = 0, t;
while (len) {
len--;
v <<= 1;
i2c_pin_set(gpios, gpios->i2c_sdc, 1);
I2C_WAIT;
i2c_pin_get(gpios, gpios->i2c_sda, &t);
v |= t;
i2c_pin_set(gpios, gpios->i2c_sdc, 0);
I2C_WAIT;
}
*data = v;
}
static void i2c_write_bits(struct rtl838x_gpios *gpios, u32 data, int len)
{
while (len) {
len--;
i2c_pin_set(gpios, gpios->i2c_sda, data & (1 << len));
I2C_WAIT;
i2c_pin_set(gpios, gpios->i2c_sdc, 1);
I2C_WAIT;
i2c_pin_set(gpios, gpios->i2c_sdc, 0);
I2C_WAIT;
}
}
/* This initializes direct external GPIOs via the RTL8231 */
int rtl8380_rtl8321_init(struct rtl838x_gpios *gpios)
{
u32 v;
int mdc = gpios->smi_clock;
int mdio = gpios->smi_data;
pr_info("Configuring SMI: Clock %d, Data %d\n", mdc, mdio);
sw_w32_mask(0, 0x2, RTL838X_IO_DRIVING_ABILITY_CTRL);
/* Enter simulated GPIO mode */
sw_w32_mask(1, 0, RTL838X_EXTRA_GPIO_CTRL);
/* MDIO clock to 2.6MHz */
sw_w32_mask(0x3 << 8, 0, RTL838X_EXTRA_GPIO_CTRL);
/* Configure SMI clock and data GPIO pins */
rtl838x_w32_mask((1 << mdc) | (1 << mdio), 0, RTL838X_GPIO_PABC_CNR);
rtl838x_w32_mask(0, (1 << mdc) | (1 << mdio), RTL838X_GPIO_PABC_DIR);
rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL0, 0xffff);
rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL1, 0xffff);
rtl8380_smi_read(gpios, RTL8231_GPIO_PIN_SEL2, &v);
v |= 0x1f;
rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL2, v);
rtl8380_smi_write(gpios, RTL8231_GPIO_IO_SEL0, 0xffff);
rtl8380_smi_write(gpios, RTL8231_GPIO_IO_SEL1, 0xffff);
rtl8380_smi_read(gpios, RTL8231_GPIO_IO_SEL2, &v);
v |= 0x1f << 5;
rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL2, v);
return 0;
}
void rtl8380_led_test(u32 mask)
{
int i;
u32 mode_sel = sw_r32(RTL838X_LED_MODE_SEL);
u32 led_gbl = sw_r32(RTL838X_LED_GLB_CTRL);
u32 led_p_en = sw_r32(RTL838X_LED_P_EN_CTRL);
/* 2 Leds for ports 0-23 and 24-27, 3 would be 0x7 */
sw_w32_mask(0x3f, 0x3 | (0x3 << 3), RTL838X_LED_GLB_CTRL);
/* Enable all leds */
sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
/* Enable software control of all leds */
sw_w32(0xFFFFFFF, RTL838X_LED_SW_CTRL);
sw_w32(0xFFFFFFF, RTL838X_LED0_SW_P_EN_CTRL);
sw_w32(0xFFFFFFF, RTL838X_LED1_SW_P_EN_CTRL);
sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL);
for (i = 0; i < 28; i++) {
if (mask & (1 << i))
sw_w32(5 | (5 << 3) | (5 << 6),
RTL838X_LED_SW_P_CTRL(i));
}
msleep(3000);
sw_w32(led_p_en, RTL838X_LED_P_EN_CTRL);
/* Disable software control of all leds */
sw_w32(0x0000000, RTL838X_LED_SW_CTRL);
sw_w32(0x0000000, RTL838X_LED0_SW_P_EN_CTRL);
sw_w32(0x0000000, RTL838X_LED1_SW_P_EN_CTRL);
sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL);
sw_w32(led_gbl, RTL838X_LED_GLB_CTRL);
sw_w32(mode_sel, RTL838X_LED_MODE_SEL);
}
void take_port_leds(struct rtl838x_gpios *gpios)
{
int leds_per_port = gpios->leds_per_port;
int mode = gpios->led_mode;
pr_info("%s, %d, %x\n", __func__, leds_per_port, mode);
pr_debug("Bootloader settings: %x %x %x\n",
sw_r32(RTL838X_LED0_SW_P_EN_CTRL),
sw_r32(RTL838X_LED1_SW_P_EN_CTRL),
sw_r32(RTL838X_LED2_SW_P_EN_CTRL)
);
pr_debug("led glb: %x, sel %x\n",
sw_r32(RTL838X_LED_GLB_CTRL), sw_r32(RTL838X_LED_MODE_SEL));
pr_debug("RTL838X_LED_P_EN_CTRL: %x", sw_r32(RTL838X_LED_P_EN_CTRL));
pr_debug("RTL838X_LED_MODE_CTRL: %x", sw_r32(RTL838X_LED_MODE_CTRL));
sw_w32_mask(3, 0, RTL838X_LED_MODE_SEL);
sw_w32(mode, RTL838X_LED_MODE_CTRL);
/* Enable software control of all leds */
sw_w32(0xFFFFFFF, RTL838X_LED_SW_CTRL);
sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
sw_w32(0x0000000, RTL838X_LED0_SW_P_EN_CTRL);
sw_w32(0x0000000, RTL838X_LED1_SW_P_EN_CTRL);
sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL);
sw_w32_mask(0x3f, 0, RTL838X_LED_GLB_CTRL);
switch (leds_per_port) {
case 3:
sw_w32_mask(0, 0x7 | (0x7 << 3), RTL838X_LED_GLB_CTRL);
sw_w32(0xFFFFFFF, RTL838X_LED2_SW_P_EN_CTRL);
/* FALLTHRU */
case 2:
sw_w32_mask(0, 0x3 | (0x3 << 3), RTL838X_LED_GLB_CTRL);
sw_w32(0xFFFFFFF, RTL838X_LED1_SW_P_EN_CTRL);
/* FALLTHRU */
case 1:
sw_w32_mask(0, 0x1 | (0x1 << 3), RTL838X_LED_GLB_CTRL);
sw_w32(0xFFFFFFF, RTL838X_LED0_SW_P_EN_CTRL);
break;
default:
pr_err("No LEDS configured for software control\n");
}
}
static const struct of_device_id rtl838x_gpio_of_match[] = {
{ .compatible = "realtek,rtl838x-gpio" },
{},
};
MODULE_DEVICE_TABLE(of, rtl838x_gpio_of_match);
static int rtl838x_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct rtl838x_gpios *gpios;
int err;
u8 indirect_bus_id;
pr_info("Probing RTL838X GPIOs\n");
if (!np) {
dev_err(&pdev->dev, "No DT found\n");
return -EINVAL;
}
gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
if (!gpios)
return -ENOMEM;
gpios->id = sw_r32(RTL838X_MODEL_NAME_INFO) >> 16;
switch (gpios->id) {
case 0x8332:
pr_debug("Found RTL8332M GPIO\n");
break;
case 0x8380:
pr_debug("Found RTL8380M GPIO\n");
break;
case 0x8381:
pr_debug("Found RTL8381M GPIO\n");
break;
case 0x8382:
pr_debug("Found RTL8382M GPIO\n");
break;
default:
pr_err("Unknown GPIO chip id (%04x)\n", gpios->id);
return -ENODEV;
}
gpios->dev = dev;
gpios->gc.base = 0;
/* 0-31: internal
* 32-63, LED control register
* 64-99: external RTL8231
* 100-131: PORT-LED 0
* 132-163: PORT-LED 1
* 164-195: PORT-LED 2
*/
gpios->gc.ngpio = 196;
gpios->gc.label = "rtl838x";
gpios->gc.parent = dev;
gpios->gc.owner = THIS_MODULE;
gpios->gc.can_sleep = true;
gpios->bus_id = -1;
gpios->irq = 31;
gpios->gc.direction_input = rtl838x_direction_input;
gpios->gc.direction_output = rtl838x_direction_output;
gpios->gc.set = rtl838x_gpio_set;
gpios->gc.get = rtl838x_gpio_get;
gpios->gc.get_direction = rtl838x_get_direction;
if (!of_property_read_u8(np, "indirect-access-bus-id", &indirect_bus_id)) {
gpios->bus_id = indirect_bus_id;
rtl8231_init(gpios);
}
if (!of_property_read_u8(np, "smi-bus-id", &indirect_bus_id)) {
gpios->bus_id = indirect_bus_id;
gpios->smi_clock = RTL838X_GPIO_A2;
gpios->smi_data = RTL838X_GPIO_A3;
gpios->i2c_sda = 1;
gpios->i2c_sdc = 2;
rtl8380_rtl8321_init(gpios);
}
if (of_property_read_bool(np, "take-port-leds")) {
if (of_property_read_u32(np, "leds-per-port", &gpios->leds_per_port))
gpios->leds_per_port = 2;
if (of_property_read_u32(np, "led-mode", &gpios->led_mode))
gpios->led_mode = (0x1ea << 15) | 0x1ea;
if (of_property_read_u32(np, "num-leds", &gpios->num_leds))
gpios->num_leds = 32;
if (of_property_read_u32(np, "min-led", &gpios->min_led))
gpios->min_led = 0;
take_port_leds(gpios);
}
err = devm_gpiochip_add_data(dev, &gpios->gc, gpios);
return err;
}
static struct platform_driver rtl838x_gpio_driver = {
.driver = {
.name = "rtl838x-gpio",
.of_match_table = rtl838x_gpio_of_match,
},
.probe = rtl838x_gpio_probe,
};
module_platform_driver(rtl838x_gpio_driver);
MODULE_DESCRIPTION("Realtek RTL838X GPIO API support");
MODULE_LICENSE("GPL v2");

2612
target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c
View File

File diff suppressed because it is too large Load Diff

26
target/linux/rtl838x/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch
View File

@ -1,26 +0,0 @@
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -75,6 +75,13 @@ config NET_DSA_REALTEK_SMI
This enables support for the Realtek SMI-based switch
chips, currently only RTL8366RB.
+config NET_DSA_RTL838X
+ tristate "Realtek rtl838x switch support"
+ depends on RTL838X
+ select NET_DSA_TAG_TRAILER
+ ---help---
+ Say Y here if you want to use the Realtek rtl838x switch.
+
config NET_DSA_SMSC_LAN9303
tristate
select NET_DSA_TAG_LAN9303
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e
obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o
obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o
realtek-smi-objs := realtek-smi-core.o rtl8366.o rtl8366rb.o
+obj-$(CONFIG_NET_DSA_RTL838X) += rtl838x_sw.o rtl838x_phy.o
obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
obj-$(CONFIG_NET_DSA_SMSC_LAN9303_I2C) += lan9303_i2c.o
obj-$(CONFIG_NET_DSA_SMSC_LAN9303_MDIO) += lan9303_mdio.o