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synced 2024-11-25 19:13:48 +08:00
Extend OPENSSL_ia32cap_P with extra word to accomodate AVX2 capability.
This commit is contained in:
Andy Polyakov
parent
b3aee265c5
commit
c5cd28bd64
@ -125,7 +125,7 @@ static double SSLeay_MSVC5_hack=0.0; /* and for VC1.5 */
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defined(__INTEL__) || \
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defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
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extern unsigned int OPENSSL_ia32cap_P[2];
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extern unsigned int OPENSSL_ia32cap_P[4];
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unsigned int *OPENSSL_ia32cap_loc(void) { return OPENSSL_ia32cap_P; }
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#if defined(OPENSSL_CPUID_OBJ) && !defined(OPENSSL_NO_ASM) && !defined(I386_ONLY)
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@ -137,7 +137,7 @@ typedef unsigned long long IA32CAP;
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#endif
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void OPENSSL_cpuid_setup(void)
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{ static int trigger=0;
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IA32CAP OPENSSL_ia32_cpuid(void);
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IA32CAP OPENSSL_ia32_cpuid(unsigned int *);
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IA32CAP vec;
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char *env;
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@ -151,10 +151,18 @@ void OPENSSL_cpuid_setup(void)
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#else
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if (!sscanf(env+off,"%lli",(long long *)&vec)) vec = strtoul(env+off,NULL,0);
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#endif
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if (off) vec = OPENSSL_ia32_cpuid()&~vec;
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if (off) vec = OPENSSL_ia32_cpuid(OPENSSL_ia32cap_P)&~vec;
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OPENSSL_ia32cap_P[2] = 0;
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if ((env=strchr(env,':'))) {
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off = (env[1]=='~')?2:1;
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vec = strtoul(env+off,NULL,0);
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if (off>1) OPENSSL_ia32cap_P[2] &= ~vec;
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else OPENSSL_ia32cap_P[2] = vec;
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}
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}
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else
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vec = OPENSSL_ia32_cpuid();
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vec = OPENSSL_ia32_cpuid(OPENSSL_ia32cap_P);
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/*
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* |(1<<10) sets a reserved bit to signal that variable
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@ -165,7 +173,7 @@ void OPENSSL_cpuid_setup(void)
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OPENSSL_ia32cap_P[1] = (unsigned int)(vec>>32);
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}
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#else
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unsigned int OPENSSL_ia32cap_P[2];
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unsigned int OPENSSL_ia32cap_P[4];
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#endif
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#else
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@ -173,7 +181,7 @@ unsigned int *OPENSSL_ia32cap_loc(void) { return NULL; }
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#endif
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int OPENSSL_NONPIC_relocated = 0;
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#if !defined(OPENSSL_CPUID_SETUP) && !defined(OPENSSL_CPUID_OBJ)
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void OPENSSL_cpuid_setup(void) {}
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void OPENSSL_cpuid_setup(unsigned int *) {}
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#endif
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#if (defined(_WIN32) || defined(__CYGWIN__)) && defined(_WINDLL)
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@ -131,6 +131,32 @@ sub ::rdrand
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{ &::generic("rdrand",@_); }
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}
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sub rxb {
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local *opcode=shift;
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my ($dst,$src1,$src2,$rxb)=@_;
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$rxb|=0x7<<5;
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$rxb&=~(0x04<<5) if($dst>=8);
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$rxb&=~(0x01<<5) if($src1>=8);
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$rxb&=~(0x02<<5) if($src2>=8);
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push @opcode,$rxb;
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}
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sub ::vprotd
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{ my $args=join(',',@_);
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if ($args =~ /xmm([0-7]),xmm([0-7]),([x0-9a-f]+)/)
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{ my @opcode=(0x8f);
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rxb(\@opcode,$1,$2,-1,0x08);
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push @opcode,0x78,0xc2;
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push @opcode,0xc0|($2&7)|(($1&7)<<3); # ModR/M
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my $c=$3;
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push @opcode,$c=~/^0/?oct($c):$c;
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&::data_byte(@opcode);
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}
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else
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{ &::generic("vprotd",@_); }
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}
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# label management
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$lbdecor="L"; # local label decoration, set by package
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$label="000";
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@ -70,6 +70,8 @@ sub ::DWP
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{ my($addr,$reg1,$reg2,$idx)=@_;
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my $ret="";
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if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
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$addr =~ s/^\s+//;
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# prepend global references with optional underscore
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$addr =~ s/^([^\+\-0-9][^\+\-]*)/&::islabel($1) or "$nmdecor$1"/ige;
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@ -157,7 +159,7 @@ sub ::file_end
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}
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}
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if (grep {/\b${nmdecor}OPENSSL_ia32cap_P\b/i} @out) {
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my $tmp=".comm\t${nmdecor}OPENSSL_ia32cap_P,8";
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my $tmp=".comm\t${nmdecor}OPENSSL_ia32cap_P,16";
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if ($::macosx) { push (@out,"$tmp,2\n"); }
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elsif ($::elf) { push (@out,"$tmp,4\n"); }
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else { push (@out,"$tmp\n"); }
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@ -39,6 +39,8 @@ sub get_mem
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{ my($size,$addr,$reg1,$reg2,$idx)=@_;
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my($post,$ret);
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if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
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$ret .= "$size PTR " if ($size ne "");
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$addr =~ s/^\s+//;
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@ -133,7 +135,7 @@ ___
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if (grep {/\b${nmdecor}OPENSSL_ia32cap_P\b/i} @out)
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{ my $comm=<<___;
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.bss SEGMENT 'BSS'
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COMM ${nmdecor}OPENSSL_ia32cap_P:QWORD
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COMM ${nmdecor}OPENSSL_ia32cap_P:DWORD:4
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.bss ENDS
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___
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# comment out OPENSSL_ia32cap_P declarations
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@ -36,6 +36,8 @@ sub get_mem
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{ my($size,$addr,$reg1,$reg2,$idx)=@_;
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my($post,$ret);
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if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
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if ($size ne "")
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{ $ret .= "$size";
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$ret .= " PTR" if ($::mwerks);
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@ -117,7 +119,7 @@ sub ::file_end
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{ if (grep {/\b${nmdecor}OPENSSL_ia32cap_P\b/i} @out)
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{ my $comm=<<___;
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${drdecor}segment .bss
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${drdecor}common ${nmdecor}OPENSSL_ia32cap_P 8
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${drdecor}common ${nmdecor}OPENSSL_ia32cap_P 16
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___
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# comment out OPENSSL_ia32cap_P declarations
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grep {s/(^extern\s+${nmdecor}OPENSSL_ia32cap_P)/\;$1/} @out;
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@ -23,7 +23,7 @@ print<<___;
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call OPENSSL_cpuid_setup
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.hidden OPENSSL_ia32cap_P
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.comm OPENSSL_ia32cap_P,8,4
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.comm OPENSSL_ia32cap_P,16,4
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.text
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@ -52,12 +52,13 @@ OPENSSL_rdtsc:
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.size OPENSSL_rdtsc,.-OPENSSL_rdtsc
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.globl OPENSSL_ia32_cpuid
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.type OPENSSL_ia32_cpuid,\@abi-omnipotent
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.type OPENSSL_ia32_cpuid,\@function,1
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.align 16
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OPENSSL_ia32_cpuid:
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mov %rbx,%r8 # save %rbx
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xor %eax,%eax
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mov %eax,8(%rdi) # clear 3rd word
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cpuid
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mov %eax,%r11d # max value for standard query level
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@ -125,6 +126,14 @@ OPENSSL_ia32_cpuid:
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shr \$14,%r10d
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and \$0xfff,%r10d # number of cores -1 per L1D
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cmp \$7,%r11d
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jb .Lnocacheinfo
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mov \$7,%eax
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xor %ecx,%ecx
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cpuid
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mov %ebx,8(%rdi)
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.Lnocacheinfo:
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mov \$1,%eax
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cpuid
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@ -164,6 +173,7 @@ OPENSSL_ia32_cpuid:
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.Lclear_avx:
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mov \$0xefffe7ff,%eax # ~(1<<28|1<<12|1<<11)
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and %eax,%r9d # clear AVX, FMA and AMD XOP bits
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andl \$0xffffffdf,8(%rdi) # cleax AVX2, ~(1<<5)
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.Ldone:
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shl \$32,%r9
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mov %r10d,%eax
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@ -22,6 +22,8 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&xor ("eax","eax");
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&bt ("ecx",21);
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&jnc (&label("nocpuid"));
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&mov ("esi",&wparam(0));
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&mov (&DWP(8,"esi"),"eax"); # clear 3rd word
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&cpuid ();
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&mov ("edi","eax"); # max value for standard query level
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@ -89,6 +91,15 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&shr ("edi",14);
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&and ("edi",0xfff); # number of cores -1 per L1D
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&cmp ("edi",7);
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&jb (&label("nocacheinfo"));
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&mov ("esi",&wparam(0));
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&mov ("eax",7);
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&xor ("ecx","ecx");
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&cpuid ();
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&mov (&DWP(8,"esi"),"ebx");
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&set_label("nocacheinfo");
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&mov ("eax",1);
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&cpuid ();
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@ -133,6 +144,8 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&and ("esi",0xfeffffff); # clear FXSR
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&set_label("clear_avx");
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&and ("ebp",0xefffe7ff); # clear AVX, FMA and AMD XOP bits
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&mov ("edi",&wparam(0));
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&and (&DWP(8,"edi"),0xffffffdf); # clear AVX2
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&set_label("done");
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&mov ("eax","esi");
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&mov ("edx","ebp");
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@ -72,3 +72,17 @@ the data cache is actually shared between logical cores. This in turn
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affects the decision on whether or not expensive countermeasures
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against cache-timing attacks are applied, most notably in AES assembler
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module.
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The vector is further extended with EBX value returned by CPUID with
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EAX=7 and ECX=0 as input. Following bits are significant:
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=item bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
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=item bit #64+5 denoting availability of AVX2 instructions;
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=item bit #64+8 denoting availability of BMI2 instructions, e.g. MUXL
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and RORX;
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=item bit #64+18 denoting availability of RDSEED instruction;
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=itme bit #64+19 denoting availability of ADCX and ADOX instructions;
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