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RC4_set_key for x86_64 and Core2 optimization.
PR: 1447
This commit is contained in:
Andy Polyakov
parent
2ec0be9e77
commit
9babf3929b
@ -120,7 +120,7 @@ my $x86_elf_asm="x86cpuid-elf.o:bn86-elf.o co86-elf.o mo86-elf.o:dx86-elf.o yx86
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my $x86_coff_asm="x86cpuid-cof.o:bn86-cof.o co86-cof.o mo86-cof.o:dx86-cof.o yx86-cof.o:ax86-cof.o:bx86-cof.o:mx86-cof.o:sx86-cof.o s512sse2-cof.o:cx86-cof.o:rx86-cof.o:rm86-cof.o:r586-cof.o:wp_block.o w86mmx-cof.o";
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my $x86_out_asm="x86cpuid-out.o:bn86-out.o co86-out.o mo86-out.o:dx86-out.o yx86-out.o:ax86-out.o:bx86-out.o:mx86-out.o:sx86-out.o s512sse2-out.o:cx86-out.o:rx86-out.o:rm86-out.o:r586-out.o:wp_block.o w86mmx-out.o";
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my $x86_64_asm="x86_64cpuid.o:x86_64-gcc.o x86_64-mont.o::aes-x86_64.o::md5-x86_64.o:sha1-x86_64.o sha256-x86_64.o sha512-x86_64.o::rc4-x86_64.o rc4_skey.o:::wp-x86_64.o";
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my $x86_64_asm="x86_64cpuid.o:x86_64-gcc.o x86_64-mont.o::aes-x86_64.o::md5-x86_64.o:sha1-x86_64.o sha256-x86_64.o sha512-x86_64.o::rc4-x86_64.o:::wp-x86_64.o";
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my $ia64_asm="ia64cpuid.o:bn-ia64.o::aes_core.o aes_cbc.o aes-ia64.o::md5-ia64.o:sha1-ia64.o sha256-ia64.o sha512-ia64.o::rc4-ia64.o rc4_skey.o:::";
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my $sparcv9_asm="sparcv9cap.o sparccpuid.o:bn-sparcv9.o sparcv9-mont.o sparcv9a-mont.o:des_enc-sparc.o fcrypt_b.o:aes_core.o aes_cbc.o aes-sparcv9.o::::::::";
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my $alpha_asm=":bn_asm.o alpha-mont.o::::::::::";
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8
TABLE
8
TABLE
@ -268,7 +268,7 @@ $bf_obj =
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$md5_obj = md5-x86_64.o
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$sha1_obj = sha1-x86_64.o sha256-x86_64.o sha512-x86_64.o
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$cast_obj =
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$rc4_obj = rc4-x86_64.o rc4_skey.o
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$rc4_obj = rc4-x86_64.o
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$rmd160_obj =
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$rc5_obj =
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$wp_obj = wp-x86_64.o
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@ -3152,7 +3152,7 @@ $bf_obj =
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$md5_obj = md5-x86_64.o
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$sha1_obj = sha1-x86_64.o sha256-x86_64.o sha512-x86_64.o
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$cast_obj =
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$rc4_obj = rc4-x86_64.o rc4_skey.o
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$rc4_obj = rc4-x86_64.o
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$rmd160_obj =
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$rc5_obj =
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$wp_obj = wp-x86_64.o
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@ -3964,7 +3964,7 @@ $bf_obj =
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$md5_obj = md5-x86_64.o
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$sha1_obj = sha1-x86_64.o sha256-x86_64.o sha512-x86_64.o
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$cast_obj =
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$rc4_obj = rc4-x86_64.o rc4_skey.o
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$rc4_obj = rc4-x86_64.o
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$rmd160_obj =
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$rc5_obj =
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$wp_obj = wp-x86_64.o
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@ -3992,7 +3992,7 @@ $bf_obj =
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$md5_obj = md5-x86_64.o
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$sha1_obj = sha1-x86_64.o sha256-x86_64.o sha512-x86_64.o
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$cast_obj =
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$rc4_obj = rc4-x86_64.o rc4_skey.o
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$rc4_obj = rc4-x86_64.o
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$rmd160_obj =
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$rc5_obj =
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$wp_obj = wp-x86_64.o
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@ -49,6 +49,14 @@
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# is not implemented, then this final RC4_CHAR code-path should be
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# preferred, as it provides better *all-round* performance].
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# Intel Core2 was observed to perform poorly on both code paths:-( It
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# apparently suffers from some kind of partial register stall, which
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# occurs in 64-bit mode only [as virtually identical 32-bit loop was
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# observed to outperform 64-bit one by almost 50%]. Adding two movzb to
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# cloop1 boosts its performance by 80%! This loop appears to be optimal
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# fit for Core2 and therefore the code was modified to skip cloop8 on
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# this CPU.
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$output=shift;
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open STDOUT,"| $^X ../perlasm/x86_64-xlate.pl $output";
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@ -152,6 +160,8 @@ $code.=<<___;
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movzb ($dat,$XX[0]),$TX[0]#d
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test \$-8,$len
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jz .Lcloop1
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cmp \$0,260($dat)
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jnz .Lcloop1
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push %rbx
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jmp .Lcloop8
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.align 16
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@ -235,6 +245,111 @@ $code.=<<___;
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.size RC4,.-RC4
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___
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$idx="%r8";
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$ido="%r9";
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$code.=<<___;
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.extern OPENSSL_ia32cap_P
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.globl RC4_set_key
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.type RC4_set_key,\@function,3
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.align 16
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RC4_set_key:
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lea 8($dat),$dat
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lea ($inp,$len),$inp
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neg $len
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mov $len,%rcx
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xor %eax,%eax
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xor $ido,$ido
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xor %r10,%r10
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xor %r11,%r11
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mov OPENSSL_ia32cap_P(%rip),$idx#d
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bt \$20,$idx#d
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jnc .Lw1stloop
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bt \$30,$idx#d
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setc $ido#b
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mov $ido#d,260($dat)
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jmp .Lc1stloop
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.align 16
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.Lw1stloop:
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mov %eax,($dat,%rax,4)
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add \$1,%al
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jnc .Lw1stloop
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xor $ido,$ido
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xor $idx,$idx
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.align 16
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.Lw2ndloop:
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mov ($dat,$ido,4),%r10d
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add ($inp,$len,1),$idx#b
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add %r10b,$idx#b
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add \$1,$len
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mov ($dat,$idx,4),%r11d
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cmovz %rcx,$len
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mov %r10d,($dat,$idx,4)
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mov %r11d,($dat,$ido,4)
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add \$1,$ido#b
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jnc .Lw2ndloop
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jmp .Lexit_key
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.align 16
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.Lc1stloop:
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mov %al,($dat,%rax)
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add \$1,%al
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jnc .Lc1stloop
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xor $ido,$ido
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xor $idx,$idx
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.align 16
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.Lc2ndloop:
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mov ($dat,$ido),%r10b
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add ($inp,$len),$idx#b
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add %r10b,$idx#b
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add \$1,$len
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mov ($dat,$idx),%r11b
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jnz .Lcnowrap
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mov %rcx,$len
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.Lcnowrap:
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mov %r10b,($dat,$idx)
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mov %r11b,($dat,$ido)
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add \$1,$ido#b
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jnc .Lc2ndloop
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movl \$-1,256($dat)
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.align 16
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.Lexit_key:
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xor %eax,%eax
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mov %eax,-8($dat)
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mov %eax,-4($dat)
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ret
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.size RC4_set_key,.-RC4_set_key
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.globl RC4_options
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.type RC4_options,\@function,0
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.align 16
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RC4_options:
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.picmeup %rax
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lea .Lopts-.(%rax),%rax
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mov OPENSSL_ia32cap_P(%rip),%edx
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bt \$20,%edx
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jnc .Ldone
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add \$12,%rax
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bt \$30,%edx
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jnc .Ldone
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add \$13,%rax
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.Ldone:
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ret
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.align 64
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.Lopts:
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.asciz "rc4(8x,int)"
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.asciz "rc4(8x,char)"
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.asciz "rc4(1x,char)"
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.asciz "RC4 for x86_64, OpenSSL project"
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.align 64
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.size RC4_options,.-RC4_options
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___
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$code =~ s/#([bwd])/$1/gm;
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print $code;
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@ -48,8 +48,37 @@ OPENSSL_wipe_cpu ENDP
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OPENSSL_ia32_cpuid PROC
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mov r8,rbx
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xor eax,eax
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cpuid
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xor eax,eax
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cmp ebx,0756e6547h
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setne al
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mov r9d,eax
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cmp edx,049656e69h
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setne al
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or r9d,eax
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cmp ecx,06c65746eh
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setne al
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or r9d,eax
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mov eax,1
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cpuid
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bt edx,28
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jnc \$Ldone
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cmp r9,0
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jne \$Lnotintel
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or edx,000100000h
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and ah,15
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cmp ah,15
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je \$Lnotintel
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or edx,040000000h
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\$Lnotintel:
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shr ebx,16
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cmp bl,1
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ja \$Ldone
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and edx,0efffffffh
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\$Ldone:
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shl rcx,32
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mov eax,edx
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mov rbx,r8
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@ -124,8 +153,37 @@ OPENSSL_wipe_cpu:
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.align 16
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OPENSSL_ia32_cpuid:
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movq %rbx,%r8
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xor %eax,%eax
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cpuid
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xor %eax,%eax
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cmp \$0x756e6547,%ebx # "Genu"
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setne %al
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mov %eax,%r9d
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cmp \$0x49656e69,%edx # "ineI"
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setne %al
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or %eax,%r9d
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cmp \$0x6c65746e,%ecx # "ntel"
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setne %al
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or %eax,%r9d
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movl \$1,%eax
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cpuid
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bt \$28,%edx # test hyper-threading bit
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jnc .Ldone
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cmp \$0,%r9
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jne .Lnotintel
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or \$1<<20,%edx # use reserved bit to engage RC4_CHAR
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and \$15,%ah
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cmp \$15,%ah # examine Family ID
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je .Lnotintel
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or \$1<<30,%edx # use reserved bit to skip unrolled loop
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.Lnotintel:
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shr \$16,%ebx
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cmp \$1,%bl # see if cache is shared
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ja .Ldone
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and \$~(1<<28),%edx
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.Ldone:
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shlq \$32,%rcx
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movl %edx,%eax
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movq %r8,%rbx
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