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rc4_skey.c: remove dead/redundant code (it's never compiled) and
misleading/obsolete comment.
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@ -104,40 +104,6 @@ void RC4_set_key(RC4_KEY *key, int len, const unsigned char *data)
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d[(n)]=d[id2]; \
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d[id2]=tmp; }
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#if defined(OPENSSL_CPUID_OBJ) && !defined(OPENSSL_NO_ASM)
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# if defined(__i386) || defined(__i386__) || defined(_M_IX86) || \
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defined(__INTEL__) || \
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defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64)
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if (sizeof(RC4_INT) > 1) {
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/*
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* Unlike all other x86 [and x86_64] implementations,
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* Intel P4 core [including EM64T] was found to perform
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* poorly with wider RC4_INT. Performance improvement
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* for IA-32 hand-coded assembler turned out to be 2.8x
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* if re-coded for RC4_CHAR! It's however inappropriate
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* to just switch to RC4_CHAR for x86[_64], as non-P4
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* implementations suffer from significant performance
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* losses then, e.g. PIII exhibits >2x deterioration,
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* and so does Opteron. In order to assure optimal
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* all-round performance, let us [try to] detect P4 at
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* run-time by checking upon HTT bit in CPU capability
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* vector and set up compressed key schedule, which is
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* recognized by correspondingly updated assembler
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* module...
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* <appro@fy.chalmers.se>
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*/
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if (OPENSSL_ia32cap_P & (1<<28)) {
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unsigned char *cp=(unsigned char *)d;
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for (i=0;i<256;i++) cp[i]=i;
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for (i=0;i<256;i++) SK_LOOP(cp,i);
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/* mark schedule as compressed! */
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d[256/sizeof(RC4_INT)]=-1;
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return;
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}
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}
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# endif
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#endif
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for (i=0; i < 256; i++) d[i]=i;
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for (i=0; i < 256; i+=4)
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{
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