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Fix aarch64 signed bit shift issue found by UBSAN

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Also fix conditional branch out of range when using sanitisers.

Fixes #18813

Signed-off-by: Tom Cosgrove <tom.cosgrove@arm.com>

Change-Id: Ic543885091ed3ef2ddcbe21de0a4ac0bca1e2494

Reviewed-by: Paul Dale <pauli@openssl.org>
Reviewed-by: Matt Caswell <matt@openssl.org>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/18816)
This commit is contained in:
Tom Cosgrove 2022-07-18 10:24:47 +01:00 committed by Tomas Mraz
parent 7a16f179ab
commit 1efd8533e1
2 changed files with 4 additions and 8 deletions
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4
crypto/aes/asm/bsaes-armv8.pl
View File

@ -1019,13 +1019,9 @@ _bsaes_key_convert:
// No output registers, usual AAPCS64 register preservation
ossl_bsaes_cbc_encrypt:
cmp x2, #128
#ifdef __APPLE__
bhs .Lcbc_do_bsaes
b AES_cbc_encrypt
.Lcbc_do_bsaes:
#else
blo AES_cbc_encrypt
#endif
// it is up to the caller to make sure we are called with enc == 0

8
crypto/arm_arch.h
View File

@ -104,17 +104,17 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
# define ARM_CPU_PART_N2 0xD49
# define MIDR_PARTNUM_SHIFT 4
# define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
# define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT)
# define MIDR_PARTNUM(midr) \
(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
# define MIDR_IMPLEMENTER_SHIFT 24
# define MIDR_IMPLEMENTER_MASK (0xff << MIDR_IMPLEMENTER_SHIFT)
# define MIDR_IMPLEMENTER_MASK (0xffU << MIDR_IMPLEMENTER_SHIFT)
# define MIDR_IMPLEMENTER(midr) \
(((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)
# define MIDR_ARCHITECTURE_SHIFT 16
# define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
# define MIDR_ARCHITECTURE_MASK (0xfU << MIDR_ARCHITECTURE_SHIFT)
# define MIDR_ARCHITECTURE(midr) \
(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
@ -125,7 +125,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
# define MIDR_CPU_MODEL(imp, partnum) \
(((imp) << MIDR_IMPLEMENTER_SHIFT) | \
(0xf << MIDR_ARCHITECTURE_SHIFT) | \
(0xfU << MIDR_ARCHITECTURE_SHIFT) | \
((partnum) << MIDR_PARTNUM_SHIFT))
# define MIDR_IS_CPU_MODEL(midr, imp, partnum) \