mirror of
https://github.com/openssl/openssl.git
synced 2024-11-29 04:55:11 +08:00
aesv8-armx.pl: inclrease interleave factor.
This is to compensate for higher aes* instruction latency on Cortex-A57.
This commit is contained in:
Andy Polyakov
parent
0f777aeb50
commit
015364baf3
@ -11,16 +11,21 @@
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# module is endian-agnostic in sense that it supports both big- and
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# little-endian cases. As does it support both 32- and 64-bit modes
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# of operation. Latter is achieved by limiting amount of utilized
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# registers to 16, which implies additional instructions. This has
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# no effect on mighty Apple A7, as results are literally equal to
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# the theoretical estimates based on instruction latencies and issue
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# rate. It remains to be seen how does it affect other platforms...
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# registers to 16, which implies additional NEON load and integer
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# instructions. This has no effect on mighty Apple A7, where results
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# are literally equal to the theoretical estimates based on AES
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# instruction latencies and issue rates. On Cortex-A53, an in-order
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# execution core, this costs up to 10-15%, which is partially
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# compensated by implementing dedicated code path for 128-bit
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# CBC encrypt case. On Cortex-A57 parallelizable mode performance
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# seems to be limited by sheer amount of NEON instructions...
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#
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# Performance in cycles per byte processed with 128-bit key:
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#
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# CBC enc CBC dec CTR
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# Apple A7 2.39 1.20 1.20
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# Cortex-A5x n/a n/a n/a
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# Cortex-A53 2.45 1.87 1.94
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# Cortex-A57 3.64 1.34 1.32
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$flavour = shift;
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open STDOUT,">".shift;
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@ -435,189 +440,166 @@ $code.=<<___;
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vst1.8 {$ivec},[$out],#16
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b .Lcbc_done
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.align 5
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.Lcbc_dec128:
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vld1.32 {$tmp0-$tmp1},[$key_]
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veor $ivec,$ivec,$rndlast
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veor $in0,$dat0,$rndlast
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mov $step1,$step
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.Loop2x_cbc_dec128:
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aesd $dat0,q8
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aesd $dat1,q8
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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subs $len,$len,#32
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aesd $dat0,q9
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aesd $dat1,q9
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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cclr $step,lo
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aesd $dat0,$tmp0
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aesd $dat1,$tmp0
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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cclr $step1,ls
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aesd $dat0,$tmp1
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aesd $dat1,$tmp1
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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aesd $dat0,q10
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aesd $dat1,q10
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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aesd $dat0,q11
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aesd $dat1,q11
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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aesd $dat0,q12
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aesd $dat1,q12
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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aesd $dat0,q13
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aesd $dat1,q13
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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aesd $dat0,q14
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aesd $dat1,q14
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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aesd $dat0,q15
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aesd $dat1,q15
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veor $ivec,$ivec,$dat0
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vld1.8 {$dat0},[$inp],$step
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veor $in0,$in0,$dat1
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vld1.8 {$dat1},[$inp],$step1
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vst1.8 {$ivec},[$out],#16
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veor $ivec,$in1,$rndlast
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vst1.8 {$in0},[$out],#16
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veor $in0,$dat0,$rndlast
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vorr $in1,$dat1,$dat1
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b.hs .Loop2x_cbc_dec128
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adds $len,$len,#32
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veor $ivec,$ivec,$rndlast
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b.eq .Lcbc_done
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veor $in0,$in0,$rndlast
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b .Lcbc_dec_tail
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___
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{
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my ($dat2,$in2,$tmp2)=map("q$_",(10,11,9));
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$code.=<<___;
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.align 5
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.Lcbc_dec:
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subs $len,$len,#16
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vorr $in0,$dat,$dat
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vld1.8 {$dat2},[$inp],#16
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subs $len,$len,#32 // bias
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add $cnt,$rounds,#2
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vorr $in1,$dat,$dat
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vorr $dat1,$dat,$dat
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vorr $in2,$dat2,$dat2
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b.lo .Lcbc_dec_tail
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cclr $step,eq
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cmp $rounds,#2
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vld1.8 {$dat1},[$inp],$step
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vorr $dat1,$dat2,$dat2
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vld1.8 {$dat2},[$inp],#16
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vorr $in0,$dat,$dat
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vorr $in1,$dat1,$dat1
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b.eq .Lcbc_dec128
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vorr $in2,$dat2,$dat2
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.Loop2x_cbc_dec:
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.Loop3x_cbc_dec:
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aesd $dat0,q8
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aesd $dat1,q8
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aesd $dat2,q8
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vld1.32 {q8},[$key_],#16
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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aesimc $dat2,$dat2
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subs $cnt,$cnt,#2
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aesd $dat0,q9
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aesd $dat1,q9
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aesd $dat2,q9
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vld1.32 {q9},[$key_],#16
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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b.gt .Loop2x_cbc_dec
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aesimc $dat2,$dat2
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b.gt .Loop3x_cbc_dec
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aesd $dat0,q8
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aesd $dat1,q8
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aesd $dat2,q8
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veor $tmp0,$ivec,$rndlast
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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veor $tmp0,$ivec,$rndlast
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aesimc $dat2,$dat2
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veor $tmp1,$in0,$rndlast
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aesd $dat0,q9
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aesd $dat1,q9
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aesd $dat2,q9
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veor $tmp2,$in1,$rndlast
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subs $len,$len,#0x30
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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vorr $ivec,$in1,$in1
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subs $len,$len,#32
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aesd $dat0,q10
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aesd $dat1,q10
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aesimc $dat0,$dat0
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cclr $step,lo
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aesimc $dat1,$dat1
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mov $key_,$key
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aesd $dat0,q11
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aesd $dat1,q11
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aesimc $dat0,$dat0
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vld1.8 {$in0},[$inp],$step
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aesimc $dat1,$dat1
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cclr $step,ls
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aesimc $dat2,$dat2
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vorr $ivec,$in2,$in2
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mov.lo x6,$len // x6, $cnt, is zero at this point
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aesd $dat0,q12
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aesd $dat1,q12
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aesd $dat2,q12
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add $inp,$inp,x6 // $inp is adjusted in such way that
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// at exit from the loop $dat1-$dat2
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// are loaded with last "words"
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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vld1.8 {$in1},[$inp],$step
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aesimc $dat2,$dat2
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mov $key_,$key
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aesd $dat0,q13
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aesd $dat1,q13
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aesd $dat2,q13
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vld1.8 {$in0},[$inp],#16
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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vld1.32 {q8},[$key_],#16 // re-pre-load rndkey[0]
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aesimc $dat2,$dat2
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vld1.8 {$in1},[$inp],#16
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aesd $dat0,q14
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aesd $dat1,q14
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aesd $dat2,q14
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vld1.8 {$in2},[$inp],#16
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aesimc $dat0,$dat0
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aesimc $dat1,$dat1
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vld1.32 {q9},[$key_],#16 // re-pre-load rndkey[1]
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aesimc $dat2,$dat2
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vld1.32 {q8},[$key_],#16 // re-pre-load rndkey[0]
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aesd $dat0,q15
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aesd $dat1,q15
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aesd $dat2,q15
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mov $cnt,$rounds
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add $cnt,$rounds,#2
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veor $tmp0,$tmp0,$dat0
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veor $tmp1,$tmp1,$dat1
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veor $dat2,$dat2,$tmp2
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vld1.32 {q9},[$key_],#16 // re-pre-load rndkey[1]
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vorr $dat0,$in0,$in0
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vst1.8 {$tmp0},[$out],#16
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vorr $dat1,$in1,$in1
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vst1.8 {$tmp1},[$out],#16
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b.hs .Loop2x_cbc_dec
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vst1.8 {$dat2},[$out],#16
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vorr $dat2,$in2,$in2
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b.hs .Loop3x_cbc_dec
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adds $len,$len,#32
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cmn $len,#0x30
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b.eq .Lcbc_done
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nop
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.Lcbc_dec_tail:
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aesd $dat,q8
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aesd $dat1,q8
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aesd $dat2,q8
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vld1.32 {q8},[$key_],#16
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aesimc $dat,$dat
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aesimc $dat1,$dat1
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aesimc $dat2,$dat2
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subs $cnt,$cnt,#2
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aesd $dat,q9
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aesd $dat1,q9
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aesd $dat2,q9
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vld1.32 {q9},[$key_],#16
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aesimc $dat,$dat
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aesimc $dat1,$dat1
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aesimc $dat2,$dat2
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b.gt .Lcbc_dec_tail
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aesd $dat,q8
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aesimc $dat,$dat
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aesd $dat,q9
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aesimc $dat,$dat
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veor $tmp,$ivec,$rndlast
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aesd $dat,q10
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aesimc $dat,$dat
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vorr $ivec,$in0,$in0
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aesd $dat,q11
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aesimc $dat,$dat
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aesd $dat,q12
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aesimc $dat,$dat
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aesd $dat,q13
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aesimc $dat,$dat
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aesd $dat,q14
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aesimc $dat,$dat
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aesd $dat,q15
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aesd $dat1,q8
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aesd $dat2,q8
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aesimc $dat1,$dat1
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aesimc $dat2,$dat2
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aesd $dat1,q9
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aesd $dat2,q9
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aesimc $dat1,$dat1
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aesimc $dat2,$dat2
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aesd $dat1,q12
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aesd $dat2,q12
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aesimc $dat1,$dat1
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aesimc $dat2,$dat2
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cmn $len,#0x20
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aesd $dat1,q13
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aesd $dat2,q13
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aesimc $dat1,$dat1
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aesimc $dat2,$dat2
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veor $tmp1,$ivec,$rndlast
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aesd $dat1,q14
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aesd $dat2,q14
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aesimc $dat1,$dat1
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aesimc $dat2,$dat2
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veor $tmp2,$in1,$rndlast
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aesd $dat1,q15
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aesd $dat2,q15
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b.eq .Lcbc_dec_one
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veor $tmp1,$tmp1,$dat1
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veor $tmp2,$tmp2,$dat2
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vorr $ivec,$in2,$in2
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vst1.8 {$tmp1},[$out],#16
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vst1.8 {$tmp2},[$out],#16
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b .Lcbc_done
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veor $tmp,$tmp,$dat
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vst1.8 {$tmp},[$out],#16
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.Lcbc_dec_one:
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veor $tmp1,$tmp1,$dat2
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vorr $ivec,$in2,$in2
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vst1.8 {$tmp1},[$out],#16
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.Lcbc_done:
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vst1.8 {$ivec},[$ivp]
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.Lcbc_abort:
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___
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}
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$code.=<<___ if ($flavour !~ /64/);
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vldmia sp!,{d8-d15}
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ldmia sp!,{r4-r8,pc}
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@ -632,8 +614,12 @@ ___
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}}}
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{{{
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my ($inp,$out,$len,$key,$ivp)=map("x$_",(0..4));
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my ($rounds,$cnt,$key_,$ctr,$tctr,$tctr1)=("w5","w6","x7","w8","w9","w10");
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my ($rounds,$cnt,$key_)=("w5","w6","x7");
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my ($ctr,$tctr0,$tctr1,$tctr2)=map("w$_",(8..10,12));
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my $step="x12"; # aliases with $tctr2
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my ($dat0,$dat1,$in0,$in1,$tmp0,$tmp1,$ivec,$rndlast)=map("q$_",(0..7));
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my ($dat2,$in2,$tmp2)=map("q$_",(10,11,9));
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my ($dat,$tmp)=($dat0,$tmp0);
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@ -662,32 +648,124 @@ $code.=<<___;
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vld1.32 {$dat0},[$ivp]
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vld1.32 {q8-q9},[$key] // load key schedule...
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sub $rounds,$rounds,#6
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add $key_,$key,x5,lsl#4 // pointer to last 7 round keys
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sub $rounds,$rounds,#4
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mov $step,#16
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cmp $len,#2
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add $key_,$key,x5,lsl#4 // pointer to last 5 round keys
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sub $rounds,$rounds,#2
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vld1.32 {q10-q11},[$key_],#32
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vld1.32 {q12-q13},[$key_],#32
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vld1.32 {q14-q15},[$key_],#32
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vld1.32 {$rndlast},[$key_]
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add $key_,$key,#32
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mov $cnt,$rounds
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subs $len,$len,#2
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b.lo .Lctr32_tail
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cclr $step,lo
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#ifndef __ARMEB__
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rev $ctr, $ctr
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#endif
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vorr $dat1,$dat0,$dat0
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add $ctr, $ctr, #1
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add $tctr1, $ctr, #1
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vorr $dat2,$dat0,$dat0
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add $ctr, $ctr, #2
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vorr $ivec,$dat0,$dat0
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rev $tctr1, $ctr
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cmp $rounds,#2
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rev $tctr1, $tctr1
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vmov.32 ${dat1}[3],$tctr1
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b.eq .Lctr32_128
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b.ls .Lctr32_tail
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rev $tctr2, $ctr
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sub $len,$len,#3 // bias
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vmov.32 ${dat2}[3],$tctr2
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b .Loop3x_ctr32
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.Loop2x_ctr32:
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.align 4
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.Loop3x_ctr32:
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aese $dat0,q8
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aese $dat1,q8
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aese $dat2,q8
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vld1.32 {q8},[$key_],#16
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aesmc $dat0,$dat0
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aesmc $dat1,$dat1
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aesmc $dat2,$dat2
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subs $cnt,$cnt,#2
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aese $dat0,q9
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aese $dat1,q9
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aese $dat2,q9
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vld1.32 {q9},[$key_],#16
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aesmc $dat0,$dat0
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aesmc $dat1,$dat1
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aesmc $dat2,$dat2
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b.gt .Loop3x_ctr32
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aese $dat0,q8
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aese $dat1,q8
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aese $dat2,q8
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mov $key_,$key
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aesmc $tmp0,$dat0
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vld1.8 {$in0},[$inp],#16
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aesmc $tmp1,$dat1
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aesmc $dat2,$dat2
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vorr $dat0,$ivec,$ivec
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aese $tmp0,q9
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vld1.8 {$in1},[$inp],#16
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aese $tmp1,q9
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aese $dat2,q9
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vorr $dat1,$ivec,$ivec
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aesmc $tmp0,$tmp0
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vld1.8 {$in2},[$inp],#16
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aesmc $tmp1,$tmp1
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aesmc $tmp2,$dat2
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vorr $dat2,$ivec,$ivec
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add $tctr0,$ctr,#1
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aese $tmp0,q12
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aese $tmp1,q12
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aese $tmp2,q12
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veor $in0,$in0,$rndlast
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add $tctr1,$ctr,#2
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aesmc $tmp0,$tmp0
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aesmc $tmp1,$tmp1
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aesmc $tmp2,$tmp2
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veor $in1,$in1,$rndlast
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add $ctr,$ctr,#3
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aese $tmp0,q13
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aese $tmp1,q13
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aese $tmp2,q13
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veor $in2,$in2,$rndlast
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rev $tctr0,$tctr0
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aesmc $tmp0,$tmp0
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vld1.32 {q8},[$key_],#16 // re-pre-load rndkey[0]
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aesmc $tmp1,$tmp1
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aesmc $tmp2,$tmp2
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vmov.32 ${dat0}[3], $tctr0
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rev $tctr1,$tctr1
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aese $tmp0,q14
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aese $tmp1,q14
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aese $tmp2,q14
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vmov.32 ${dat1}[3], $tctr1
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rev $tctr2,$ctr
|
||||
aesmc $tmp0,$tmp0
|
||||
aesmc $tmp1,$tmp1
|
||||
aesmc $tmp2,$tmp2
|
||||
vmov.32 ${dat2}[3], $tctr2
|
||||
subs $len,$len,#3
|
||||
aese $tmp0,q15
|
||||
aese $tmp1,q15
|
||||
aese $tmp2,q15
|
||||
|
||||
mov $cnt,$rounds
|
||||
veor $in0,$in0,$tmp0
|
||||
veor $in1,$in1,$tmp1
|
||||
veor $in2,$in2,$tmp2
|
||||
vld1.32 {q9},[$key_],#16 // re-pre-load rndkey[1]
|
||||
vst1.8 {$in0},[$out],#16
|
||||
vst1.8 {$in1},[$out],#16
|
||||
vst1.8 {$in2},[$out],#16
|
||||
b.hs .Loop3x_ctr32
|
||||
|
||||
adds $len,$len,#3
|
||||
b.eq .Lctr32_done
|
||||
cmp $len,#1
|
||||
mov $step,#16
|
||||
cclr $step,eq
|
||||
|
||||
.Lctr32_tail:
|
||||
aese $dat0,q8
|
||||
aese $dat1,q8
|
||||
vld1.32 {q8},[$key_],#16
|
||||
@ -699,102 +777,20 @@ $code.=<<___;
|
||||
vld1.32 {q9},[$key_],#16
|
||||
aesmc $dat0,$dat0
|
||||
aesmc $dat1,$dat1
|
||||
b.gt .Loop2x_ctr32
|
||||
b.gt .Lctr32_tail
|
||||
|
||||
aese $dat0,q8
|
||||
aese $dat1,q8
|
||||
aesmc $tmp0,$dat0
|
||||
vorr $dat0,$ivec,$ivec
|
||||
aesmc $tmp1,$dat1
|
||||
vorr $dat1,$ivec,$ivec
|
||||
aese $tmp0,q9
|
||||
aese $tmp1,q9
|
||||
vld1.8 {$in0},[$inp],#16
|
||||
aesmc $tmp0,$tmp0
|
||||
vld1.8 {$in1},[$inp],#16
|
||||
aesmc $tmp1,$tmp1
|
||||
add $ctr,$ctr,#1
|
||||
aese $tmp0,q10
|
||||
aese $tmp1,q10
|
||||
rev $tctr,$ctr
|
||||
aesmc $tmp0,$tmp0
|
||||
aesmc $tmp1,$tmp1
|
||||
add $ctr,$ctr,#1
|
||||
aese $tmp0,q11
|
||||
aese $tmp1,q11
|
||||
veor $in0,$in0,$rndlast
|
||||
rev $tctr1,$ctr
|
||||
aesmc $tmp0,$tmp0
|
||||
aesmc $tmp1,$tmp1
|
||||
veor $in1,$in1,$rndlast
|
||||
mov $key_,$key
|
||||
aese $tmp0,q12
|
||||
aese $tmp1,q12
|
||||
subs $len,$len,#2
|
||||
aesmc $tmp0,$tmp0
|
||||
aesmc $tmp1,$tmp1
|
||||
vld1.32 {q8-q9},[$key_],#32 // re-pre-load rndkey[0-1]
|
||||
aese $tmp0,q13
|
||||
aese $tmp1,q13
|
||||
aesmc $tmp0,$tmp0
|
||||
aesmc $tmp1,$tmp1
|
||||
aese $tmp0,q14
|
||||
aese $tmp1,q14
|
||||
vmov.32 ${dat0}[3], $tctr
|
||||
aesmc $tmp0,$tmp0
|
||||
vmov.32 ${dat1}[3], $tctr1
|
||||
aesmc $tmp1,$tmp1
|
||||
aese $tmp0,q15
|
||||
aese $tmp1,q15
|
||||
|
||||
mov $cnt,$rounds
|
||||
veor $in0,$in0,$tmp0
|
||||
veor $in1,$in1,$tmp1
|
||||
vst1.8 {$in0},[$out],#16
|
||||
vst1.8 {$in1},[$out],#16
|
||||
b.hs .Loop2x_ctr32
|
||||
|
||||
adds $len,$len,#2
|
||||
b.eq .Lctr32_done
|
||||
b .Lctr32_tail
|
||||
|
||||
.Lctr32_128:
|
||||
vld1.32 {$tmp0-$tmp1},[$key_]
|
||||
|
||||
.Loop2x_ctr32_128:
|
||||
aese $dat0,q8
|
||||
aese $dat1,q8
|
||||
aesmc $dat0,$dat0
|
||||
vld1.8 {$in0},[$inp],#16
|
||||
aesmc $dat1,$dat1
|
||||
vld1.8 {$in1},[$inp],#16
|
||||
aese $dat0,q9
|
||||
aese $dat1,q9
|
||||
add $ctr,$ctr,#1
|
||||
aesmc $dat0,$dat0
|
||||
aesmc $dat1,$dat1
|
||||
rev $tctr,$ctr
|
||||
aese $dat0,$tmp0
|
||||
aese $dat1,$tmp0
|
||||
add $ctr,$ctr,#1
|
||||
aesmc $dat0,$dat0
|
||||
aesmc $dat1,$dat1
|
||||
rev $tctr1,$ctr
|
||||
aese $dat0,$tmp1
|
||||
aese $dat1,$tmp1
|
||||
subs $len,$len,#2
|
||||
aesmc $dat0,$dat0
|
||||
aesmc $dat1,$dat1
|
||||
aese $dat0,q10
|
||||
aese $dat1,q10
|
||||
aesmc $dat0,$dat0
|
||||
aesmc $dat1,$dat1
|
||||
aese $dat0,q11
|
||||
aese $dat1,q11
|
||||
aesmc $dat0,$dat0
|
||||
aesmc $dat1,$dat1
|
||||
vld1.8 {$in0},[$inp],$step
|
||||
aese $dat0,q12
|
||||
aese $dat1,q12
|
||||
vld1.8 {$in1},[$inp]
|
||||
aesmc $dat0,$dat0
|
||||
aesmc $dat1,$dat1
|
||||
aese $dat0,q13
|
||||
@ -803,56 +799,19 @@ $code.=<<___;
|
||||
aesmc $dat1,$dat1
|
||||
aese $dat0,q14
|
||||
aese $dat1,q14
|
||||
veor $in0,$in0,$rndlast
|
||||
aesmc $dat0,$dat0
|
||||
aesmc $dat1,$dat1
|
||||
veor $in0,$in0,$rndlast
|
||||
aese $dat0,q15
|
||||
veor $in1,$in1,$rndlast
|
||||
aese $dat0,q15
|
||||
aese $dat1,q15
|
||||
|
||||
cmp $len,#1
|
||||
veor $in0,$in0,$dat0
|
||||
vorr $dat0,$ivec,$ivec
|
||||
veor $in1,$in1,$dat1
|
||||
vorr $dat1,$ivec,$ivec
|
||||
vst1.8 {$in0},[$out],#16
|
||||
vmov.32 ${dat0}[3], $tctr
|
||||
vst1.8 {$in1},[$out],#16
|
||||
vmov.32 ${dat1}[3], $tctr1
|
||||
b.hs .Loop2x_ctr32_128
|
||||
|
||||
adds $len,$len,#2
|
||||
b.eq .Lctr32_done
|
||||
|
||||
.Lctr32_tail:
|
||||
aese $dat,q8
|
||||
vld1.32 {q8},[$key_],#16
|
||||
aesmc $dat,$dat
|
||||
subs $cnt,$cnt,#2
|
||||
aese $dat,q9
|
||||
vld1.32 {q9},[$key_],#16
|
||||
aesmc $dat,$dat
|
||||
b.gt .Lctr32_tail
|
||||
|
||||
aese $dat,q8
|
||||
aesmc $dat,$dat
|
||||
aese $dat,q9
|
||||
aesmc $dat,$dat
|
||||
vld1.8 {$in0},[$inp]
|
||||
aese $dat,q10
|
||||
aesmc $dat,$dat
|
||||
aese $dat,q11
|
||||
aesmc $dat,$dat
|
||||
aese $dat,q12
|
||||
aesmc $dat,$dat
|
||||
aese $dat,q13
|
||||
aesmc $dat,$dat
|
||||
aese $dat,q14
|
||||
aesmc $dat,$dat
|
||||
veor $in0,$in0,$rndlast
|
||||
aese $dat,q15
|
||||
|
||||
veor $in0,$in0,$dat
|
||||
vst1.8 {$in0},[$out]
|
||||
vst1.8 {$in1},[$out]
|
||||
|
||||
.Lctr32_done:
|
||||
___
|
||||
@ -887,29 +846,30 @@ if ($flavour =~ /64/) { ######## 64-bit code
|
||||
};
|
||||
|
||||
foreach(split("\n",$code)) {
|
||||
s/\`([^\`]*)\`/eval($1)/geo;
|
||||
s/\`([^\`]*)\`/eval($1)/geo;
|
||||
|
||||
s/\bq([0-9]+)\b/"v".($1<8?$1:$1+8).".16b"/geo; # old->new registers
|
||||
s/@\s/\/\//o; # old->new style commentary
|
||||
s/@\s/\/\//o; # old->new style commentary
|
||||
|
||||
#s/[v]?(aes\w+)\s+([qv].*)/unaes($1,$2)/geo or
|
||||
s/cclr\s+([wx])([^,]+),\s*([a-z]+)/csel $1$2,$1zr,$1$2,$3/o or
|
||||
s/vmov\.i8/movi/o or # fix up legacy mnemonics
|
||||
s/vext\.8/ext/o or
|
||||
s/vrev32\.8/rev32/o or
|
||||
s/vtst\.8/cmtst/o or
|
||||
s/vshr/ushr/o or
|
||||
s/^(\s+)v/$1/o or # strip off v prefix
|
||||
s/mov\.([a-z]+)\s+([wx][0-9]+),\s*([wx][0-9]+)/csel $2,$3,$2,$1/o or
|
||||
s/vmov\.i8/movi/o or # fix up legacy mnemonics
|
||||
s/vext\.8/ext/o or
|
||||
s/vrev32\.8/rev32/o or
|
||||
s/vtst\.8/cmtst/o or
|
||||
s/vshr/ushr/o or
|
||||
s/^(\s+)v/$1/o or # strip off v prefix
|
||||
s/\bbx\s+lr\b/ret/o;
|
||||
|
||||
# fix up remainig legacy suffixes
|
||||
s/\.[ui]?8//o;
|
||||
m/\],#8/o and s/\.16b/\.8b/go;
|
||||
s/\.[ui]?32//o and s/\.16b/\.4s/go;
|
||||
s/\.[ui]?64//o and s/\.16b/\.2d/go;
|
||||
s/\.[ui]?32//o and s/\.16b/\.4s/go;
|
||||
s/\.[ui]?64//o and s/\.16b/\.2d/go;
|
||||
s/\.[42]([sd])\[([0-3])\]/\.$1\[$2\]/o;
|
||||
|
||||
print $_,"\n";
|
||||
print $_,"\n";
|
||||
}
|
||||
} else { ######## 32-bit code
|
||||
my %opcode = (
|
||||
@ -955,11 +915,11 @@ if ($flavour =~ /64/) { ######## 64-bit code
|
||||
}
|
||||
|
||||
foreach(split("\n",$code)) {
|
||||
s/\`([^\`]*)\`/eval($1)/geo;
|
||||
s/\`([^\`]*)\`/eval($1)/geo;
|
||||
|
||||
s/\b[wx]([0-9]+)\b/r$1/go; # new->old registers
|
||||
s/\bv([0-9])\.[12468]+[bsd]\b/q$1/go; # new->old registers
|
||||
s/\/\/\s?/@ /o; # new->old style commentary
|
||||
s/\/\/\s?/@ /o; # new->old style commentary
|
||||
|
||||
# fix up remainig new-style suffixes
|
||||
s/\{q([0-9]+)\},\s*\[(.+)\],#8/sprintf "{d%d},[$2]!",2*$1/eo or
|
||||
@ -971,9 +931,10 @@ if ($flavour =~ /64/) { ######## 64-bit code
|
||||
s/vdup\.32\s+(.*)/unvdup32($1)/geo or
|
||||
s/vmov\.32\s+(.*)/unvmov32($1)/geo or
|
||||
s/^(\s+)b\./$1b/o or
|
||||
s/^(\s+)mov\./$1mov/o or
|
||||
s/^(\s+)ret/$1bx\tlr/o;
|
||||
|
||||
print $_,"\n";
|
||||
print $_,"\n";
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user