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fix[265e_api]: Support cons_intra_pred_flag cfg

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Change-Id: I57d7df14086cab0a6019f77b7b4b6259f456455e
Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
This commit is contained in:
Yanjun Liao 2024-03-28 16:21:06 +08:00 committed by Herman Chen
parent b8c4c585e2
commit 25649d2fae
5 changed files with 18 additions and 2 deletions
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1
inc/rk_venc_cmd.h
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@ -987,6 +987,7 @@ typedef enum MppEncH265CfgChange_e {
MPP_ENC_H265_CFG_TILE_CHANGE = (1 << 22),
MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE = (1 << 23),
MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE = (1 << 24),
MPP_ENC_H265_CFG_CHANGE_CONST_INTRA = (1 << 25),
MPP_ENC_H265_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncH265CfgChange;

3
mpp/base/mpp_enc_cfg.cpp
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@ -246,6 +246,7 @@ public:
ENTRY(h265, lpf_acs_sli_en, U32, RK_U32, MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE, codec.h265, lpf_acs_sli_en) \
ENTRY(h265, lpf_acs_tile_disable, U32, RK_U32, MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE, codec.h265, lpf_acs_tile_disable) \
ENTRY(h265, auto_tile, S32, RK_S32, MPP_ENC_H265_CFG_TILE_CHANGE, codec.h265, auto_tile) \
ENTRY(h265, const_intra, S32, RK_S32, MPP_ENC_H265_CFG_CHANGE_CONST_INTRA, codec.h265, const_intra_pred) \
/* vp8 config */ \
ENTRY(vp8, qp_init, S32, RK_S32, MPP_ENC_RC_CFG_CHANGE_QP_INIT, rc, qp_init) \
ENTRY(vp8, qp_min, S32, RK_S32, MPP_ENC_RC_CFG_CHANGE_QP_RANGE, rc, qp_min) \
@ -382,7 +383,7 @@ MppEncCfgService::MppEncCfgService() :
MPP_RET ret;
RK_S32 i;
ret = mpp_trie_init(&trie, 1853, cfg_cnt);
ret = mpp_trie_init(&trie, 1872, cfg_cnt);
if (ret) {
mpp_err_f("failed to init enc cfg set trie\n");
return ;

13
mpp/codec/enc/h265/h265e_api.c
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@ -529,6 +529,19 @@ static MPP_RET h265e_proc_h265_cfg(MppEncH265Cfg *dst, MppEncH265Cfg *src)
if (change & MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE)
dst->lpf_acs_tile_disable = src->lpf_acs_tile_disable;
if ((change & MPP_ENC_H265_CFG_CHANGE_CONST_INTRA) &&
(dst->const_intra_pred != src->const_intra_pred)) {
RockchipSocType soc_type = mpp_get_soc_type();
if (soc_type != ROCKCHIP_SOC_RK3576 && src->const_intra_pred == 1) {
dst->const_intra_pred = 0;
mpp_log("warning: Only rk3576's HEVC encoder support constraint intra prediction flag = 1.");
} else
dst->const_intra_pred = src->const_intra_pred;
dst->change |= MPP_ENC_H265_CFG_CHANGE_CONST_INTRA;
}
/*
* NOTE: use OR here for avoiding overwrite on multiple config
* When next encoding is trigger the change flag will be clear

2
mpp/codec/enc/h265/h265e_ps.c
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@ -401,7 +401,7 @@ MPP_RET h265e_set_pps(H265eCtx *ctx, H265ePps *pps, H265eSps *sps)
{
MppEncH265Cfg *codec = &ctx->cfg->codec.h265;
MppEncRcCfg *rc = &ctx->cfg->rc;
pps->m_bConstrainedIntraPred = 0;
pps->m_bConstrainedIntraPred = codec->const_intra_pred;
pps->m_PPSId = 0;
pps->m_SPSId = 0;
pps->m_picInitQPMinus26 = 0;

1
mpp/hal/rkenc/h265e/hal_h265e_vepu510.c
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@ -1150,6 +1150,7 @@ static void vepu510_h265_set_slice_regs(H265eSyntax_new *syn, H265eVepu510Frame
regs->synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag;
regs->synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth;
regs->synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag;
regs->synt_pps.csip_flag = syn->pp.constrained_intra_pred_flag;
regs->synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg;
regs->synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg;