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156 lines
4.6 KiB
ReStructuredText
156 lines
4.6 KiB
ReStructuredText
Mesa 17.0.2 Release Notes / March 20, 2017
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==========================================
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Mesa 17.0.2 is a bug fix release which fixes bugs found since the 17.0.1
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release.
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Mesa 17.0.2 implements the OpenGL 4.5 API, but the version reported by
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glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
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glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being
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used. Some drivers don't support all the features required in OpenGL
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4.5. OpenGL 4.5 is **only** available if requested at context creation
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because compatibility contexts are not supported.
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SHA256 checksums
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----------------
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::
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2e0f41e7974ba7a36ca32bbeaf8ebcd65c8fd4d2dc9872f04d4becbd5e7a8cb5 mesa-17.0.2.tar.gz
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f8f191f909e01e65de38d5bdea5fb057f21649a3aed20948be02348e77a689d4 mesa-17.0.2.tar.xz
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New features
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------------
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None
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Bug fixes
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---------
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- `Bug 68504 <https://bugs.freedesktop.org/show_bug.cgi?id=68504>`__ -
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9.2-rc1 workaround for clover build failure on ppc/altivec: cannot
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convert 'bool' to '__vector(4) \__bool int' in return
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- `Bug 97988 <https://bugs.freedesktop.org/show_bug.cgi?id=97988>`__ -
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[radeonsi] playing back videos with VDPAU exhibits
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deinterlacing/anti-aliasing issues not visible with VA-API
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- `Bug 99484 <https://bugs.freedesktop.org/show_bug.cgi?id=99484>`__ -
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Crusader Kings 2 - Loading bars, siege bars, morale bars, etc. do not
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render correctly
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- `Bug 99715 <https://bugs.freedesktop.org/show_bug.cgi?id=99715>`__ -
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Don't print: "Note: Buggy applications may crash, if they do please
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report to vendor"
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- `Bug 100049 <https://bugs.freedesktop.org/show_bug.cgi?id=100049>`__
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- "ralloc: Make sure ralloc() allocations match malloc()'s
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alignment." causes seg fault in 32bit build
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Changes
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-------
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Alex Smith (3):
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- radv: Emit pending flushes before executing a secondary command
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buffer
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- radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBuffer
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- radv/ac: Fix shared memory offset calculation
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Bas Nieuwenhuizen (3):
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- radv: Disable HTILE for textures with multiple layers/levels.
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- radv: Emit cache flushes before CP DMA.
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- Revert "radv: Emit cache flushes before CP DMA."
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Dave Airlie (3):
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- radv: drop Z24 support.
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- radv: disable mip point pre clamping.
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- radv: setup llvm target data layout
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Emil Velikov (4):
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- docs: add sha256 checksums for 17.0.1
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- cherry-ignore: add the swizzle blorp_clear fix
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- i965: move brw_define.h ifndef guard to the top
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- Update version to 17.0.2
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Fredrik Höglund (2):
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- radv: fix the dynamic buffer index in vkCmdBindDescriptorSets
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- radv/ac: fix multiple descriptor sets with dynamic buffers
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Gregory Hainaut (1):
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- glapi: fix typo in count_scale
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Ilia Mirkin (2):
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- nvc0: take extra pushbuf space into account for pushbuf_space calls
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- nvc0: increase alignment to 256 for texture buffers on fermi
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Jacob Lifshay (1):
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- vulkan/wsi: Improve the DRI3 error message
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James Legg (1):
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- radv: Fix using more than 4 bound descriptor sets
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Jason Ekstrand (7):
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- anv/blorp/clear_subpass: Only set surface clear color for fast clears
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- anv: Accurately advertise dynamic descriptor limits
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- anv: Stall before fast-clear operations
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- anv: Properly handle destroying NULL devices and instances
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- anv/blorp: Turn off AUX after doing a CCS_D resolve
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- anv/blorp: Only set a clear color for resolves if fast-cleared
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- nir/intrinsics: Make load_barycentric_input take a 2-component coor
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Jonas Pfeil (1):
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- ralloc: Make sure ralloc() allocations match malloc()'s alignment.
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Kenneth Graunke (1):
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- egl: Ensure ResetNotificationStrategy matches for shared contexts.
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Marek Olšák (3):
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- st/mesa: reset sample_mask, min_sample, and render_condition for PBO
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ops
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- st/mesa: set blend state for PBO readbacks
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- radeonsi: mark all bound shader buffer ranges as initialized
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Matt Turner (1):
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- clover: Work around build failure with AltiVec.
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Nanley Chery (2):
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- anv/pass: Avoid accessing attachment array out of bounds
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- anv/image: Remove extra dependency on HiZ-specific variable
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Nicolai Hähnle (2):
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- st/glsl_to_tgsi: avoid iterating past the head of the instruction
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list
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- st/mesa: inform the driver of framebuffer changes before compute
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dispatches
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Robert Foss (1):
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- mesa: Avoid read of uninitialized variable
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Samuel Iglesias Gonsálvez (5):
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- i965/fs: mark last DF uniform array element as 64 bit live one
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- i965/fs: detect different bit size accesses to uniforms to push them
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in proper locations
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- i965/fs: fix indirect load DF uniforms on BSW/BXT
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- i965/fs: fix source type when emitting MOV_INDIRECT to read ICP
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handles
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- i965/fs: emit MOV_INDIRECT with the source with the right register
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type
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Samuel Pitoiset (1):
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- radeonsi: disable sinking common instructions down to the end block
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