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Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Brezillon Boris <boris.brezillon@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28241>
316 lines
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316 lines
14 KiB
ReStructuredText
Panfrost
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========
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The Panfrost driver stack includes an OpenGL ES implementation for Arm Mali
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GPUs based on the Midgard and Bifrost microarchitectures. It is **conformant**
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on Mali-G52 and Mali-G57 but **non-conformant** on other GPUs. The following
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hardware is currently supported:
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========= ============= ============ =======
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Product Architecture OpenGL ES OpenGL
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========= ============= ============ =======
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Mali T600 Midgard (v4) 2.0 2.1
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Mali T620 Midgard (v4) 2.0 2.1
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Mali T720 Midgard (v4) 2.0 2.1
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Mali T760 Midgard (v5) 3.1 3.1
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Mali T820 Midgard (v5) 3.1 3.1
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Mali T830 Midgard (v5) 3.1 3.1
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Mali T860 Midgard (v5) 3.1 3.1
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Mali T880 Midgard (v5) 3.1 3.1
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Mali G72 Bifrost (v6) 3.1 3.1
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Mali G31 Bifrost (v7) 3.1 3.1
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Mali G51 Bifrost (v7) 3.1 3.1
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Mali G52 Bifrost (v7) 3.1 3.1
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Mali G76 Bifrost (v7) 3.1 3.1
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Mali G57 Valhall (v9) 3.1 3.1
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Mali G310 Valhall (v10) 3.1 3.1
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Mali G610 Valhall (v10) 3.1 3.1
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========= ============= ============ =======
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Other Midgard and Bifrost chips (e.g. G71) are not yet supported.
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Older Mali chips based on the Utgard architecture (Mali 400, Mali 450) are
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supported in the :doc:`Lima <lima>` driver, not Panfrost. Lima is also
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available in Mesa.
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Other graphics APIs (Vulkan, OpenCL) are not supported at this time.
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Building
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--------
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Panfrost's OpenGL support is a Gallium driver. Since Mali GPUs are 3D-only and
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do not include a display controller, Mesa uses kmsro to support display
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controllers paired with Mali GPUs. If your board with a Panfrost supported GPU
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has a display controller with mainline Linux support not supported by kmsro,
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it's easy to add support, see the commit ``cff7de4bb597e9`` as an example.
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LLVM is *not* required by Panfrost's compilers. LLVM support in Mesa can
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safely be disabled for most OpenGL ES users with Panfrost.
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Build like ``meson . build/ -Dvulkan-drivers=
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-Dgallium-drivers=panfrost -Dllvm=disabled`` for a build directory
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``build``.
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For general information on building Mesa, read :doc:`the install documentation
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<../install>`.
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Chat
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----
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Panfrost developers and users hang out on IRC at ``#panfrost`` on OFTC. Note
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that registering and authenticating with ``NickServ`` is required to prevent
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spam. `Join the chat. <https://webchat.oftc.net/?channels=panfrost>`_
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Compressed texture support
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--------------------------
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In the driver, Panfrost supports ASTC, ETC, and all BCn formats (e.g. RGTC,
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S3TC, etc.) However, Panfrost depends on the hardware to support these formats
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efficiently. All supported Mali architectures support these formats, but not
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every system-on-chip with a Mali GPU support all these formats. Many lower-end
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systems lack support for some BCn formats, which can cause problems when playing
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desktop games with Panfrost. To check whether this issue applies to your
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system-on-chip, Panfrost includes a ``panfrost_texfeatures`` tool to query
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supported formats.
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To use this tool, include the option ``-Dtools=panfrost`` when configuring Mesa.
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Then inside your Mesa build directory, the tool is located at
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``src/panfrost/tools/panfrost_texfeatures``. Copy it to your target device,
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set as executable as necessary, and run on the target device. A table of
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supported formats will be printed to standard output.
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drm-shim
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--------
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Panfrost implements ``drm-shim``, stubbing out the Panfrost kernel interface.
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Use cases for this functionality include:
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- Future hardware bring up
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- Running shader-db on non-Mali workstations
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- Reproducing compiler (and some driver) bugs without Mali hardware
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Although Mali hardware is usually paired with an Arm CPU, Panfrost is portable C
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code and should work on any Linux machine. In particular, you can test the
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compiler on shader-db on an Intel desktop.
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To build Mesa with Panfrost drm-shim, configure Meson with
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``-Dgallium-drivers=panfrost`` and ``-Dtools=drm-shim``. See the above
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building section for a full invocation. The drm-shim binary will be built to
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``build/src/panfrost/drm-shim/libpanfrost_noop_drm_shim.so``.
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To use, set the ``LD_PRELOAD`` environment variable to the drm-shim binary. It
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may also be necessary to set ``LIBGL_DRIVERS_PATH`` to the location where Mesa
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was installed.
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By default, drm-shim mocks a Mali-G52 system. To select a specific Mali GPU,
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set the ``PAN_GPU_ID`` environment variable to the desired GPU ID:
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========= ============= =======
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Product Architecture GPU ID
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========= ============= =======
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Mali-T720 Midgard (v4) 720
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Mali-T860 Midgard (v5) 860
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Mali-G72 Bifrost (v6) 6221
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Mali-G52 Bifrost (v7) 7212
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Mali-G57 Valhall (v9) 9093
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Mali-G610 Valhall (v10) a867
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========= ============= =======
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Additional GPU IDs are enumerated in the ``panfrost_model_list`` list in
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``src/panfrost/lib/pan_props.c``.
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As an example: assuming Mesa is installed to a local path ``~/lib`` and Mesa's
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build directory is ``~/mesa/build``, a shader can be compiled for Mali-G52 as:
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.. code-block:: sh
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~/shader-db$ BIFROST_MESA_DEBUG=shaders \
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LIBGL_DRIVERS_PATH=~/lib/dri/ \
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LD_PRELOAD=~/mesa/build/src/panfrost/drm-shim/libpanfrost_noop_drm_shim.so \
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PAN_GPU_ID=7212 \
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./run shaders/glmark/1-1.shader_test
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The same shader can be compiled for Mali-T720 as:
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.. code-block:: sh
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~/shader-db$ MIDGARD_MESA_DEBUG=shaders \
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LIBGL_DRIVERS_PATH=~/lib/dri/ \
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LD_PRELOAD=~/mesa/build/src/panfrost/drm-shim/libpanfrost_noop_drm_shim.so \
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PAN_GPU_ID=720 \
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./run shaders/glmark/1-1.shader_test
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These examples set the compilers' ``shaders`` debug flags to dump the optimized
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NIR, backend IR after instruction selection, backend IR after register
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allocation and scheduling, and a disassembly of the final compiled binary.
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As another example, this invocation runs a single dEQP test "on" Mali-G52,
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pretty-printing GPU data structures and disassembling all shaders
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(``PAN_MESA_DEBUG=trace``) as well as dumping raw GPU memory
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(``PAN_MESA_DEBUG=dump``). The ``EGL_PLATFORM=surfaceless`` environment variable
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and various flags to dEQP mimic the surfaceless environment that our
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continuous integration (CI) uses. This eliminates window system dependencies,
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although it requires a specially built CTS:
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.. code-block:: sh
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~/VK-GL-CTS/build/external/openglcts/modules$ PAN_MESA_DEBUG=trace,dump \
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LIBGL_DRIVERS_PATH=~/lib/dri/ \
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LD_PRELOAD=~/mesa/build/src/panfrost/drm-shim/libpanfrost_noop_drm_shim.so \
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PAN_GPU_ID=7212 EGL_PLATFORM=surfaceless \
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./glcts --deqp-surface-type=pbuffer \
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--deqp-gl-config-name=rgba8888d24s8ms0 --deqp-surface-width=256 \
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--deqp-surface-height=256 -n \
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dEQP-GLES31.functional.shaders.builtin_functions.common.abs.float_highp_compute
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U-interleaved tiling
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---------------------
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Panfrost supports u-interleaved tiling. U-interleaved tiling is
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indicated by the ``DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED`` modifier.
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The tiling reorders whole pixels (blocks). It does not compress or modify the
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pixels themselves, so it can be used for any image format. Internally, images
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are divided into tiles. Tiles occur in source order, but pixels (blocks) within
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each tile are reordered according to a space-filling curve.
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For regular formats, 16x16 tiles are used. This harmonizes with the default tile
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size for binning and CRCs (transaction elimination). It also means a single line
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(16 pixels) at 4 bytes per pixel equals a single 64-byte cache line.
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For formats that are already block compressed (S3TC, RGTC, etc), 4x4 tiles are
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used, where entire blocks are reorder. Most of these formats compress 4x4
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blocks, so this gives an effective 16x16 tiling. This justifies the tile size
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intuitively, though it's not a rule: ASTC may uses larger blocks.
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Within a tile, the X and Y bits are interleaved (like Morton order), but with a
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twist: adjacent bit pairs are XORed. The reason to add XORs is not obvious.
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Visually, addresses take the form::
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| y3 | (x3 ^ y3) | y2 | (y2 ^ x2) | y1 | (y1 ^ x1) | y0 | (y0 ^ x0) |
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Reference routines to encode/decode u-interleaved images are available in
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``src/panfrost/shared/test/test-tiling.cpp``, which documents the space-filling
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curve. This reference implementation is used to unit test the optimized
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implementation used in production. The optimized implementation is available in
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``src/panfrost/shared/pan_tiling.c``.
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Although these routines are part of Panfrost, they are also used by Lima, as Arm
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introduced the format with Utgard. It is the only tiling supported on Utgard. On
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Mali-T760 and newer, Arm Framebuffer Compression (AFBC) is more efficient and
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should be used instead where possible. However, not all formats are
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compressible, so u-interleaved tiling remains an important fallback on Panfrost.
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Instancing
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----------
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The attribute descriptor lets the attribute unit compute the address of an
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attribute given the vertex and instance ID. Unfortunately, the way this works is
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rather complicated when instancing is enabled.
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To explain this, first we need to explain how compute and vertex threads are
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dispatched. When a quad is dispatched, it receives a single, linear index.
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However, we need to translate that index into a (vertex id, instance id) pair.
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One option would be to do:
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.. math::
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\text{vertex id} = \text{linear id} \% \text{num vertices}
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\text{instance id} = \text{linear id} / \text{num vertices}
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but this involves a costly division and modulus by an arbitrary number.
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Instead, we could pad num_vertices. We dispatch padded_num_vertices *
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num_instances threads instead of num_vertices * num_instances, which results
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in some "extra" threads with vertex_id >= num_vertices, which we have to
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discard. The more we pad num_vertices, the more "wasted" threads we
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dispatch, but the division is potentially easier.
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One straightforward choice is to pad num_vertices to the next power of two,
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which means that the division and modulus are just simple bit shifts and
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masking. But the actual algorithm is a bit more complicated. The thread
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dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
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to dividing by a power of two. As a result, padded_num_vertices can be
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1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
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since we need less padding.
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padded_num_vertices is picked by the hardware. The driver just specifies the
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actual number of vertices. Note that padded_num_vertices is a multiple of four
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(presumably because threads are dispatched in groups of 4). Also,
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padded_num_vertices is always at least one more than num_vertices, which seems
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like a quirk of the hardware. For larger num_vertices, the hardware uses the
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following algorithm: using the binary representation of num_vertices, we look at
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the most significant set bit as well as the following 3 bits. Let n be the
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number of bits after those 4 bits. Then we set padded_num_vertices according to
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the following table:
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========== =======================
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high bits padded_num_vertices
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========== =======================
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1000 :math:`9 \cdot 2^n`
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1001 :math:`5 \cdot 2^{n+1}`
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101x :math:`3 \cdot 2^{n+2}`
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110x :math:`7 \cdot 2^{n+1}`
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111x :math:`2^{n+4}`
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========== =======================
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For example, if num_vertices = 70 is passed to glDraw(), its binary
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representation is 1000110, so n = 3 and the high bits are 1000, and
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therefore padded_num_vertices = :math:`9 \cdot 2^3` = 72.
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The attribute unit works in terms of the original linear_id. if
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num_instances = 1, then they are the same, and everything is simple.
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However, with instancing things get more complicated. There are four
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possible modes, two of them we can group together:
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1. Use the linear_id directly. Only used when there is no instancing.
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2. Use the linear_id modulo a constant. This is used for per-vertex
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attributes with instancing enabled by making the constant equal
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padded_num_vertices. Because the modulus is always padded_num_vertices, this
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mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
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The shift field specifies the power of two, while the extra_flags field
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specifies the odd number. If shift = n and extra_flags = m, then the modulus
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is :math:`(2m + 1) \cdot 2^n`. As an example, if num_vertices = 70, then as
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computed above, padded_num_vertices = :math:`9 \cdot 2^3`, so we should set
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extra_flags = 4 and shift = 3. Note that we must exactly follow the hardware
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algorithm used to get padded_num_vertices in order to correctly implement
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per-vertex attributes.
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3. Divide the linear_id by a constant. In order to correctly implement
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instance divisors, we have to divide linear_id by padded_num_vertices times
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to user-specified divisor. So first we compute padded_num_vertices, again
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following the exact same algorithm that the hardware uses, then multiply it
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by the GL-level divisor to get the hardware-level divisor. This case is
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further divided into two more cases. If the hardware-level divisor is a
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power of two, then we just need to shift. The shift amount is specified by
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the shift field, so that the hardware-level divisor is just
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:math:`2^\text{shift}`.
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If it isn't a power of two, then we have to divide by an arbitrary integer.
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For that, we use the well-known technique of multiplying by an approximation
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of the inverse. The driver must compute the magic multiplier and shift
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amount, and then the hardware does the multiplication and shift. The
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hardware and driver also use the "round-down" optimization as described in
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https://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
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The hardware further assumes the multiplier is between :math:`2^{31}` and
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:math:`2^{32}`, so the high bit is implicitly set to 1 even though it is set
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to 0 by the driver -- presumably this simplifies the hardware multiplier a
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little. The hardware first multiplies linear_id by the multiplier and
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takes the high 32 bits, then applies the round-down correction if
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extra_flags = 1, then finally shifts right by the shift field.
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There are some differences between ridiculousfish's algorithm and the Mali
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hardware algorithm, which means that the reference code from ridiculousfish
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doesn't always produce the right constants. Mali does not use the pre-shift
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optimization, since that would make a hardware implementation slower (it
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would have to always do the pre-shift, multiply, and post-shift operations).
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It also forces the multiplier to be at least :math:`2^{31}`, which means
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that the exponent is entirely fixed, so there is no trial-and-error.
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Altogether, given the divisor d, the algorithm the driver must follow is:
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1. Set shift = :math:`\lfloor \log_2(d) \rfloor`.
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2. Compute :math:`m = \lceil 2^{shift + 32} / d \rceil` and :math:`e = 2^{shift + 32} % d`.
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3. If :math:`e <= 2^{shift}`, then we need to use the round-down algorithm. Set
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magic_divisor = m - 1 and extra_flags = 1. 4. Otherwise, set magic_divisor =
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m and extra_flags = 0.
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