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8dc3c91a5c
From drm-next at the following commit:
commit 2a7005c8a3982ba27fab237d85c27da446484e9c (HEAD)
Merge: 0666cba1f5b2b 47c65b3853f88
Author: Dave Airlie <airlied@redhat.com>
Date: Fri Jun 11 13:34:42 2021 +1000
Merge tag 'drm-intel-gt-next-2021-06-10' of...
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599>
301 lines
12 KiB
C
301 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright (C) 2015 Etnaviv Project
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ETNAVIV_DRM_H__
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#define __ETNAVIV_DRM_H__
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/* Please note that modifications to all structs defined here are
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* subject to backwards-compatibility constraints:
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* 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
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* user/kernel compatibility
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* 2) Keep fields aligned to their size
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* 3) Because of how drm_ioctl() works, we can add new fields at
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* the end of an ioctl if some care is taken: drm_ioctl() will
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* zero out the new fields at the tail of the ioctl, so a zero
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* value should have a backwards compatible meaning. And for
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* output params, userspace won't see the newly added output
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* fields.. so that has to be somehow ok.
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*/
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/* timeouts are specified in clock-monotonic absolute times (to simplify
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* restarting interrupted ioctls). The following struct is logically the
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* same as 'struct timespec' but 32/64b ABI safe.
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*/
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struct drm_etnaviv_timespec {
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__s64 tv_sec; /* seconds */
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__s64 tv_nsec; /* nanoseconds */
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};
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#define ETNAVIV_PARAM_GPU_MODEL 0x01
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#define ETNAVIV_PARAM_GPU_REVISION 0x02
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#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
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#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
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#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
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#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
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#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
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#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
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#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
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#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a
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#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b
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#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c
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#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d
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#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e
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#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f
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#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
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#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
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#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
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#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
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#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
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#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
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#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
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#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
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#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
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#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
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#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
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#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
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#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
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#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
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#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
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#define ETNA_MAX_PIPES 4
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struct drm_etnaviv_param {
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__u32 pipe; /* in */
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__u32 param; /* in, ETNAVIV_PARAM_x */
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__u64 value; /* out (get_param) or in (set_param) */
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};
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/*
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* GEM buffers:
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*/
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#define ETNA_BO_CACHE_MASK 0x000f0000
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/* cache modes */
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#define ETNA_BO_CACHED 0x00010000
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#define ETNA_BO_WC 0x00020000
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#define ETNA_BO_UNCACHED 0x00040000
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/* map flags */
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#define ETNA_BO_FORCE_MMU 0x00100000
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struct drm_etnaviv_gem_new {
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__u64 size; /* in */
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__u32 flags; /* in, mask of ETNA_BO_x */
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__u32 handle; /* out */
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};
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struct drm_etnaviv_gem_info {
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__u32 handle; /* in */
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__u32 pad;
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__u64 offset; /* out, offset to pass to mmap() */
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};
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#define ETNA_PREP_READ 0x01
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#define ETNA_PREP_WRITE 0x02
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#define ETNA_PREP_NOSYNC 0x04
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struct drm_etnaviv_gem_cpu_prep {
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__u32 handle; /* in */
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__u32 op; /* in, mask of ETNA_PREP_x */
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struct drm_etnaviv_timespec timeout; /* in */
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};
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struct drm_etnaviv_gem_cpu_fini {
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__u32 handle; /* in */
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__u32 flags; /* in, placeholder for now, no defined values */
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};
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/*
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* Cmdstream Submission:
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*/
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/* The value written into the cmdstream is logically:
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* relocbuf->gpuaddr + reloc_offset
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*
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* NOTE that reloc's must be sorted by order of increasing submit_offset,
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* otherwise EINVAL.
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*/
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struct drm_etnaviv_gem_submit_reloc {
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__u32 submit_offset; /* in, offset from submit_bo */
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__u32 reloc_idx; /* in, index of reloc_bo buffer */
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__u64 reloc_offset; /* in, offset from start of reloc_bo */
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__u32 flags; /* in, placeholder for now, no defined values */
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};
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/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
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* cmdstream buffer(s) themselves or reloc entries) has one (and only
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* one) entry in the submit->bos[] table.
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*
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* As a optimization, the current buffer (gpu virtual address) can be
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* passed back through the 'presumed' field. If on a subsequent reloc,
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* userspace passes back a 'presumed' address that is still valid,
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* then patching the cmdstream for this entry is skipped. This can
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* avoid kernel needing to map/access the cmdstream bo in the common
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* case.
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* If the submit is a softpin submit (ETNA_SUBMIT_SOFTPIN) the 'presumed'
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* field is interpreted as the fixed location to map the bo into the gpu
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* virtual address space. If the kernel is unable to map the buffer at
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* this location the submit will fail. This means userspace is responsible
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* for the whole gpu virtual address management.
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*/
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#define ETNA_SUBMIT_BO_READ 0x0001
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#define ETNA_SUBMIT_BO_WRITE 0x0002
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struct drm_etnaviv_gem_submit_bo {
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__u32 flags; /* in, mask of ETNA_SUBMIT_BO_x */
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__u32 handle; /* in, GEM handle */
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__u64 presumed; /* in/out, presumed buffer address */
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};
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/* performance monitor request (pmr) */
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#define ETNA_PM_PROCESS_PRE 0x0001
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#define ETNA_PM_PROCESS_POST 0x0002
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struct drm_etnaviv_gem_submit_pmr {
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__u32 flags; /* in, when to process request (ETNA_PM_PROCESS_x) */
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__u8 domain; /* in, pm domain */
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__u8 pad;
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__u16 signal; /* in, pm signal */
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__u32 sequence; /* in, sequence number */
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__u32 read_offset; /* in, offset from read_bo */
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__u32 read_idx; /* in, index of read_bo buffer */
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};
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/* Each cmdstream submit consists of a table of buffers involved, and
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* one or more cmdstream buffers. This allows for conditional execution
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* (context-restore), and IB buffers needed for per tile/bin draw cmds.
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*/
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#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
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#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
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#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
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#define ETNA_SUBMIT_SOFTPIN 0x0008
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#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \
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ETNA_SUBMIT_FENCE_FD_IN | \
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ETNA_SUBMIT_FENCE_FD_OUT| \
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ETNA_SUBMIT_SOFTPIN)
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#define ETNA_PIPE_3D 0x00
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#define ETNA_PIPE_2D 0x01
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#define ETNA_PIPE_VG 0x02
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struct drm_etnaviv_gem_submit {
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__u32 fence; /* out */
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__u32 pipe; /* in */
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__u32 exec_state; /* in, initial execution state (ETNA_PIPE_x) */
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__u32 nr_bos; /* in, number of submit_bo's */
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__u32 nr_relocs; /* in, number of submit_reloc's */
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__u32 stream_size; /* in, cmdstream size */
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__u64 bos; /* in, ptr to array of submit_bo's */
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__u64 relocs; /* in, ptr to array of submit_reloc's */
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__u64 stream; /* in, ptr to cmdstream */
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__u32 flags; /* in, mask of ETNA_SUBMIT_x */
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__s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
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__u64 pmrs; /* in, ptr to array of submit_pmr's */
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__u32 nr_pmrs; /* in, number of submit_pmr's */
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__u32 pad;
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};
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/* The normal way to synchronize with the GPU is just to CPU_PREP on
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* a buffer if you need to access it from the CPU (other cmdstream
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* submission from same or other contexts, PAGE_FLIP ioctl, etc, all
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* handle the required synchronization under the hood). This ioctl
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* mainly just exists as a way to implement the gallium pipe_fence
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* APIs without requiring a dummy bo to synchronize on.
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*/
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#define ETNA_WAIT_NONBLOCK 0x01
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struct drm_etnaviv_wait_fence {
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__u32 pipe; /* in */
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__u32 fence; /* in */
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__u32 flags; /* in, mask of ETNA_WAIT_x */
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__u32 pad;
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struct drm_etnaviv_timespec timeout; /* in */
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};
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#define ETNA_USERPTR_READ 0x01
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#define ETNA_USERPTR_WRITE 0x02
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struct drm_etnaviv_gem_userptr {
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__u64 user_ptr; /* in, page aligned user pointer */
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__u64 user_size; /* in, page aligned user size */
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__u32 flags; /* in, flags */
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__u32 handle; /* out, non-zero handle */
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};
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struct drm_etnaviv_gem_wait {
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__u32 pipe; /* in */
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__u32 handle; /* in, bo to be waited for */
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__u32 flags; /* in, mask of ETNA_WAIT_x */
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__u32 pad;
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struct drm_etnaviv_timespec timeout; /* in */
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};
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/*
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* Performance Monitor (PM):
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*/
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struct drm_etnaviv_pm_domain {
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__u32 pipe; /* in */
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__u8 iter; /* in/out, select pm domain at index iter */
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__u8 id; /* out, id of domain */
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__u16 nr_signals; /* out, how many signals does this domain provide */
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char name[64]; /* out, name of domain */
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};
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struct drm_etnaviv_pm_signal {
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__u32 pipe; /* in */
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__u8 domain; /* in, pm domain index */
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__u8 pad;
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__u16 iter; /* in/out, select pm source at index iter */
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__u16 id; /* out, id of signal */
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char name[64]; /* out, name of domain */
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};
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#define DRM_ETNAVIV_GET_PARAM 0x00
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/* placeholder:
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#define DRM_ETNAVIV_SET_PARAM 0x01
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*/
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#define DRM_ETNAVIV_GEM_NEW 0x02
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#define DRM_ETNAVIV_GEM_INFO 0x03
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#define DRM_ETNAVIV_GEM_CPU_PREP 0x04
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#define DRM_ETNAVIV_GEM_CPU_FINI 0x05
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#define DRM_ETNAVIV_GEM_SUBMIT 0x06
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#define DRM_ETNAVIV_WAIT_FENCE 0x07
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#define DRM_ETNAVIV_GEM_USERPTR 0x08
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#define DRM_ETNAVIV_GEM_WAIT 0x09
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#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a
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#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b
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#define DRM_ETNAVIV_NUM_IOCTLS 0x0c
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#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
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#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
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#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
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#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
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#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
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#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
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#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
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#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
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#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
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#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
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#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ETNAVIV_DRM_H__ */
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