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Samuel Pitoiset
af1cd45858 gitlab-ci: enable building the test image for VK unconditionally 
It was diabled because RADV is the only driver that tests Vulkan
and running CTS on my personal machine and without recovery is
not safe enough for CI (too long and too unstable).

Now that we are going to test Fossilize with RADV, it's needed to
build the test image for VK unconditionally. As RADV now supports
creating NULL devices, the fossilize jobs can run everywhere.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3960>
 2020-03-05 20:33:56 +00:00
Samuel Pitoiset
1cdb6edbe6 gitlab-ci: add Fossilize support to detect compiler regressions 
Fossilize is equivalent to vkpipeline-db but it's definitely more
robust. This is based on the CI traces system.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3960>
 2020-03-05 20:33:56 +00:00
Samuel Pitoiset
93fcc9ad57 gitlab-ci: build Fossilize in the test image for VK 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3960>
 2020-03-05 20:33:56 +00:00
Rhys Perry
b088a4b113 aco: only reserve sgprs for vcc if it's used 
pipeline-db (Vega):

Totals:
SGPRS: 5186302 -> 5075616 (-2.13 %)
VGPRS: 3704580 -> 3704580 (0.00 %)
Spilled SGPRs: 144859 -> 144859 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 4124 -> 4124 (0.00 %) dwords per thread
Code Size: 247315944 -> 247315944 (0.00 %) bytes
LDS: 1311 -> 1311 (0.00 %) blocks
Max Waves: 674560 -> 674562 (0.00 %)

Totals from affected shaders:
SGPRS: 536992 -> 426306 (-20.61 %)
VGPRS: 356404 -> 356404 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 8498748 -> 8498748 (0.00 %) bytes
LDS: 8 -> 8 (0.00 %) blocks
Max Waves: 113832 -> 113834 (0.00 %)

There are some small code size changes in a few RotTR shaders and a small
increase in max_waves in two Detroit: Become Human shaders.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3906>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3906>
 2020-03-05 20:18:34 +00:00
Rhys Perry
c6e0c062da aco: improve control flow handling in GFX6-9 NOP pass 
Fixes Detroit: Become Human hang. Also affects World of Warships.

pipeline-db (Tahiti):
Totals from affected shaders:
SGPRS: 0 -> 0 (0.00 %)
VGPRS: 0 -> 0 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)

pipeline-db (Polaris):
Totals from affected shaders:
SGPRS: 17168 -> 17168 (0.00 %)
VGPRS: 11296 -> 11296 (0.00 %)
Spilled SGPRs: 1870 -> 1870 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 1472628 -> 1473292 (0.05 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 628 -> 628 (0.00 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 17168 -> 17168 (0.00 %)
VGPRS: 11296 -> 11296 (0.00 %)
Spilled SGPRs: 1870 -> 1870 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 1409716 -> 1410380 (0.05 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)

Max Waves is lower than it should be because of a null winsys bug.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4004>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4004>
 2020-03-05 19:37:24 +00:00
Rhys Perry
47b7f104a0 aco: consider non-hazard writes in handle_raw_hazard_internal 
I think this helps GFX6 in particular because code like this is common:
s_add_i32       s4, 0x60, s3
s_mov_b32       s5, 0
s_load_dwordx4  s[4:7], s[4:5], 0x0
s_buffer_load_dword s4, s[4:7], 0xcc

pipeline-db (Tahiti):
Totals from affected shaders:
SGPRS: 1923878 -> 1923878 (0.00 %)
VGPRS: 1528964 -> 1528964 (0.00 %)
Spilled SGPRs: 476 -> 476 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 88723604 -> 88528880 (-0.22 %) bytes
LDS: 241 -> 241 (0.00 %) blocks
Max Waves: 145402 -> 145402 (0.00 %)

pipeline-db (Polaris):
Totals from affected shaders:
SGPRS: 428128 -> 428128 (0.00 %)
VGPRS: 353092 -> 353092 (0.00 %)
Spilled SGPRs: 119251 -> 119251 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 57580468 -> 57563964 (-0.03 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 11631 -> 11631 (0.00 %)

piepline-db (Vega):
Totals from affected shaders:
SGPRS: 425016 -> 425016 (0.00 %)
VGPRS: 349588 -> 349588 (0.00 %)
Spilled SGPRs: 117835 -> 117835 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 54890792 -> 54874432 (-0.03 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 54 -> 54 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4004>
 2020-03-05 19:37:24 +00:00
Rhys Perry
38743577f8 aco: improve get_wait_states() 
pipeline-db (Tahiti):
Totals from affected shaders:
SGPRS: 21208 -> 21208 (0.00 %)
VGPRS: 22388 -> 22388 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 3278596 -> 3277004 (-0.05 %) bytes
LDS: 19 -> 19 (0.00 %) blocks
Max Waves: 238 -> 238 (0.00 %)

pipeline-db (Polaris):
Totals from affected shaders:
SGPRS: 64 -> 64 (0.00 %)
VGPRS: 96 -> 96 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 5200 -> 5192 (-0.15 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 10 -> 10 (0.00 %)

pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 0 -> 0 (0.00 %)
VGPRS: 0 -> 0 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4004>
 2020-03-05 19:37:24 +00:00
Rhys Perry
7f1b537304 aco: add new NOP insertion pass for GFX6-9 
This new pass is more similar to the GFX10 pass and should be able to
handle control flow better.

No pipeline-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4004>
 2020-03-05 19:37:24 +00:00
Jason Ekstrand
ce19681257 iris: Enable HiZ and stencil CCS for blorp blit destinations 
Now that blorp blits write to depth and stencil as depth and stencil, we
can leave HiZ and stencil CCS enabled for blorp blit destinations.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
 2020-03-05 18:56:45 +00:00
Jason Ekstrand
a0d5c7da18 iris: Enable CCS for copies from HiZ+CCS depth buffers 
Ever since b274469daa, BLORP is able to sample from whatever the
sampler supports.  In c0c899cf78, we added HiZ support for copies from
HiZ compressed depth buffers but forgot HiZ+CCS.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
 2020-03-05 18:56:45 +00:00
Jason Ekstrand
83b641a038 anv: Enable HiZ for VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL 
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
 2020-03-05 18:56:45 +00:00
Jason Ekstrand
6cec618e82 blorp: Write to depth/stencil images as depth/stencil when possible 
On Gen4 and G45 and earlier, we have to handle weird offsetting to write
to depth and stencil due to a lack of proper depth mipmapping support in
hardware.  On Gen6, we have to deal with strange HiZ and stencil
layouts.  Prior to Gen9, we also had to do crazy things for stencil
writes because we didn't support GL_ARB_shader_stencil_export and
friends in hardware.  However, starting with Gen7 for depth and Gen9 for
stencil, we can easily write out with the "right" hardware.  This allows
us to leave HiZ and other compression enabled for blorp_blit() and
blorp_copy() operations.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
 2020-03-05 18:56:45 +00:00
Jason Ekstrand
4531f0ffce iris: Allow HiZ on blit sources 
Ever since 95cc5438eb, BLORP has been able to read from HiZ-compressed
depth buffers as long as the sampler supports HiZ.  This just makes iris
stop doing the unneeded resolve.

Closes: #2583
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
 2020-03-05 18:56:45 +00:00
Jason Ekstrand
9f5f4269a6 isl: Set 3DSTATE_DEPTH_BUFFER::Depth correctly for 3D surfaces 
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
 2020-03-05 18:56:45 +00:00
Dylan Baker
07f1ef5656 docs: Update stable process around using fixes: and gitlab 
Currently the docs still recommend using
mesa-stable@lists.freedesktop.org, which is pretty awful. We really
don't want a second mailing list and it's mostly full of junk because of
CC: tags anyway.

This changes the preferred actions to be:
1) use a fixes: tag ahead of time
2) use a Cc tag ahead of time if fixes isn't appropriate
3) Use a gitlab MR against the staging/ branch for post-merge/backport
   nominations

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3056>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3056>
 2020-03-05 18:24:14 +00:00
Jonathan Marek
55dac91adc turnip: fix tile->slot calculation 
Fixes HW binning cases when the horizontal number of tiles isn't divisible
by the horizontal number of pipes (only happens with more than 32 tiles).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3142>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3142>
 2020-03-05 12:53:29 -05:00
Jonathan Marek
036230341f turnip: improve binning pipe layout config 
The old code looks the same as GL driver, but we get things like
pipe_count = {32, 1}, which seems bad.

This uses similar logic as for tiles which produces a balanced pipe_count
width/height.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3142>
 2020-03-05 12:48:12 -05:00
Kristian H. Kristensen
9f9432d56c Revert "spirv: Use a simpler and more correct implementaiton of tanh()" 
This reverts commit da1c49171d.

The reduced formula has precision problems on fp16 around 0.  Bring
back the old formula, but make sure to keep the clamping.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4054>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4054>
 2020-03-05 15:23:31 +00:00
Kristian H. Kristensen
986e92f0ea Revert "glsl: Use a simpler formula for tanh" 
This reverts commit 9807f502eb.

The simplified formula doesn't pass the tanh dEQP tests when we lower
to fp16 math.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4054>
 2020-03-05 15:23:31 +00:00
Alyssa Rosenzweig
bc5724faf4 pan/bi: Add bi_print_shader 
Woot! That's the last of it! IR printing is now complete*

*until the IR gets updated when new shiny things are added.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c152d4c835 pan/bi: Add bi_print_block 
Almost there...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c316d1553b pan/bi: Add bi_print_clause 
Again for post-sched purposes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
919cdf15b3 pan/bi: Add bi_print_bundle for printing bi_bundle 
Post-schedule, nops are significnat here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
bde54cb6d3 pan/bi: Add bi_instruction printing 
So we can debug the IR in memory before code emit has happened. We'd
like to have a complete dump of the IR -- neglecting this with Midgard
was one of those mistakes I've regretted so let's get this right for the
first time around.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
aef0f00cbc pan/bi: Move bi_interp_mode_name to bi_print 
Instead of open-coding it in the middle of the disassembler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
5d16a8109c pan/bi: Add BIR manipulation routines to bir.c 
New file.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
5f7a3ba872 pan/bi: Move some print routines out of the disasm 
These are generally useful for debug of the compiler IR even prior to
code emit; let's share these.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
8ec671801a pan/bi: Add IR iteration macros 
Copypaste from Midgard, for the most part.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
0b26cb194c pan/bi: Add quirks system 
Modeled after the Midgard system. Already we know of two
compiler-visible differences between G52 and G71, so let's keep track so
we can eventually port the compiler to other Bifrost systems.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
07228a6895 pan/bi: Add high-latency property for classes 
This is required to know how to schedule legally, and also influences
some issues relating to RA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
546c301ff6 pan/bi: Add CSEL condition 
Along with src_types, this is enough to represent CSEL.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
47451bb9f1 pan/bi: Add bi_branch data 
For BI_BRANCH, of course. Meshes well with the cfg.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
73c91f14c9 pan/bi: Extract bifrost_branch structure 
It's in the disassembler as bitfields, let's extract to a proper
structure so we can see what's there.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
2afddc4433 pan/bi: Add pred/successors to build CFG 
We'll want this for analysis passes or something, probably.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
d3370bd5a5 pan/bi: Add constants to bi_clause 
Scheduling will have to pay attention to this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
cb3cd8aa56 pan/bi: Add EXTRACT, MAKE_VEC synthetic ops 
These allow translating between the vector I/O and scalar ALUs,
facilitated by an RA dance to ensured contiguous registers are used.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
8929fe0c84 pan/bi: Add source type for conversions 
We should now be able to unambiguously represent conversions.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
5896db9578 pan/bi: Add swizzles 
Requires a new field on bifrost_instruction, as well as a new class
property and a new class for the dedicated swizzle ops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c70a198f24 pan/bi: Clarify special op scheduling 
They're encoded on ADD but eat the full cycle.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
fba1d12742 pan/bi: Add clause header fields to bi_clause 
These will be filled out during scheduling (and possibly RA), to be used
when emitting code.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
44ebc275fe pan/bi: Add class-specific ops 
For disambiguating things like min and max within the MINMAX class.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
b5bdd89444 pan/bi: Add constant field to bi_instruction 
Now that we can index it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
a2c1265dd3 pan/bi: Add special indices 
For fixed registers, uniforms, and constants, which bypass the usual SSA
mechanism to map well to the ISA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c42002d26f pan/bi: Add dest_type field to bifrost_instruction 
A number of opcodes within a class are disambiguated by type/size, and
whether modifiers make sense or not depends on whether the instruction
acts like a float.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
a35854c5ee pan/bi: Add bi_clause, bi_bundle abstractions 
These will be used during and after scheduling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
99f3c1f34c pan/bi: Add PAN_SCHED_* flags 
Class (mostly) determines scheduling options.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
9643b9dd5b pan/bi: Add bi_load_vary structure 
For ld_vary in the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
6a7987aba1 pan/bi: Pull out bifrost_load_var 
We're not using this structure yet but we want everything in the ISA
ready for us.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
aa2f12de56 pan/bi: Add bi_load structure 
Fills out the class for LD_ATTR, LD_VAR_ADDR

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
b93aec6df1 pan/bi: Add bifrost_minmax_mode field 
We'll open up a union for class specific data, since this is interesting
only to BI_MINMAX. (And even then...)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00